TW498521B - Semiconductor package with enhanced heat-dissipation efficiency - Google Patents

Semiconductor package with enhanced heat-dissipation efficiency Download PDF

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Publication number
TW498521B
TW498521B TW090118971A TW90118971A TW498521B TW 498521 B TW498521 B TW 498521B TW 090118971 A TW090118971 A TW 090118971A TW 90118971 A TW90118971 A TW 90118971A TW 498521 B TW498521 B TW 498521B
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TW
Taiwan
Prior art keywords
semiconductor package
substrate
heat sink
heat
wafer
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Application number
TW090118971A
Other languages
Chinese (zh)
Inventor
Tzung-Da He
Jian-Ping Huang
Original Assignee
Siliconware Precision Industries Co Ltd
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Priority to TW090118971A priority Critical patent/TW498521B/en
Application granted granted Critical
Publication of TW498521B publication Critical patent/TW498521B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

There is provided a semiconductor package with enhanced heat-dissipation efficiency, which comprises at least one die attached to a substrate formed thereon at least one die-attach region defined therein a plurality of thermal vias passing through the substrate, such that the top of the thermal vias can be connected to the die attached to the substrate, and the bottom thereof is connected to the thermal pad formed below the substrate and corresponding to the die-attach region. The thermal pad has a surface directly exposed to the atmosphere. Therefore, the heat generated by the die can be dissipated to the atmosphere via the thermal vias and the exposed surface of the thermal pad, so as to effectively increase the heat dissipating efficiency of the semiconductor package.

Description

498521 A7 ___ B7 五、發明說明（1 ) [發明領域] 本發明係關於一種半導體封裝件，尤指一種具有散熱 元件以提升散熱效率之半導體封裝件。 [背景說明] 球栅陣列（Ball Grid Array，以下略稱為“bga”）半 導體封裝件由於係以較多數量之銲球（s〇lder Balls)為晶片 之輸入/輸出連結端（I/O Connections)，故能適用於高度積 體化（High Integration)之晶片。惟，積體化程度越高之晶 片於運作時所產生之熱量越高，遂使如何有效逸散晶片所 產生之熱量成為BG A半導體封裝件在設計上之一大課 題。 解決散熱效率之方式有許多種，其中一種係如美國專 利第5,216,278號案中所提出之半導體封裝件。該種bga 半導體封裝件係在基板對應於晶片之底面上植接有多數之 散熱銲球（Thermal Balls)，以藉該散熱銲球將晶片產生之 熱i傳遞至與該半導體封裝件接連之印刷電路板（pCB) 上、此種結構雖可提升散熱效率，惟基板底面上可供散熱 |銲球植接之面積有限，使散熱銲球之植接數量受限而遂影 ^ 響散熱效率之提升。 | 針對於此，美國專利第5,642,261號案乃提出一種於 |基板上嵌設有一散熱片之半導體封裝件，以藉該散熱片所 | ，、有之較大散熱面積，改善前揭美國專利第5,216,278號 _案之散熱效率之提升會受限的問題。然而，如第6圖所示， ϊ I該種半裝件須於基板10上開設一貫穿該基板H)之 本紙張&度適用中 1國家標準（Cn3a_:!規格⑵。X 297公Ϊ )---- 1 16382 (請先閱讀背面之注意事項再填寫本頁) 訂· .線' 498521 - A7 ----- B7 五、發明說明（2 ) 嵌孔100，俾供一散熱片U嵌設其中，以讓晶片12與散 熱片11相接而將晶片12產生之熱量直接由散熱片^逸 散至大氣中’惟基板1〇須開設嵌孔1〇〇除會導致製造成 本增加，同時，因基板10之熱膨脹係數（c〇effieient 〇f Thermal Expansion)與散熱片u之熱膨脹係數有顯著之差 異’在在會在溫度循環（Temperature Cycle)及信賴性驗證 (Reliability Test)中所產生之熱應力效應導致基板1〇與散 μ熱片Π之接合面出現裂痕（Crack)，使外界之溼氣得由基 板10與散熱片11間產生之裂隙而進入該封裝件内部，致 而影響至是種半導體封裝件之信賴性。 [發明概述] 本發明之目的即在提供一種半導體封裝件，使晶片所 產生之熱里知直接由散熱片逸散至大氣中，而散熱片與基 板之接設毋須於基板上開孔，故可避免製造成本的增加， 且該散熱片得提供足夠之散熱面積以使晶片所產生之熱量 &得有效逸散。 為達成上揭及其它目的，本發明之半導體封裝件係包 括：一基板，其具有一頂面及一相對之底面，於該頂面上 預設有至少一晶片黏置區，於該晶片黏置區内並開設有複 數貫穿該基板之散熱貫孔，且於該基板之底面上對應至該 晶片黏置區之處形成有一散熱墊，使該散熱墊與該基板之 :散熱貫孔相接；至少一黏置於該基板之晶片黏置區上之晶 片’並使該晶片與基板電性連接；複數電性連接至該基板 1 底面上之導電連接元件，以供晶片與外界裝置電性連接； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意事項再填寫本頁}498521 A7 ___ B7 V. Description of the Invention (1) [Field of Invention] The present invention relates to a semiconductor package, and more particularly to a semiconductor package having a heat dissipation element to improve heat dissipation efficiency. [Background] Ball Grid Array (hereinafter abbreviated as "bga") semiconductor package uses a larger number of solder balls as input / output terminals (I / O Connections), so it can be applied to high integration (High Integration) chips. However, the higher the degree of integration, the higher the heat generated by the wafer during operation, so how to effectively dissipate the heat generated by the wafer has become a major issue in the design of BG A semiconductor packages. There are many ways to solve the heat dissipation efficiency, and one of them is a semiconductor package as proposed in U.S. Patent No. 5,216,278. This type of bga semiconductor package is implanted with a large number of thermal balls on the bottom surface of the substrate corresponding to the wafer, so that the heat generated by the wafer is transferred to the printing connected to the semiconductor package through the thermal balls. On the circuit board (pCB), although this structure can improve heat dissipation efficiency, the bottom surface of the substrate can be used for heat dissipation. The area of solder ball implantation is limited, which limits the number of heat sinking solder ball implantations. Promotion. In response, U.S. Patent No. 5,642,261 proposes a semiconductor package with a heat sink embedded on the substrate to borrow from the heat sink, which has a larger heat dissipation area and improves the previously disclosed U.S. Patent No. No. 5,216,278 _ the problem that the improvement of heat dissipation efficiency will be limited. However, as shown in FIG. 6, ϊI This kind of half-assembly must be provided on the substrate 10 with a paper & degree applicable to the national 1 standard (Cn3a_ :! specifications ⑵. X 297) ) ---- 1 16382 (Please read the precautions on the back before filling in this page) Order ·. Thread '498521-A7 ----- B7 V. Description of the invention (2) Embedded hole 100, for a heat sink U is embedded therein, so that the heat generated by the wafer 12 is directly radiated from the heat sink ^ to the chip 12 and the heat sink 11 to dissipate the heat into the atmosphere. However, the substrate 10 must be provided with an embedded hole 100, which will increase the manufacturing cost. At the same time, there is a significant difference between the thermal expansion coefficient of the substrate 10 (coefficient thermal expansion) and the thermal expansion coefficient of the heat sink u 'in the temperature cycle (Temperature Cycle) and reliability test (Reliability Test) The generated thermal stress effect causes cracks on the joint surface of the substrate 10 and the heat dissipation sheet Π, so that external moisture can enter the interior of the package through the cracks generated between the substrate 10 and the heat sink 11 and cause This affects the reliability of a semiconductor package. [Summary of the Invention] The object of the present invention is to provide a semiconductor package, so that the heat generated by the wafer is directly dissipated from the heat sink to the atmosphere, and the connection between the heat sink and the substrate does not require a hole in the substrate, so An increase in manufacturing cost can be avoided, and the heat sink must provide a sufficient heat dissipation area so that the heat & generated by the chip can be efficiently dissipated. In order to achieve the disclosure and other purposes, the semiconductor package of the present invention includes: a substrate having a top surface and an opposite bottom surface; at least one wafer adhesion area is preset on the top surface, and the wafer is adhered to the wafer. A plurality of heat radiation through holes penetrating through the substrate are provided in the placement area, and a heat radiation pad is formed on the bottom surface of the substrate corresponding to the wafer adhesion area, so that the heat radiation pad is connected to the heat radiation through holes of the substrate. ; At least one wafer stuck on the wafer adhesion area of the substrate and electrically connecting the wafer to the substrate; a plurality of electrically connected to a conductive connection element on the bottom surface of the substrate 1 for the chip and external devices to be electrically connected Connection; This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------- install --- (Please read the precautions on the back before filling in this page}

J^T --線· 經濟部智慧朗產扃員工湞費名竹相句$ 16382 498521J ^ T-Line · Ministry of Economics, Intelligent Production, Employees, Fees, Bamboo Phrases $ 16382 498521

五、發明說明（3 ) 以及一用以包覆該晶片並形成於該基板之頂面上的封裝 體。 經濟部智慧財產局員工消費合作社印製 為使該導電連接元件得與外界裝置妥適電性連接，該 散熱墊之厚度須小於該導電連接元件的高度。同時’為使 該散熱墊與基板之接設方式並得令該散熱墊之周邊為覆蓋 該基板底面上之拒銲劑（Solder Mask)有包覆，而將散熱墊 未為該拒銲劑所包覆之表面外露於大氣中。 [圖式簡單說明] 以下茲以較佳具體例佐以所附圖式進一步詳細說明本 發明之特點及功效。 第1圖係本發明第一實施例之半導體封裝件之剖視圖， 第2圖係本發明第一實施例之半導體封裝件之仰視 TgJ ·園， 第3圖係本發明第二實施例之半導體封裝件之剖視圍， 第4圖係本發明第三實施例之半導體封裝件之分解示 意圖； 第5圖係本發明第四實施例之半導體封裝件之分解示 忍圖，以及 第6圖係一習知半導體封裝件之剖視圖。 [發明之詳細說明] 弟1實施例 如第1及2圖所示者為本發明第一實施例之半導體封 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公g ) 16382 (請先閱讀背面之注意事項再填寫本頁) 05. Description of the invention (3) and a package for covering the wafer and formed on a top surface of the substrate. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In order for the conductive connection element to be properly electrically connected to external devices, the thickness of the heat sink must be less than the height of the conductive connection element. At the same time, in order to connect the heat-dissipating pad to the substrate and make the periphery of the heat-dissipating pad be covered with a solder mask covering the bottom surface of the substrate, the heat-dissipating pad is not covered with the solder-repellent. Its surface is exposed to the atmosphere. [Brief description of the drawings] The features and effects of the present invention will be further described in detail below with preferred specific examples and the attached drawings. FIG. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a bottom view of a semiconductor package of the first embodiment of the present invention, TgJ · Park, and FIG. 3 is a semiconductor package of a second embodiment of the present invention Fig. 4 is an exploded view of a semiconductor package of the third embodiment of the present invention; Fig. 5 is an exploded view of the semiconductor package of the fourth embodiment of the present invention; A cross-sectional view of a conventional semiconductor package. [Detailed description of the invention] The embodiment 1 shown in Figures 1 and 2 of the first embodiment of the present invention is a semiconductor sealed paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 g) 16382 ( (Please read the notes on the back before filling out this page) 0

JeT·. •線' 498521 經濟部智慧財產局員工消費合作社印製 16382 A7 五、發明說明（4 ) 裝件之剖視圖及仰視圖。 參照第1圖，本發明第一實施例之半導體封裝件2主 要係由一基板20，黏置於該基板2〇上之晶片21，形成於 該基板20上之散熱墊22，以及用以包覆該晶片21之封 裝膠體23所構成。 該基板20係具有一頂面2〇〇及一相對於該頂面2〇〇 之底面201。該頂面200上於大致中央位置處形成有一晶 I片黏置區202，並於該晶片黏置區2〇2外形成有多數第一 導電跡線（Conductive Traces)203，在該晶片黏置區202内 則設有多數之接地墊（Ground Pads)204，同時，該晶片黏 置區202内並開設有複數貫穿該基板2〇之散熱貫孔2〇5， 使該散熱貫孔205之一端係通連至該基板20頂面2〇〇上 之接地塾204 ’而另一端則通連至該基板2〇之底面2〇1 ; 該基板20之底面201相對於該第一導電跡線203之區域 上亦設有多數第二導電跡線206,且令該第二導電跡線206 ^與該第一導電跡線203藉多數位於該晶片黏置區202外且 貫穿該基板20之導電貫孔（Conductive Vias)207電性連 接。此外，在該基板20之頂面200及底面201上並分別 敷設有拒銲劑208、209，以將該第一導電跡線203及第 二導電跡線206覆蓋住而令其與外界氣密隔離，同時使該 晶片黏置區202與第一導電跡線203終端上之銲接墊（Bond Fingers)203a外露出該拒銲劑208，以及使底面201上相 對於該晶片黏置區202之區域與第二導電跡線206終端上 之植球墊（Ball Pads)206a外露出該拒銲劑209。由於該基 本纸張&度適用中國國家標準(CNS)A4規格（210 X 297公餐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 498521 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 B7 五、發明說明（5 ) 板20之形成係以習知製程為之，故在此不再詳予贅述。 該晶片21係以習用之如銀膠之膠黏劑24黏設至該基 板20之晶片黏置區202上，視需要，該晶片黏置區202 上得黏置有複數片晶片，或在該基板20上形成複數個晶 片黏置區。該晶片21與基板20黏結後，則係以多數之金 線25將該晶片21電性連接至第一導電跡線203之銲接墊 2〇3a上，以使該晶片21藉金線25與基板20形成電性連 接關係。 該散熱墊22之形成係與該第二導電跡線206同時為 之，亦即，利用一貼設於該基板20上之銅箔（CopperFoil) 藉钱刻等習知方式於該底面201上分別形成出該散熱墊22 及多數之第二導電跡線206。該散熱墊22係對應於該晶 片黏置區202之部位上，以使該散熱墊22恰位於該晶片 21下方，由於該晶片21與散熱塾22得分別與散熱貫孔205 端接，故該晶片21所產生之熱量得經散熱貫孔2〇5傳遞 至該散熱墊22而有效逸散，且由於該散熱墊22之一表面 220係直接外露於大氣中，因而傳遞至該散熱墊22埶 量得直接由該外露表面220直接逸散至大氣中，而提升該 半導體封裝件2之散熱效率.同時，由於該散熱墊“係 由片狀銅箱所形成，令其供散熱用之表面積較前揭之使用 散熱銲球之習知者為大，故具較佳之散熱效率；且該散熱 墊22係直接形成於基板20之底面2〇1上，毋須如前揭I 國專利須於基板上開孔以嵌設散熱片之方式為之，故 、 造成基板20之製造成本的增加，也無基板2〇與散熱 本紙張尺度適用中國國家標準（CNS)A4規烙（210 X --— - 5 16382 (請先閱讀背面之注意事項再填寫本頁) ' 丨線 498521 經 ’濟 部 智 慧 財 產 局 員 X 消 費 合 作 社 印 製 A7 B7 五、發明說明（6 ) 間產生裂隙之問題。再而，為使該基板20與散熱塾22之 結合性提升，得於該散熱墊22形成於該基板2〇上後，於 敷設該拒鮮劑209時使拒銲劑209亦包覆住該散熱塾22 之周邊部分，以令該散熱墊22得與該拒銲劑209形成嵌 接關係。當然，該散熱墊22亦得不為拒銲劑2〇9所遮覆， 而呈兩者分開之狀態。 在該封裝膠體23形成於該基板2〇之頂面2〇〇上後， 於該基板20之底面201上係以習知之植球技術將多數之 銲球27植接於該第二導電跡線2〇6之植球墊2〇以上，以 供該晶片21藉銲球27與外界裝置電性連結。該銲球27 均係位於散熱墊22之外圍，如第2圖所示， 埶 不致干涉至鲜球27之設置，且該散熱塾22之厚度;^、於 各銲球27之高度，俾在該半導體封裝件2銲接至印刷電 路板（未圖示）上時，該銲球27得安適地與印刷電路板上 對應之銲墊電性連接而不會受到散熱墊22之影響。 .[第二實施例] / & 第3圖所示者為本發明第二實施例之半導體封裝件之 剖視圖。 該第二實施例之半導逋封裝件3之結構大致同於前述 之第一實施例，其不同處在於該半導體封裝件3之散教墊 32外露於大氣中之表面32〇係形成凹凸狀，藉以進一步 =該散熱塾32所提供之散熱面積。該凹凸狀之表面320 成里得以任何習知方式為之，並無特殊限制。 [第三實施例] 本纸張尺度適用中國國家標準(CNS)A4^^··—公釐τ 16382 -n n 1 HI n n >1 n n an ϋ ϋ I · i i i n n an -n 一51，I n n βϋ ·ϋ n —- n I (請先閱讀背面之注意事項再填寫本頁) 498521 經濟部智慧財產局員工消費合作社印製 五、發明說明（7 / 第4圖所不者為本發明第三實施例之半導體封裝件之 分解示意圖。 如圖所示，該第三實施例之半導體封裝件4之結構大 致同於前述之第一實施例，其不同處在於供晶片產生之熱 量散熱用之散熱墊42得藉錫膏（Solder Paste)等習知黏合 劑480黏設至一設於一印刷電路板48上之散熱片， 該散熱片481之底面上並塗俦錫膏482以黏結—接地墊 483，使該散熱墊42與散熱片481之結合提供晶片41較 大之散面積，而得提高散熱效率；同時，各銲球47亦藉 錫膏484分別電性連接至印刷電路板48上之銲墊485上。 因而’該半導體封裝件4與印刷電路板48電性連接後， 該晶片41所產生之熱量仍得藉多數之散熱貫孔4〇5傳遞 至該散熱墊42及散熱片481而逸散至印刷電路板上。 如此，除可有效提升散熱效率，電接地跡線4〇4、散埶貫 孔405、散熱墊42 '散熱片481及接地墊仏3亦可形‘成二 接地迴路，而進一步提升該半導體封裝件4之電性。 [第四實施例] 第5圖所示者為本發明第四實施例之半導體封裝件之 分解示意圖。 如圖所示，該第四實施例之半導體封裝件5之結構大 致同於前述之第三實施例，其不同處在於該用以逸散晶片 51所產生之熱量的散熱塾52乃藉錫膏580黏接至一嵌置 於-與該具散熱塾52之半導體封裝件5電性連接之印刷 ，路板58中之散熱片匕該印刷電…8係開設有 本纸張尺度適用中國國家標準(CNS)A4規格 (請先閱讀背面之注意事項再填寫本頁) 0 訂-' -線JeT ·. • Line '498521 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16382 A7 V. Description of the Invention (4) Sectional view and bottom view of the assembly. Referring to FIG. 1, the semiconductor package 2 according to the first embodiment of the present invention is mainly composed of a substrate 20, a wafer 21 adhered to the substrate 20, a heat dissipation pad 22 formed on the substrate 20, and a package for packaging. It is composed of the encapsulant 23 covering the chip 21. The substrate 20 has a top surface 2000 and a bottom surface 201 opposite to the top surface 2000. A crystalline I-chip adhesion region 202 is formed on the top surface 200 at a substantially central position, and a plurality of first conductive traces 203 are formed outside the wafer adhesion region 202. The wafer is adhered to the wafer. In the area 202, a plurality of ground pads 204 are provided. At the same time, a plurality of heat dissipation through-holes 205 penetrating the substrate 20 are provided in the wafer adhesion area 202, so that one end of the heat dissipation through-hole 205 is formed. It is connected to the ground 塾 204 ′ on the top surface 200 of the substrate 20 and the other end is connected to the bottom surface 201 of the substrate 20. The bottom surface 201 of the substrate 20 is opposite to the first conductive trace 203. There are also a plurality of second conductive traces 206 on the area, and the second conductive traces 206 ^ and the first conductive traces 203 are located outside the wafer adhesion area 202 and pass through the substrate 20 The vias (Conductive Vias) 207 are electrically connected. In addition, the top surface 200 and the bottom surface 201 of the substrate 20 are respectively provided with solder resists 208 and 209 to cover the first conductive trace 203 and the second conductive trace 206 so as to be air-tightly isolated from the outside. At the same time, the solder resist 208 is exposed to the bonding pads 202 and bond fingers 203a on the terminals of the first conductive trace 203, and the area on the bottom surface 201 opposite to the bonding pad 202 and the first The solder resist 209 is exposed outside the Ball Pads 206 a on the terminals of the two conductive traces 206. As the basic paper & degree applies to China National Standard (CNS) A4 specification (210 X 297 meals) ------------- installation -------- order --- ------ line (Please read the notes on the back before filling this page) 498521 Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs V. Description of Invention (5) The formation of plate 20 is based on a known process. Therefore, it will not be described in detail here. The wafer 21 is adhered to a wafer adhesion area 202 of the substrate 20 with a conventional adhesive 24 such as silver glue. If necessary, a plurality of wafers may be adhered to the wafer adhesion area 202, or A plurality of wafer adhesion regions are formed on the substrate 20. After the wafer 21 and the substrate 20 are bonded, the wafer 21 is electrically connected to the bonding pad 201a of the first conductive trace 203 with a plurality of gold wires 25, so that the wafer 21 borrows the gold wires 25 and the substrate. 20 forms an electrical connection relationship. The heat dissipation pad 22 is formed at the same time as the second conductive trace 206. That is, a copper foil (CopperFoil) attached to the substrate 20 is used to borrow money and engraved on the bottom surface 201 in a conventional manner. The heat dissipation pad 22 and a plurality of second conductive traces 206 are formed. The heat-dissipating pad 22 is located on a portion corresponding to the die attaching area 202 so that the heat-dissipating pad 22 is located just below the wafer 21. Since the wafer 21 and the heat-dissipating fin 22 are respectively terminated with the heat-dissipating through-holes 205, the The heat generated by the chip 21 can be efficiently dissipated to the heat dissipation pad 22 through the heat dissipation through hole 205, and since one surface 220 of the heat dissipation pad 22 is directly exposed to the atmosphere, it is transferred to the heat dissipation pad 22 埶Measured directly from the exposed surface 220 to escape directly into the atmosphere, thereby improving the heat dissipation efficiency of the semiconductor package 2. At the same time, because the heat sink "is formed of a sheet-shaped copper box, its surface area for heat dissipation is relatively small. The previous use of heat-dissipating solder balls is large, so it has better heat-dissipation efficiency; and the heat-dissipating pad 22 is directly formed on the bottom surface 201 of the substrate 20, and it is not necessary to expose the national patent on the substrate as previously disclosed The openings are formed by embedding heat sinks. Therefore, the manufacturing cost of the substrate 20 is increased, and there is no substrate 20 and heat dissipation. The paper size applies the Chinese National Standard (CNS) A4 standard (210 X ---- 5 16382 (Please read the notes on the back first (Fill in this page) '丨 Line 498521 Economics' Printed by A7 B7, Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Cooperative V. The problem of cracks between the invention description (6). In addition, in order to make the substrate 20 and the heat sink 22 cohesive Lifting, after the heat dissipation pad 22 is formed on the substrate 20, when the freshness preventive agent 209 is laid, the solder resist 209 also covers the peripheral portion of the heat dissipation pad 22, so that the heat dissipation pad 22 can communicate with the The solder resist 209 forms an embedding relationship. Of course, the heat dissipation pad 22 may not be covered by the solder resist 209, but is separated from the two. The encapsulant 23 is formed on the top surface 2 of the substrate 20 After 〇〇, on the bottom surface 201 of the substrate 20, the majority of the solder balls 27 are planted on the second conductive trace 206 by the conventional ball planting technology 20 for the wafer. 21 is electrically connected to the external device by the solder ball 27. The solder balls 27 are all located on the periphery of the heat dissipation pad 22, as shown in FIG. 2, so as not to interfere with the setting of the fresh ball 27, and the thickness of the heat dissipation pad 22; ^ At the height of each solder ball 27, solder the semiconductor package 2 to a printed circuit board ( (Pictured), the solder ball 27 must be electrically connected with the corresponding solder pad on the printed circuit board comfortably without being affected by the heat dissipation pad 22. [Second Embodiment] / & Figure 3 This is a cross-sectional view of the semiconductor package of the second embodiment of the present invention. The structure of the semiconductor package 3 of the second embodiment is substantially the same as that of the first embodiment described above, except that the semiconductor package 3 is scattered. The surface 32 of the teaching pad 32 exposed to the atmosphere is formed in a concave-convex shape, so as to further equal the heat-dissipating area provided by the heat sink 32. The concave-convex surface 320 can be formed in any conventional manner without any particular limitation. [Third embodiment] This paper size applies Chinese National Standard (CNS) A4 ^^ ·· —mm τ 16382 -nn 1 HI nn > 1 nn an ϋ ϋ I · iiinn an -n -51, I nn βϋ · ϋ n —- n I (Please read the notes on the back before filling in this page) 498521 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (7 / Figure 4 is the third of the invention An exploded view of the semiconductor package of the embodiment. As shown in the figure, the structure of the semiconductor package 4 of the third embodiment is substantially the same as that of the first embodiment described above, and the difference lies in the heat dissipation for the heat generated by the chip. The pad 42 may be attached to a heat sink provided on a printed circuit board 48 by a conventional adhesive 480 such as Solder Paste, and the bottom surface of the heat sink 481 is coated with a solder paste 482 for bonding to a ground pad. 483. The combination of the heat dissipation pad 42 and the heat sink 481 provides a larger scattered area of the chip 41 to improve the heat dissipation efficiency. At the same time, each solder ball 47 is also electrically connected to the printed circuit board 48 through a solder paste 484. On the bonding pad 485. Therefore, the 'the semiconductor package 4 and the printed circuit board 4 8. After the electrical connection, the heat generated by the chip 41 still needs to be transferred to the heat dissipation pad 42 and the heat sink 481 and dissipated to the printed circuit board through the majority of the heat dissipation through holes 405. In this way, in addition to effectively improving heat dissipation Efficiency, the electric ground trace 404, the scattered through holes 405, the heat dissipation pad 42 ', the heat sink 481, and the ground pad 3 can also be formed into two ground loops to further improve the electrical properties of the semiconductor package 4. [ Fourth Embodiment] FIG. 5 is an exploded view of a semiconductor package according to a fourth embodiment of the present invention. As shown in the figure, the structure of the semiconductor package 5 of the fourth embodiment is substantially the same as the third embodiment described above. The embodiment is different in that the heat sink 52 for dissipating the heat generated by the chip 51 is bonded to an embedded-electrical connection with the semiconductor package 5 having the heat sink 52 by a solder paste 580. Printed, the heat sink in the road board 58. This printed electrical ... 8 series are equipped with this paper standard applicable to China National Standard (CNS) A4 specifications (please read the precautions on the back before filling this page) 0 Order-'-line

五、發明說明（8 開孔585以供該翁备 ^ 通散熱片581嵌置其中，為使該散熱墊52 得藉锡胃580點接至該散熱墊52以逸散晶片51所產生之 熱里j該散熱片581須凸伸出該印刷電路板58之頂面586 適當兩度。同時’為使該半導體封裝件5與印刷電路板 58結合後之散熱效率更進一步提升，得於該散熱墊η之 -面上外接散熱片59，俾增加散熱面積而提升散熱效 果0 [元件符號說明] 經濟部智慧財產局員工消費合作社印製 10 基板 100 嵌孔 11 散熱片 12 晶片 2 半導體封裝件 20 基板 200 頂面 201 底面 202 晶片黏置區 203 第一導電跡線 203a 鋒接墊 204 接地跡線 205 散熱貫孔 206 第一導電跡線 206a 植球墊 208 拒銲劑 209 拒銲劑 21 晶片 22 散熱墊 220 表面 23 封裝膠體 24 膠黏劑 25 金線 27 銲球 3 半導體封裝件 32 散熱塾 320 表面 4 半導體封裝件 404 接地跡線 405 散熱貫孔 41 晶片 42 散熱墊 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 16382 ---------------------^---------^ (請先閱讀背面之注意事項再填寫本頁) 8 498521 A7 B7 五、發明說明（9 )V. Description of the invention (8 Opening hole 585 for the Weng Bei ^ through the heat sink 581 embedded in, so that the heat sink 52 can be connected to the heat sink 52 by the tin stomach 580 point to dissipate the heat generated by the chip 51 Here, the heat sink 581 must protrude from the top surface 586 of the printed circuit board 58 by two degrees. At the same time, in order to further improve the heat dissipation efficiency of the semiconductor package 5 and the printed circuit board 58, The heat sink 59 is connected to the surface of the pad η, which increases the heat dissipation area and improves the heat dissipation effect. 0 [Description of component symbols] Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 10 Substrate 100 Embedded holes 11 Heat sink 12 Chip 2 Semiconductor package 20 Substrate 200 Top surface 201 Bottom surface 202 Wafer adhesion area 203 First conductive trace 203a Edge pad 204 Ground trace 205 Thermal via 206 First conductive trace 206a Ball-planted pad 208 Solder resist 209 Solder resist 21 Chip 22 Thermal pad 220 Surface 23 Packaging gel 24 Adhesive 25 Gold wire 27 Solder ball 3 Semiconductor package 32 Thermal pad 320 Surface 4 Semiconductor package 404 Ground trace 405 Thermal via 41 Chip 42 Thermal pad Paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 16382 --------------------- ^ --------- ^ (Please read the notes on the back before filling this page) 8 498521 A7 B7 V. Description of the invention (9)

48 印刷電路板 480 錫膏 481 散熱片 482 錫膏 483 接地塾 484 錫膏 485 銲墊 5 半導體封裝件 51 晶片 52 散熱塾 58 印刷電路板 580 錫膏 581 散熱片 585 開孑L 586 頂面 59 散熱片 以上所述者，僅為本發明之具體實施例而已，其它任 何未背離本創作之精神與技術下所作之等效改變或修飾， 均應仍包含在下述專利範圍之内。 (請先閱讀背面之注意事項再填寫本頁) •線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4覘格（21〇χ 297公釐） 9 1638248 Printed Circuit Board 480 Solder Paste 481 Heat Sink 482 Solder Paste 483 Ground 塾 484 Solder Paste 485 Solder Pad 5 Semiconductor Package 51 Chip 52 Heat Sink 58 Printed Circuit Board 580 Solder Paste 581 Heat Sink 585 Open L 586 Top Surface 59 Heat Sink The above mentioned are only specific embodiments of the present invention, and any other equivalent changes or modifications made without departing from the spirit and technology of this creation should still be included in the scope of the following patents. (Please read the precautions on the back before filling this page) • Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 grid (21〇χ 297 mm) 9 16382

Claims (1)

經濟部智慧財產局員工消費合作社印製 10 498521 f_g|__ 六、申請專利範圍 】，一種具增進散熱效率之半導體封裝件，係包括： 一基板，其具有一頂面及一相對之底面，於該頂 面上之預設位置上形成至少一晶片黏置區，以供至少 一晶片黏設於該晶片黏置區上，並使該晶片與基板電 性連接，且於該晶片黏置區内開設有複數散熱貫孔， 使該散熱貫孔貫連該基板之頂面及底面，· 一形成於該基板之底面上之散熱墊，該散熱墊與 | 基板接置後係對應於該晶片，並與該散熱墊貫孔接連； 複數植設於該基板底面上之導電連接元件；以及 一用以包覆該晶片且形成於該基板頂面上之封裝 膠體。 2♦如申請專利範圍第〗項之半導體封裝件，其中，該散 熱墊之周邊為一敷設於該基板之底面上之拒銲劑所包 覆。 3.如申請專利範圍第1項之半導體封裝件，其中，該散 瞻熱塾復得與該半導體封裝件電性連接之外界裝置上所 設之散熱片接連，俾使該晶片所產生之熱量得藉該散 熱貫孔傳遞至該散熱墊，再至該散熱片上。 4·如申請專利範圍第1項之半導體封裝件，其中，該散 熱塾復得與一嵌置於一與該半導體封裝件電性連接之 外界裝置中的散熱片接連，俾使該晶片所產生之熱量 得藉該散熱貫孔傳遞至該散熱墊，而至該散熱片上。 5.如申請專利範圍第3或4項之半導體封裝件，其中， 該外界裝置係一印刷電路板。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 16382 I I I I I I I I I « - — II 1 III ^ ·11111111 (請先閱讀背面之注意事項再填寫本頁) 其中，該散 其中，該散 A8 B8 C8 D8 :、申請專利範圍 6.如申請專利範園第！項之半導體封裝件 熱墊之高度係小該導電連接元件之高度 7·如申請專利範圍，！項之半導體封=” 熱墊-表面係予以凹凸化處理，以增加散熱面積 8.如申請專利範圍第1項之半導體封裝件，其中，該散 熱墊係金屬片形成者。 9·如申請專利範圍第1項之半導體封裝件，其中，該導 電連接元件係銲球。 10.如申請專利範圍第！項之半導體封裝件，其中，該晶 片係與該散熱貫孔接連，以使該晶片所產生之熱量由 該散熱貫孔傳遞至該散熱墊上。 --------—------^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 11 16382Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 498521 f_g | __ VI. Patent Application Scope], a semiconductor package with improved heat dissipation efficiency, which includes: a substrate with a top surface and a bottom surface opposite to At least one wafer adhesion area is formed at a predetermined position on the top surface, so that at least one wafer is adhered to the wafer adhesion area, and the wafer is electrically connected to the substrate, and is in the wafer adhesion area. A plurality of thermal vias are provided so that the thermal vias penetrate the top surface and the bottom surface of the substrate, and a thermal pad formed on the bottom surface of the substrate. The thermal pad is connected to the substrate and corresponds to the wafer, and The heat-dissipating pads are continuous with through-holes; a plurality of conductive connection elements implanted on the bottom surface of the substrate; and a packaging gel for covering the chip and formed on the top surface of the substrate. 2 ♦ If the semiconductor package according to the scope of the application for a patent, the periphery of the thermal pad is covered by a solder resist laid on the bottom surface of the substrate. 3. If the semiconductor package according to item 1 of the patent application scope, wherein the scattered heat is reconnected with the heat sink provided on the outer boundary device electrically connected to the semiconductor package, so that the heat generated by the chip It must be transmitted to the heat sink through the heat sink through hole, and then to the heat sink. 4. If the semiconductor package according to item 1 of the patent application scope, wherein the heat sink is connected with a heat sink embedded in an outer boundary device electrically connected to the semiconductor package, so that the chip generates The heat must be transferred to the heat sink through the heat sink through hole, and to the heat sink. 5. The semiconductor package of claim 3 or 4, wherein the external device is a printed circuit board. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 16382 IIIIIIIII «--II 1 III ^ · 11111111 (Please read the precautions on the back before filling out this page) A8 B8 C8 D8: 、 Applicable patent scope 6. If applying for patent Fanyuandi! The height of the semiconductor package of the item is smaller than the height of the conductive connection element. 7 · If the scope of the patent is applied ,! Item of semiconductor seal = ”The thermal pad-surface is roughened to increase the heat dissipation area. 8. As for the semiconductor package in the first item of the patent application scope, wherein the heat sink is a metal sheet former. 9 · If a patent is applied for The semiconductor package of the scope item 1, wherein the conductive connection element is a solder ball. 10. The semiconductor package of the scope of the patent application item !, wherein the chip is connected to the heat sink through hole so that the chip is The heat generated is transferred from the heat sink through hole to the heat sink. ------------------ ^ --------- ^ (Please read the precautions on the back before filling (This page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm) 11 16382
TW090118971A 2001-08-03 2001-08-03 Semiconductor package with enhanced heat-dissipation efficiency TW498521B (en)

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