TW497073B - Data processor system and instruction system using grouping - Google Patents

Data processor system and instruction system using grouping Download PDF

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Publication number
TW497073B
TW497073B TW088117156A TW88117156A TW497073B TW 497073 B TW497073 B TW 497073B TW 088117156 A TW088117156 A TW 088117156A TW 88117156 A TW88117156 A TW 88117156A TW 497073 B TW497073 B TW 497073B
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TW
Taiwan
Prior art keywords
instruction
group
prefix
type
command
Prior art date
Application number
TW088117156A
Other languages
English (en)
Chinese (zh)
Inventor
Zvika Rozenshein
Jacob Tokar
Uri Dayan
Joe Paul Gergen
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW497073B publication Critical patent/TW497073B/zh

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018Bit or string instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30185Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Electrophonic Musical Instruments (AREA)
TW088117156A 1998-10-13 1999-10-05 Data processor system and instruction system using grouping TW497073B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/170,690 US6418527B1 (en) 1998-10-13 1998-10-13 Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods

Publications (1)

Publication Number Publication Date
TW497073B true TW497073B (en) 2002-08-01

Family

ID=22620876

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088117156A TW497073B (en) 1998-10-13 1999-10-05 Data processor system and instruction system using grouping

Country Status (10)

Country Link
US (1) US6418527B1 (https=)
EP (1) EP0994413B1 (https=)
JP (1) JP2000122864A (https=)
KR (1) KR100690225B1 (https=)
CN (1) CN1129843C (https=)
AT (1) ATE266226T1 (https=)
DE (1) DE69916962T2 (https=)
ES (1) ES2221282T3 (https=)
SG (1) SG95605A1 (https=)
TW (1) TW497073B (https=)

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JP3627725B2 (ja) * 2002-06-24 2005-03-09 セイコーエプソン株式会社 情報処理装置及び電子機器
US6944749B2 (en) * 2002-07-29 2005-09-13 Faraday Technology Corp. Method for quickly determining length of an execution package
US6865662B2 (en) * 2002-08-08 2005-03-08 Faraday Technology Corp. Controlling VLIW instruction operations supply to functional units using switches based on condition head field
WO2004114128A2 (en) * 2003-06-25 2004-12-29 Koninklijke Philips Electronics N.V. Instruction controlled data processing device
US7340588B2 (en) * 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US7873815B2 (en) * 2004-03-04 2011-01-18 Qualcomm Incorporated Digital signal processors with configurable dual-MAC and dual-ALU
US20060149926A1 (en) * 2004-12-23 2006-07-06 Yuval Sapir Control words for instruction packets of processors and methods thereof
US20060149922A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Multiple computational clusters in processors and methods thereof
US20060150171A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Control words for instruction packets of processors and methods thereof
US7350040B2 (en) * 2005-03-03 2008-03-25 Microsoft Corporation Method and system for securing metadata to detect unauthorized access
US7526633B2 (en) * 2005-03-23 2009-04-28 Qualcomm Incorporated Method and system for encoding variable length packets with variable instruction sizes
US7793078B2 (en) * 2005-04-01 2010-09-07 Arm Limited Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding
JP5217431B2 (ja) * 2007-12-28 2013-06-19 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US8281106B2 (en) * 2008-12-16 2012-10-02 International Business Machines Corporation Specifying an addressing relationship in an operand data structure
US8407680B2 (en) * 2008-12-16 2013-03-26 International Business Machines Corporation Operand data structure for block computation
US8285971B2 (en) * 2008-12-16 2012-10-09 International Business Machines Corporation Block driven computation with an address generation accelerator
US8458439B2 (en) * 2008-12-16 2013-06-04 International Business Machines Corporation Block driven computation using a caching policy specified in an operand data structure
US8327345B2 (en) * 2008-12-16 2012-12-04 International Business Machines Corporation Computation table for block computation
GB2486737B (en) 2010-12-24 2018-09-19 Qualcomm Technologies Int Ltd Instruction execution
GB2486740B (en) 2010-12-24 2019-02-13 Qualcomm Technologies Int Ltd Encapsulated instruction set
WO2012131437A1 (en) * 2011-03-30 2012-10-04 Freescale Semiconductor, Inc. Integrated circuit device and method for enabling cross-context access
US8898433B2 (en) * 2012-04-26 2014-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Efficient extraction of execution sets from fetch sets
KR102210997B1 (ko) * 2014-03-12 2021-02-02 삼성전자주식회사 Vliw 명령어를 처리하는 방법 및 장치와 vliw 명령어를 처리하기 위한 명령어를 생성하는 방법 및 장치
US9733940B2 (en) 2014-11-17 2017-08-15 International Business Machines Corporation Techniques for instruction group formation for decode-time instruction optimization based on feedback
US9940242B2 (en) * 2014-11-17 2018-04-10 International Business Machines Corporation Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries
US10402199B2 (en) * 2015-10-22 2019-09-03 Texas Instruments Incorporated Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
US20170192788A1 (en) * 2016-01-05 2017-07-06 Intel Corporation Binary translation support using processor instruction prefixes
CN114004349A (zh) * 2016-08-05 2022-02-01 中科寒武纪科技股份有限公司 一种能支持不同位宽运算数据的运算单元、方法及装置
US10761849B2 (en) * 2016-09-22 2020-09-01 Intel Corporation Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
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Also Published As

Publication number Publication date
EP0994413A3 (en) 2002-01-23
ES2221282T3 (es) 2004-12-16
EP0994413B1 (en) 2004-05-06
KR100690225B1 (ko) 2007-03-12
ATE266226T1 (de) 2004-05-15
DE69916962T2 (de) 2005-04-07
EP0994413A2 (en) 2000-04-19
CN1250906A (zh) 2000-04-19
SG95605A1 (en) 2003-04-23
US20020056035A1 (en) 2002-05-09
JP2000122864A (ja) 2000-04-28
KR20000029005A (ko) 2000-05-25
CN1129843C (zh) 2003-12-03
DE69916962D1 (de) 2004-06-09
US6418527B1 (en) 2002-07-09

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