TW495971B - Method for forming integrated circuit having MONOS device and mixed-signal circuit - Google Patents

Abstract

A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Description

495971 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming integrated circuits, and more particularly to a method for forming a metal-Oxide Nitride-Oxide Semiconductor (MONOS) element and a mixed-signal (Mixed- Signal) Circuit integration method. 5-2 Background of the Invention: 〇 In view of the increasing demand for integrated circuits and diversified uses of integrated circuits, the industry has widely adopted system-on-chip (Sytem ο na Chi) components. Elements with different functions, such as logic elements and memory elements, are integrated into a single chip, and these elements have an interactive relationship with each other. It is also because the manufacturing processes for forming logic elements such as metal oxide semiconductor transistors (MOS Transistor) and memory elements such as non-volatile memory (N ο η-V ο 1 ati 1 e M em 〇ry) are equivalent. Diversity. It is very complicated and difficult to make a system-on-a-chip with logic elements and non-volatile memory elements. In order to integrate a variety of components with different functions on a single chip, it is necessary to develop simultaneously applicable processes for the operation and manufacturing of various components. The Embedded Memory Logic device is a system-on-a-chip, which integrates the memory device and logic device into a single 495971. 5. Description of the invention (2) chip. The entire embedded memory logic element is composed of a logic circuit area and a memory cell area (Ce 1 1 Array). There are usually many memory cells located in the memory cell area, in which Je stores lean materials, and these materials are processed by logic elements in the avoidance circuit area. Among them, dynamic random access memory (DRAM) or static random access memory (SRAM) is a memory widely used in a memory cell area. However, non-volatile memory such as NR 0 M (N itride R ead-Ο η 1 y Memory) memory cells and MONOS (Metal-Oxide Nitride-Oxide Semi ο nductor) memory cells are rarely integrated into the system single chip . ❶ The first picture A shows a MONOS memory cell on a substrate 100. In the first picture A, an oxide layer 102, a nitride layer 104, and an oxide layer 106 constitute an 0N0 (Oxide-Nitride-Oxide) layer. The first A picture also shows a polycrystalline silicon layer 108 used as a conductor layer. The first B diagram shows a metal oxide semiconductor transistor on a substrate 120. The metal oxide semiconductor transistor includes a gate oxide layer 1 2 2, a polycrystalline silicon gate electrode 1 2 4, and a source / inverter 1 2 6 a and 1 2 6 b. The first C diagram shows a PIP (Polysilicon-Insulator-Poly silicon) capacitor on the substrate 130, where the PIP capacitor includes an oxide layer 1 3 2, a polycrystalline silicon layer electrode 1 3 4 and an oxide Layer 1 3 6 and a polycrystalline silicon layer electrode 1 3 8. Metal oxide semiconductor f-body transistors and PI capacitors can form mixed-signal circuits. MONOS memory, metal oxide semiconductor transistors and PI capacitors not only have different structures and operating principles, but their manufacturing processes are also quite different. In view of the various requirements for making system-on-a-chip, such as reducing production costs and integrating various systems

495971 V. Description of the invention (3) Process and improvement of yield, etc. It is very necessary to propose an improved process integration technology to meet the needs of modern system single-chip manufacturing. This is the purpose proposed by the present invention. 5-3 Purpose and Summary of the Invention: One object of the present invention is to provide a novel process integration technology, which can integrate MONOS memory, metal oxide semiconductor transistors and PIP capacitors into a system single chip. Another object of the present invention is to provide a method for forming a system-on-a-chip including a MONOS memory, a metal oxide semiconductor transistor, and a PI capacitor. This method has fewer process steps. Another object of the present invention is to provide a method for forming a system-on-a-chip, which can reduce production costs, integrate various process steps, and improve yield to achieve the above-mentioned objectives. A method for integrating a circuit, the method includes at least the following steps: providing a substrate having a memory cell region and a peripheral region, the memory cell region having a first dielectric layer, a first Two dielectric layers and a third dielectric layer, and the peripheral region has the first dielectric layer

495971 V. Description of the invention (4) The electrical layer is not necessarily a first dielectric layer, a second dielectric layer and a first conductor layer; a plurality of ions are implanted into the migration to etch the first conductor layer in the peripheral region Removing the exposed substrate from the substrate; oxidizing the second conductor layer to form a fourth dielectric layer; and a fifth conductor layer on the recording layer and the third conductor layer A dielectric layer, a third dielectric layer forming a light first conductor layer layer to form a second dielectric layer in addition to the third dielectric layer and a peripheral region, and a fourth dielectric pattern transfer to memorize the upper and upper cells. Dielectric layer, the dielectric layer on this peripheral area can also be formed by etching the first dielectric layer, namely the ONO layer, and then growing: the resist layer covers the memory cell area; the cloth; the photoresist layer is removed; Two conductor layers and a third conductor electrical layer to expose the first dielectric layer of the second dielectric to expose the substrate, the second conductor layer and the layer; forming a fourth conductor layer to etch the first conductor layer Four conductor layers to form a sixth conductor layer. In the fourth embodiment, the present invention records MONOS with fewer process steps. , Metal oxide semiconductor transistor and the capacitor PI P within the integrated system on-chip. In the present invention, a first dielectric layer including at least a silicon dioxide layer is used as a bottom oxide layer of a M 0 N 0 S memory element, and a gate oxide layer of a metal oxide semiconductor transistor PI is a bottom insulating layer of a capacitor. , Which can reduce process steps. In addition, in the present invention, the first conductor layer including at least one polycrystalline silicon layer is used as the gate electrode of the metal oxide semiconductor transistor and the lower electrode of the PI capacitor, or the N-type or P-type can be used simultaneously. The conductivity of the gate of the metal oxide semiconductor transistor and the electrode below the PI capacitor is adjusted, so the process steps are reduced. In addition, the non-substrate selective oxidation process is used to form the top oxide layer and PI capacitor insulation layer as the MONOS memory element.

495971 V. Description of the invention (5) This can avoid the reliability problem caused by the dry or wet etching damage of the third dielectric layer, and can also prevent the edge of the second dielectric layer from directly contacting the conductor layer and causing leakage, at the same time It can also form the fourth dielectric layer as the insulating layer of the PIP capacitor and can be used in the polycrystalline silicon reoxidation process of the metal oxide semiconductor transistor to reduce the leakage current of the metal oxide semiconductor transistor. The present invention also uses the fourth conductor layer as the conductor layer of the MONOS memory element and the upper electrode of the PIP capacitor or GP0LY. Therefore, the processes for forming the conductor layer as the MONOS memory element and the electrode on the PI capacitor can be integrated. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention. 5-4 Detailed Description of the Invention: What must be explained here is that the process steps and structures described below do not include a complete process. The present invention can be implemented by various integrated circuit process technologies, and only the process technologies required to understand the present invention are mentioned here. The following will make a detailed description according to the attached drawings of the present invention. Please note that the drawings are simple forms and are not drawn to scale, and the dimensions are exaggerated to facilitate understanding of the present invention. Refer to the second figure A and display a bottom 2 0 0, this substrate 2 0 0 up to

Fifth, invention description (6) It contains a field π in the memory cell area (Araray R egi ο η) that forms the MONO S memory; this is not the bottom; it forms the peripheral area (Periphery Region) of the logic element. Contains a silicon substrate with < 1 0 0 > lattice direction, but is limited to; ^ P ·. ≪ 1 00 > silicon substrate with lattice direction. Memory Cell Area (Array

Kegl〇n) μ _ Shaorenrenba ^ has a Sandwich layer, this sandwich layer to 22: 4 (\ electric layer 202, 204 and 206, this sandwich layer with an oxide -The nitrogen layer is an 0NO layer (Oxide-Nitride-〇xide Layer) 2 0 ^ 1 is not limited to a 0N0 layer. There is also a dielectric layer 202 on the surrounding area. The silicon dioxide layer formed by the oxidation method. Dielectric 202 is used in the present invention as the gate oxide layer of the bottom of the MONOS memory element and the metal oxide semiconductor transistor. Therefore, the thickness of the eight layers 2 0 2 is in the memory The cell area and the surrounding area can be different, & in " "Yingding. For example, 'the thickness of the dielectric layer 2 0 2 in the memory cell area; = on demand and between about 90 Angstroms, the thickness in the peripheral area can be It is about 20 angstroms ^ is about 50 angstroms. At this time, the thickness of the dielectric layer 202 in the memory cell region is about 200 Å, and the thickness of the 200 angstrom dielectric layer 202 is about 2 in the peripheral region. 〇_70 is better than Angstrom. The difference in thickness between the memory cell area and the surrounding area can be traditional: the dielectric layer 202 process and the etching process can be achieved or the 0N0 layer in the surrounding area can be completely used. Filmed to The thickness can be required. In order to form at least one moment to remove the reoxygen dielectric layer 204 and at least < the dielectric layer containing the oxidized stone layer 7 ^ dagger stone layer in the memory cell area, you can traditionally Methods such as chemical gas 206 are limited to the lithography process. The thickness of the dielectric layer 206 is known as: etched and between, and preferably about 130 angstroms. Dielectric layer 206 Thick H Angstroms to about 200 Angstroms to about 200 Angstroms, while at about 80 Angstroms & may be about 20 Angstroms to Govern A picture, conductor 495971 V. Description of the invention (7 The layer 208 is formed to cover the memory cell area and the surrounding area. The conductor layer 208 includes at least a polycrystalline silicon layer formed by a conventional method such as chemical vapor deposition. Referring to FIG. 2B, the conventional The lithography process forms a pattern on the structure shown in Figure 2A, and a photoresist layer 210 is formed to cover the memory cell area. Then an N-type implantation or a 'P-type implantation is performed on the structure. The structure shown in Figure 2A is to implant N-type implant ions such as phosphorus ions or P-type implant ions such as boron ions into the exposed conductor layer 208 to adjust the conductor layer. Electrical conductivity of 2.08. N-type implants are used for N-type metal oxide semiconductor transistors and P-type implants are used for P-type metal oxide semiconductor transistors. Both N-type implants and P-type implants are available. Corresponding lithography process. The conductive layer 208 is also used as the lower electrode of the PIP capacitor, and the N-type implant or P-type implant system is used to adjust the conductivity of the lower electrode of the PIP capacitor. Refer to Figure 2C As shown, the photoresist layer 2 10 is removed and the conductive layer 208 is etched to form the conductive layers 2 8 a and 2 8 b and the dielectric layers 2 0 2 and 2 6 are exposed. The conductive layer 208 can be etched by a conventional method, but a dry etching method such as a reactive ion etching method is preferred. The conductive layers 2 0 a and 2 8 b are used as the gate of the metal oxide semiconductor transistor and the lower electrode of the PIP capacitor, respectively, and the dielectric layer 2 2 is also used as the gate of the metal oxide semiconductor transistor. The oxide layer and the bottom insulating layer of the PIP capacitor. In addition, since the PIP capacitor is usually located on the shallow trench isolation (ST I) or field oxide layer, the PIP capacitor in the present invention is not limited to being located on the shallow trench isolation or field oxide layer, as long as the PIP capacitor is isolated from the substrate. .

495971

V. Description of the invention (8) Referring to the second figure D, the dielectric layer 20 6 and the exposed dielectric layer 202 are removed by a conventional method such as an etching method. The dielectric layer 202 was removed because the previous process and etching of the conductive layer 208 often caused the dielectric layer 202 to be damaged. In addition, referring to the second figure E, a dielectric layer 204 including at least one nitride layer, a substrate 200 including at least a silicon substrate, and a conductor layer 2 0 8 including at least a polycrystalline silicon layer. 0 b is oxidized by a conventional method such as a wet oxidation method to form dielectric layers 214, 216a, 216b, 218a, and 218b. The dielectric layers 214, 216a, 216b, 21 8a, and 21 8b include at least a silicon dioxide layer. However, due to the traditional wet oxidation method, the speed of oxidizing silicon nitride is much lower than the speed of silicon oxide. For example, the oxidation speed of silicon nitride and silicon is much greater than 1: α. Using a non-substrate selective oxidation process is Suitably, the oxidation speed ratio of the oxidized lice-to-silicon silicon to silicon can exceed about 0.6. At least; b :. The interlayer of V electricity 2 夂: = oxidation to convert its-part into the intermediary is preferred. The remaining two ΐ :: about 30 angstroms to about 130 angstroms, and about angstroms, and the thickness of about 70 Å layer 204 can be about 60 angstroms to about 70 angstroms to about 110 angstroms. The dielectric layers 21 6a and 21 6b may be between about 110 Angstroms. The dielectric layers 21 8a and 2 18b may be about 70 angstroms to a thickness of about 40-10, 2 1 6 a, 2 1 6 b, 2 1 8 8 and 2 1 8 b. The conductive layer 2 0 8 a is formed '′ This method does not have a substrate (substrate) oxidation method and less metal oxide semiconducting ^ ^ The layer 2 1 6 a is re-oxidized with polycrystalline silicon to reduce the leakage current of the full moon crystal. Reference second? As shown in the figure,-the conductor layer is formed in the second tone

495971 Fifth, the structure of invention description (9). The conductor layer 220 includes at least one polycrystalline silicon layer and preferably an I η S i t u polycrystalline silicon layer. The In S i t u polycrystalline silicon layer is filled with phosphorus implant ions and W s i is on the polycrystalline silicon layer to reduce the resistance value. The conductive layer 2 2 0 can be a conventional method such as chemical vapor deposition, but a low pressure chemical vapor deposition is preferred. The conductor layer 2 2 0 including at least a polycrystalline silicon layer is a conductor layer for a MONOS memory element and an electrode on a PIP capacitor or called GP0LY (Gate P〇1y) 〇 Referring to the second G diagram, the conductor layer 2 2 0 The conductive layers 2 2 a and 2 2 b are formed by etching using a conventional lithography process and an etching process. Among them, a dry etching method such as a reactive ion etching method is preferred. The conductor layers 2 2 0 a and 2 2 0 b are used as the conductor layer of the MONOS memory element and the electrode on the PIP capacitor or GPOLY (Gate Poly). Thereafter, the non-substrate selective oxidation process is performed again for polycrystalline silicon re-oxidation to form a dielectric layer 2 2 2 to reduce the leakage current of the metal oxide semiconductor transistor. The present invention integrates MONOS memory, metal oxide semiconductor transistor and PI capacitor into the system single chip with fewer manufacturing steps. In the present invention, a dielectric layer 202 including at least a silicon dioxide layer is used as the bottom oxide layer of the M 0 N 0 S memory element, and the gate oxide layer of the metal oxide semiconductor transistor PI is insulated from the bottom of the capacitor. Layers, thus reducing process steps. In addition, the present invention uses a conductive layer 208 including at least a polycrystalline silicon layer as the gate of the metal oxide semiconductor transistor and the lower electrode of the PI capacitor, and simultaneously adjusts the metal oxidation by N-type or P-type implantation. Semiconductor transistor

Page 13 495971 V. Description of the Invention The conductivity of the gate of the body and the electrode under the PI capacitor is reduced, so the process steps are reduced. In addition, the present invention utilizes a non-substrate selective oxidation process to form a dielectric layer 2 1 4 as a top oxide layer of a MONOS memory element and a dielectric layer 216 b as an insulating layer of a PIP capacitor, so that the dielectric layer 206 can be avoided. The problem of reliability caused by etching damage, and at the same time, a dielectric layer 2 1 6 b can be formed as the insulating layer of the PIP capacitor. The present invention also uses the conductor layer 220 as the conductor layer of the MONOS memory element and the electrode above the PIP capacitor or GP0LY. Therefore, the processes for forming the conductor layer as the MONOS memory element and the electrode above the PI capacitor can be integrated. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention.

Page 495971 Brief description of the drawings In order to make the other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows. The first picture A shows a cross-sectional view of a MONOS memory cell on a substrate; the first picture B shows a cross-sectional view of a metal oxide semiconductor transistor on a substrate, and the first picture C shows a cross-section view on a substrate A cross-sectional view of the previous PIP capacitor; FIG. 2A shows a substrate having a memory cell region, a peripheral region, and a conductive layer covering the substrate, and the memory cell region has a sandwich layer; Figure 2B shows an ion implantation process performed on the structure shown in Figure 2A; Figure 2C shows the results of etching the conductor layer shown in Figure 2B; Figure D shows the removal of sandwiches Results of the top layer of the layer; Figure 2E shows the results of oxidizing the structure shown in Figure 2D;

495971 on page 15 The diagram briefly illustrates that the second F diagram shows the results of forming a conductor layer on the structure shown in the second E diagram; and the second G diagram shows the results of etching the conductor layer shown in the second F diagram . Representative symbols of the main parts: 1 0 0 substrate 1 0 2 oxide layer 1 0 4 silicon nitride layer 1 0 6 oxide layer 108 polycrystalline silicon layer 1 2 0 substrate 1 2 2 gate oxide layer 1 2 4 polycrystalline silicon gate Electrode 1 2 6 a source / drain 1 2 6 b source / drain 1 3 0 substrate 1 3 2 oxide layer 13 4 polycrystalline silicon layer electrode 1 3 6 oxide layer 1 3 8 polycrystalline silicon layer electrode 2 0 0 Substrate 2 0 2 dielectric layer

Page 16 495971 Brief description of drawings 2 0 4 dielectric layer 2 0 6 dielectric layer 2 0 8 conductor layer 2 0 8a conductor layer 2 0 8b conductor layer 2 1 0 photoresist layer 2 1 4 dielectric layer 2 1 6 a Dielectric layer 2 1 6 b Dielectric layer 2 1 8 a Dielectric layer 2 1 8 b Dielectric layer 2 2 0 Conductor layer 2 2 2 Dielectric layer page 17

Claims (1)

495971 VI. Scope of patent application 1. A method of forming an integrated circuit having a MONOS element and a mixed signal circuit, the method includes at least the following steps: providing a substrate having a memory cell region and a peripheral region, the The memory cell region has a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially stacked, and the peripheral region has the first dielectric layer; forming a first conductor layer to cover Forming a photoresist layer covering the memory cell area; implanting a plurality of ions into the first conductor layer; removing the photoresist layer; pattern transfer to etch the first conductor layer to form A second conductor layer and a third conductor layer on the peripheral region; removing the third dielectric layer to expose the second dielectric layer; removing the exposed first dielectric layer on the peripheral region Layer to expose the substrate; oxidize the second dielectric layer, the substrate, the second conductor layer, and the third conductor layer to form a fourth dielectric layer; and form a fourth conductor layer to cover the first dielectric layer Four dielectric layers; and pattern transfer for etching A fourth conductor layer to form a fifth conductive layer on the memory cell region and a sixth conductive layer over the fourth dielectric layer and the third conductive layer. 2. The method according to item 1 of the scope of patent application, wherein the first dielectric layer, a second dielectric layer, and a third dielectric layer described above include at least one hafnium dioxide silicon-silicon nitride-two Silicon oxide layer. Page 18 495971 6. Application scope of patent 3. The method as described in item 1 of the scope of application for patent, wherein the first conductor layer mentioned above includes at least one polycrystalline stone layer. 4. The method according to item 1 of the scope of patent application, wherein the ion described above includes at least an N-type implant ion. 5. The method according to item 1 of the scope of the patent application, wherein the ion described above includes at least a P-type implant ion. 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned oxidation process for oxidizing the second dielectric layer, the substrate, the second conductor layer and the third conductor layer includes at least one non-substrate selection Sexual oxidation process. 7. The method as described in item 1 of the scope of patent application, wherein the fourth dielectric layer described above includes at least a dioxide layer. 8. The method according to item 1 of the scope of patent application, wherein the fourth conductor layer mentioned above comprises at least one polycrystalline silicon layer. 9. A method of forming an integrated circuit having a MONOS element and a mixed-signal circuit, the method comprising at least the following steps: providing a substrate having a memory cell region and a peripheral region, the memory cell region having One of the first silicon dioxide layer, one silicon nitride Page 19 495971 VI. Patent application scope layer and a second silicon dioxide layer, and the peripheral area has the first silicon dioxide layer; forming a first conductor layer covering the memory cell area and the peripheral area; forming A photoresist layer covers the memory cell area; implanting a plurality of ions into the first conductor layer; removing the photoresist layer; pattern transfer to etch the first conductor layer to form a second conductor layer and a third conductor Layer on the peripheral region; removing the second silicon dioxide layer to expose the silicon nitride layer; removing the exposed first silicon dioxide layer on the peripheral region to expose the substrate, Oxidizing the silicon nitride layer, the substrate, the second conductor layer and the third conductor layer to form a third stone dioxide layer; forming a fourth conductor layer to cover the third silicon dioxide layer; and a pattern Transfer to etch the fourth conductor layer to form a fifth conductor layer on the memory cell region and a sixth conductor layer on the third silicon dioxide layer and the third conductor layer. 10. The method according to item 9 of the scope of the patent application, wherein the first conductive layer includes at least one polycrystalline silicon layer. 1 1. The method according to item 9 of the scope of the patent application, wherein the ions mentioned above include at least N-type implant ions. Page 20 495971 6. Application scope of patent 1 2. The method described in item 9 of the scope of application for patent, wherein the ion mentioned above includes at least P-type implant ion. 13. The method according to item 9 of the scope of patent application, wherein the above-mentioned oxidation process for oxidizing the second dielectric layer, the substrate, the second conductor layer, and the third conductor layer includes at least one non-substrate Selective oxidation process. 14. The method according to item 9 of the scope of patent application, wherein the fourth conductor layer described above comprises at least a polycrystalline silicon layer and W S i on the polycrystalline silicon layer. 15. A method of forming an integrated circuit having a MONOS element and a mixed-signal circuit, the method comprising at least the following steps: providing a substrate having a memory cell region and a peripheral region, the memory cell region having A first silicon dioxide layer, a nitride layer and a second silicon dioxide layer are sequentially stacked, and the peripheral region has the first silicon dioxide layer; a first conductor layer is formed to cover the memory Forming a photoresist layer to cover the memory cell area; implanting a plurality of ions into the first conductor layer; removing the photoresist layer; pattern transfer to etch the first conductor layer to form a first Two conductor layers and a third conductor layer on the peripheral region; removing the second silicon dioxide layer to expose the silicon nitride layer; removing the exposed first silicon dioxide layer on the peripheral region To Page 21 495971 6. The scope of the patent application exposes the substrate; oxidizes the silicon nitride layer, the substrate, the second conductor layer and the third conductor layer to form a third silicon dioxide layer and a non-substrate In a selective oxidation process, a fourth conductor layer is formed to cover the third silicon dioxide layer; and pattern transfer is performed to etch the fourth conductor layer to form a fifth conductor layer on the memory cell region and a sixth conductor layer. The third silicon dioxide layer is on the third conductor layer. 16. The method according to item 15 of the scope of the patent application, wherein the above-mentioned first conductive layer includes at least one polycrystalline silicon layer. 1 7. The method according to item 15 of the scope of patent application, wherein the ions mentioned above include at least N-type implant ions. 18. The method according to item 15 of the scope of patent application, wherein the ions described above include at least a P-type implant ion. 19. The method according to item 15 of the scope of patent application, wherein the fourth conductor layer described above includes at least a polycrystalline silicon layer and WS i φ 〇 2 0 located on the polycrystalline silicon layer. The method according to the item, wherein the fourth conductor layer is formed by a low-pressure chemical vapor deposition method. Page 22