TW495960B - Highly conformal titanium nitride deposition process for high aspect ratio structures - Google Patents

Highly conformal titanium nitride deposition process for high aspect ratio structures Download PDF

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TW495960B
TW495960B TW090115967A TW90115967A TW495960B TW 495960 B TW495960 B TW 495960B TW 090115967 A TW090115967 A TW 090115967A TW 90115967 A TW90115967 A TW 90115967A TW 495960 B TW495960 B TW 495960B
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aspect ratio
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ammonia
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Rajarao Jammy
Cheryl G Faltermeier
Uwe Schroeder
Kwong Hon Wong
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Infineon Technologies Corp
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/038Making the capacitor or connections thereto the capacitor being in a trench in the substrate

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Description

495960 A7 B7 五、發明説明(1 ) 發明範疇 概略而言,本發明係有關積體電路的製造。特別,本發 明係有關一種藉化學氣相沉積而沉積高度一致性氯化飲薄 膜之方法。 發明背景 氮化鈦(ΉΝ)於製造積體電路(1C)方法之一種重要材料具 有多項應用用途。薄膜氮化鈦廣用作爲矽1C之接觸擴散阻 擋層。此種用途的原因在於氮化鈥的表現類似珍之不透性 阻擋層,以及由於其它雜質擴散入氮化鈦之活化能高(例如 銅擴散入氮化鈦薄膜之活化能爲4.3電子伏特,而銅擴散入 金屬的正常値僅1至2電子伏特)。氮化欽防止有顯著量金屬 擴散入矽石出現接面波尖故障,造成跨接面短路。氮化鈦 的化學及熱力學性質也極爲安定。氮化鈦具有過渡金屬碳 化物、硼化物或氮化物之最低電子係數之一,全部皆屬化 學性質及熱性質安定化合物。 另一項應用中,使用氮化献作爲全面性沉積鶴薄膜之黏 著層。氮化欽係於介電層切割接線或通孔後沉積。典型介 電材料爲硼磷矽酸鹽玻璃(BPSG)、熱氧化物以及電漿加強 式氧化物及氮化碎。其次沉積全面性鎮,以及回蚀刻形成 柱塞,柱塞係於介電層頂部共面。然後鋁經沉積及圖樣化 而形成積體電路的金屬互連線。此一系列方法步驟通常重 複而形成三至四階金屬化階級。薄(例如厚度100毫微米)氮 化鈦黏著層係於沉積鎢之前沉積,原因在於鎢與典型介電 材料間之黏著性不良。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) A7
由於氮化鈦具有高度傳道 ,,„ ^ 地认 人傳寸性,故虱化鈦於高度緻密且複 4的結構例如深溝渠以、 乂及堆蘩電客器結構形成電極也是相 &具有吸引力的候選材料。 ,、 — ,、有低黾阻力的高度一致性薄 膜爲具有增加表面積之先進裝置結構所需,例如帶有半球 :顆粒的堆叠、有顆粒的冠狀物、帶有顆粒的深溝渠等。 薄陕氮化鈦可滿足該等需求。 於大部分應用,要求薄膜可維持—致厚度且無裂痕或空 隙:由於薄膜交叉出現於下方基板表面的階級,故可能非 ^望地偏離理想狀況例如變薄或裂開。薄膜如何維持名目 厚^的手&係以薄膜跨過一階時的最小厚度%對該薄膜於平 坦區的的名目厚度1之比表示。此種薄膜性質稱作薄膜的 「階遮盍率」表示爲於階出現的名目厚度百分比:階遮蓋 率(%)^/%>1〇〇%。以階遮蓋率爲100%較爲理想,但各種 方法係由對指定應用可接受的較小的最小値表示。 階南度及被遮蓋的結構縱橫比也決定預期的階遮蓋率。 階高度愈高或階之縱橫比(亦即單階之高度對寬度比,或毗 鄰二階之高度對間隔比)愈大,則愈難以遮蓋階而未造成薄 膜的減薄。因此,預期的階遮蓋率愈差。隨著微電子技術 的接觸維度不斷地縮小,以及縱橫比不斷地增加,等形接 觸層、襯墊、阻擋層及其它結構的形成逐漸變困難。 氮化鈦薄膜可藉若干不同方法形成,包括(1)濺鍍鈦至基 板然後於氮氣或氨氣反應:(2)於氮氣氛下反應性濺鍍鈦 ;以及(3)化學氣相沉積(CVD)。前二方法爲物理性方法, 獲得沉積材料的視線彈道。結果高縱橫比(亦即縱橫比大於 本紙張尺度適用中國國家標準(CNS) A4規格(21〇x297公釐)
495960 A7 B7 五、發明説明(3 ) 約1 : 45)之接觸側壁及底部遮蓋率比較基板頂面較差。 第二種方法C V D經由各種氣相組成分反應而沉積物質薄 膜於基板上。CVD方法用以產生稱作磊晶膜的單晶薄膜。 CVD讓沉積材料表面擴散。高縱橫比接觸之側壁及底部之 遮蓋率僅等於低縱橫比之基板頂面之遮蓋率。此外,用於 高縱橫比結構,CVD產生對溝渠侧壁之一致性性不良的薄 膜。 氮化鈦典型係使用CVD方法經由四氯化鈦(TiCl4)與氨氣 (NH3)以一對五以下(1 : <5)之比例範圍反應製成。兩種氣體 係以分開氣體線路輸送而於反應腔室内混合。習知得自四 氯化鈦之氮化鈦之CVD出現反應速率限制使用溫度之兩項 問題。第一問題爲反應速率慢,沉積時間延長。更重要地 ,於較低溫、,氯雜質留在沉積膜。氯雜質增加氮化鈦薄膜 的電阻。此外,氯腐蝕金屬特別鋁,損傷表面。Foster之美 國專利第5,378,501號揭示經由使用四氯化鈦及氨氣於稀釋 劑於低於55 〇°C溫度藉CVD沉積氮化鈥薄膜。Foster要求使 用特殊設備,但造成基板上邊界層厚度減至最低。 其它沉積方法有其本身缺點。Miyamoto之美國專利第 5,840,628號揭示一種電漿化學氣相沉積方法。電漿爲部分 游離氣體。欲製造電漿,裝置激發具有高縱橫比或微波頻 率的氣體。然後電漿發光、發射帶電粒子(離子及電子)、以 及中性活性成分(原子、準分子及自由基)。此等粒子及成分 撞擊被帶進電_漿環境的基板。Miyamoto揭示之電漿CVD方 法需要二步驟而非一步驟。 -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
495960 A7 B7 五、發明説明(4 ) 曾經提出多項解決之道用以沉積氮化鈦於低縱橫比結構 。例如美國專利第5,91 8,149號係針對沉積鋁或鋁合金於小 通孔或溝渠。該製法包括設置溝渠或通孔於介電質,阻擋 層伸展入溝渠或通孔。一層欽設置於阻擋層上,也伸展至 溝渠或通孔内部,鋁或鋁合金設置於鈦層上。阻擋層提供 良好一致性遮蓋率,同時也防止介電質向外流出對導體造 成不良影響。該方法包括以下特定步驟:(1)提供具有凹部 之氧化物介電質於晶圓;(2)加熱晶圓表面;(3)藉CVD方法 沉積氮化鈦阻擋層於凹部,其中氮化鈦來源材料係由晶圓 之加熱表面分解成爲氮化鈥;(4)沉積欽層於阻擋層上的凹 部,鈦層係藉物理氣相沉積方法沉積至小於200埃之厚度; (5)於室溫沉積鋁種晶層於鈦層上,其中種晶層厚2,000至 4,000埃:(6)加熱晶圓至425°C或以下;以及(7)沉積第二鋁 層於種晶層。 美國專利第5,192,589號提供另一種低縱橫比結構的解決 之道。揭示一種透過C VD形成薄形氮化飲薄膜之方法。沉 積方法係於低壓腔室(亦即壓力降至0. 1至2托耳之腔室)進行 ,使用氨氣及金屬-有機化合物肆(二甲基醯胺基)鈦 Ti(NMe2)4作爲前驅物。氨氣於沉-積腔室的流速維持於金屬-有機前驅物流速之約30倍。此種流速結果導致沉積的氮化 鈦薄膜隨著時間的經過當曝露於空氣環境時具有低的相對 恆定的體積電阻率。此外,沉積方法係於基板溫度至少200 。(:,理想上高達450°C進行俾讓沉積氮化鈦薄膜的體積電阻 率減至最低。 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495960 A7 —Β7 五、發明説明(5 ) 爲了克服習知沉積方法的缺點,提供新穎方法。本發明 之目的係提供一種可於高縱橫比結構上達成沉積高度一致 性高品質氮化鈦薄膜之改良方法。本發明之相關目的係達 成趨近於100%的階遮蓋率。另一目的係提供可於具有低電 阻之南縱橫比結構達成沉積之方法。又另一目的係提供_ 種可於高縱橫比結構以可接受的污染達成沉積之方法。本 發明也有一目的係提供一種比較習知方法無需使用特殊設 備或額外步驟之方法。 發明概要 爲了達成此等及其它目的,有鑑於其目的,本發明提供 一種藉CVD於半導體基板表面沉積高度一致性氮化鈦薄膜 之方法。該方法包括下列步驟:(1)提供具有表面之半導體 基板;(2)維持基板表面於約350°C至約800。(:溫度;(3)形成 包含四氯化鈥、氨氣以及選擇性稀釋劑之氣態反應混合物 ’其中四氯化鈥對氨之比爲約5:1至20:1 ;以及(4)氣態反典 混合物通過半導體基板表面。須了解前文概略説明及後文 詳細説明僅供舉例説明之用而非限制本發明。 圖式之簡單説明 由後文詳細説明連同附圖一起研讀將最爲了解本發明 。須強調根據一般實務,圖式的各項結構並未照比例緣製 。相反地,各種結構的尺寸任意放大或縮小以求清晰。附 圖包括: 圖1 a至1 e提供舉例説明可有利地使用本發明方法以氮化 欽填補的結構類型,特別圖la顯示含有高縱橫比的深溝渠 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) -8 - 495960 A7 B7 五、發明説明(6 ) 其上已經沉積氮化鈦層基板; 圖lb顯示含有高縱橫比之深溝渠的基板,一層半球晶粒 沉積於溝渠,氮化鈦沉積於溝渠及半球形晶粒上; 圖1 c顯示基板含有高縱橫比堆疊電容器,其上已經沉積 氮化鈥; 圖Id顯示一種含高縱橫比堆疊電容器之基板,一層半球 晶粒沉積於基板上,以及氮化鈦沉積於該結構及半球晶粒 上: 圖le顯示一片基板含有高縱橫比之複雜堆疊結構,其上 已經沉積氮化鈦; 圖2a爲使用本發明方法沉積氮化鈦於溝渠後具有縱橫比 約4 0 : 1之溝渠頂部的知描電子顯微相片(S E Μ);以及 圖2b爲圖2a所示溝渠之底部之掃描電子顯微相片。 發明之詳細説明 全文説明書中,類似參考編號表示附圖中各圖類似的元 件。本發明爲一種藉低溫CVD高度一致性高品質氮化鈦薄 膜之方法,該薄膜具有極低體積電阻率及絕佳階級遮蓋率 。氮化鈥層之氯含量低於5 %。所述方法爲概略方法,容易 擴充至其它金屬及金屬氮化物系統而僅有微小修改。全部 列舉的數値係指單一晶圓裝置,但也可略爲修改而使用爐 。特別本發明非僅限於任何特定形狀的構造或任何單獨記 憶裝置。 於典型CVD方法,欲沉積的基板置於反應腔室,加熱至 足夠讓前驅物複合物蒸氣沉積的溫度。此等蒸氣被導入反 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495960 A7 B7 五、發明説明(7 應腔室内且運送至基板附近。然後蒸氣於基板上分解,沉 積預定材料薄膜於基板上。 反應本身使用至少兩種反應物··四氯化鈦(Ticl4)及氨氣 (NH3)。四氯化飲及氨氣係使用約5 : 1至約·· 1 (容積對容 積),較佳約8 : 1至約15 :丨,更佳約1〇 :丨的比例,對照習 知方法使用的比例低於約5 : !。雖然對CVD並非必要或較 佳知有所茜可使用咼達約1 〇倍過量的稀釋劑。稀釋劑可 爲氣體例如氦、氬、氫或氮氣。 化學氣相沉積可於習知氣相沉積系統進行,例如業界人 士所熟知的系統進行。半導體基板表面維持於低於約88〇ό ,典型約350°C至約650X:,及較佳約45(TC至55(TC溫度。總 氣體流速須爲約100 sccm至約sccm,進氣溫度須爲約 150°C 〇 匕藉本發明方法達成高—致性程度,允許該方法以氮化欽 G補複4的一度义間結構而未形成大裂缝或空隙。氮化鈥 方便沉積於難以達到的表面上。圖“至^説明可藉本發明 方法沉積氮化鈦層之三度空間結構類型。 圖la顯示基板10含有高縱橫比深溝渠12,溝渠内已經沉 %虱化鈦層16。氮化鈦層16係使用本發明方法沉積。較佳 深溝渠12具有縱橫比至少約4〇 :丨,更佳至少約45 : 1,及 又更佳至少約45 : 1至16〇 : i。具有縱橫比大於45 : t之深 冓^ ”構以及其i類似的南縱橫比結構之製備爲業界人 士眾所周知。 圖lb顯示基板20含有高縱橫比深溝渠22。一層半球形晶 -10-
495960 A7 B7 五、發明説明(8 ) 粒(HSG)24沉積或生長於深溝渠22。半球形晶粒24粗化深溝 渠22表面,因而增加有效面積,如此提高電阻。氮化欽26 係使用根據本發明方法沉積於深溝渠22内部,以及半球形 晶粒24表面上。 半球形晶粒沉積或生長於結構係揭示於Watanabe之美國 專利第5,366,917號。Watanabe揭示表面有顯微粗度的多晶 矽層可基於矽晶粒的生長形成。一種揭示方法包括根據 LPCVD方法於沉積薄膜之晶體態由非晶相變遷至多晶相的 溫度(稱作轉化溫度)沉積矽於基板。另一方法爲其中非晶矽 (a-Si)薄膜於眞空或於惰性氣體例如氮氣形成於基板上,然 後試樣再度於眞空或於惰性氣體例如氮氣於高於轉化溫度 之溫度進行加熱(退化處理)。根據該方法,可經由排它使用 CVD方法或CVD方法組合形成具有顯微粗度表面之多晶矽 薄膜以及退火該薄膜爲眾所周知的半導體製造技術。 圖lc顯示含高縱橫比堆疊電容器32之基板30,電容器上 已經沉積氮化鈦層36。氮化鈦層36係使用本發明方法沉積 。較佳堆疊電容器32具有縱橫比至少約4 : 1。具有縱橫比 至少4 : 1之堆疊電容器結構之製備爲業界人士所熟知。 圖Id顯示含高縱橫比堆疊電容器42之基板40。半球形晶 粒(HSG)44沉積於結構上而增加有效表面積,如此提高電阻 。氮化鈥層46使用本發明方法沉積於結構及半球形晶粒上 。本發明方法也可用於沉積氮化鈦層於具有高縱橫比的同 心柱上。 _ 圖le顯示具有高縱橫比含細小或梳狀結構之複雜堆疊結 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495960 A7 B7 五、發明説明(9 構52的基板50。化欽層冗使用本發明方法沉積於結構上。 應用本發明方法對具有高縱橫比的溝渠可達成60%至 100%的階級遮蓋率。於具有縱橫比大於1〇 : 1之深溝渠,特 別具有縱検比約45 : 1或以上,較佳具有縱橫比約45 : 1至 約160 : 1之溝渠可沉積高度一致性氮化鈦薄膜。 產業應用 本發明方法可用以於高縱橫比通孔、接觸孔及柱塞形成 接觸線或阻擋層。本發明方法也可對高縱橫比深溝渠及堆 登電客器結構形成氮化鈦電容器電極。此等裝置及結構可 用於製造半導體裝置例如用於數位電腦。 實例 下列實例係供更明白驗證本發明的整體特色。本實例僅 供舉例説明而非限制本發明。氮化鈦係經由四氯化鈦與氨 氣反應形成。反應係於應用材料公司單一晶圓工具化學氣 相沉積系統進行。 使用5 : 1至20 : 1範圍之四氯化鈦/氨比(容積對容積)。各 氣體係於氣體分開管線輸送。氣體係於CVD裝置之反應腔 1:混合。研究於O.OOOi粍耳至5〇托耳範圍之壓力,以及350 °(:至800乇範圍之溫度。只要條件係控制於規定的反應計畫 以内,則可於寬廣的處理條件製造一致性氮化鈦3 於500 C及4托耳(氨=50 sccm及四氣化鈦=5〇〇 sccm)可獲 得絕佳階級遮盍率。氮化鈥層之氣含量低於5%。圖2&及圖 2b顯7F於此等條件下於具有縱橫比約4〇 ·· 1的溝渠沉積氮化 鈦。圖2a顯示溝渠頂部。圖2b顯示溝渠底部。矽基板6〇包 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公复) m 裝 η
495960 A7 B7 五、發明説明(1〇 ) 含二溝渠62及64。於溝渠62及64之側壁及底部形成均勻且 高度一致性的氮化鈦薄膜66及68。 雖然已經特別顯示及參照較佳具體實施例説明本發明, 但業界人士了解未悖離本發明之精髓及範圍可就形式及細 節上作出多種修改及變化。例如於前文説明列舉特定細節 俾供更徹底了解本發明,但熟諳技藝人士無需使用此等特 定細節即可實施本發明。 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)

Claims (1)

  1. 495960 A8 B8 C8 六、申請專利範圍 L 一種沉積高度一致性氮化鈦薄膜於半導體基板表面之方 •法,該方法包含下列步驟: 提供具有表面之半導體基板; 維持基板表面於約350°C溫度至約800°C的溫度; 形成包括四氯化鈦及氨之氣態反應混合物,其中四氯 化鈦對氨之比爲約5 : 1至20 : 1 ;以及 氣悲反應混合物通過半導體基板表面。 2·如申請專利範圍第1項之方法,其中該氣態反應混合物進 一步包括稀釋劑。 3.如申請專利範圍第1項之方法,其中四氮化鈦對氨之比爲 約 8 : 1 至 1 5 : 1。 4·如申請專利範圍第1項之方法,其中該表面爲具有高縱橫 比至少1 : 1的結構表面。 如申请專利範圍第1項之方法,其中該氣態反應混合物具 有泥速爲約100 sccm至約1,〇〇〇 sccm 6·如申请專利範圍第丨項之方法,其中半導體基板表面溫度 係維持於約35CTC至約65CTC。 如申請專利範圍第6項之方法,其中四氯化鈦對氨之比爲 :1 至 15 : 1 〇 如申請專利範圍第7項之方法 係維持於約450°C至約550°C。 如申请專利範圍第6項之方法 約 10 : 1 〇 其中半導體基板表面溫度 約 10 : 1 〇 其中四氣化鈦對氨之比爲
    本紙 準(CNS) A4 規格 _Χ297:^ 奶960 A8 B8 C8
    ^、申請專利範圍 土少40.1之溝渠表面。 11· ‘如申請專利範圍第10項之方法,其中四氯化鈦對氨之比 爲約8 : 1至1 5 : 1。 12·如申請專利範圍第11項之方法,其中該氣態反應混合物 具有流速爲約100 sccin至約1,〇〇〇 seem。 13 ’如申請專利範圍第12項之方法,其中該半導體基板表面 溫度係維持於約350°C至約650°C。 14·如申请專利範圍第13項之方法,其中該氣態反應混合物 具有流速爲約550 seem。 U·如申請專利範圍第丨項之方法,其中該氣態反應混合物不 包括稀釋劑。 16. 如申請專利範圍第15項之方法,其中該四氣化鈦對氨之 比爲約8 : 1至1 5 : 1。 17. 如申請專利範圍第16項之方法,其中該表面爲具有縱橫 比至少1 : 1之結構表面。 1 8.如申請專利範圍第16項之方法,其中該表面爲具有縱橫 比至少40 : 1之溝渠表面。 19.如申請專利範圍第16項之方法,其中該表面爲具有縱橫 比至少4: 1之堆疊電容器表面。 20·如申請專利範圍第16項之方法,其中該半導體基板表面 溫度係維持於約350°C至約65CTC。’ 21. 如申請專利範圍第2〇項之方法,其中該四氯化鈦對氨之 比爲約1 0 ·· 1。 22. 如申請專利範圍第2丨項之方法,其中該氣態反應混合物 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 495960 8 8 8 8 A B c D 六、申請專利範圍 具有流速爲約100 seem至約1,000 seem。 23· ·如申請專利範圍第22項之方法,其中該表面爲具有縱橫 比至少4 ·· 1之堆疊電容器表面。 24.如申請專利範圍第22項之方法,其中該表面爲具有縱橫 比至少40 : 1之溝渠表面。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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