495929 A7 B7 五、發明説明（ (一）發明領域·· 本發明係有關-種具凹陷式浮置閘之快閃記憶體的製 造方法，尤指-種可提供可消许鳥嘴現象（blrdbeak)，達成 更準確穩定的位元線區，使可減增加之快耽憶體製造方 法 經濟部中央樣準局員工消費合作社印装 (二）習用技術的說明： 快閃記憶體（flash memory) —般而言，快閃記憶體是 由記憶胞陣列（memory cell array)與週邊電路兩大部分所組 成，其中作為資料儲存的快閃記憶胞陣列是由許多記憶胞排 列整齊於_交錯的字元線（丽dline)與位元線（bi他e) 中所構成。而週邊電路則是提供快閃記憶體操作時所需的電 源供應電路，及資料輸人、触蝴電路。依_極電極形 狀分類，快閃記憶胞在堆疊閘式（stack_gate)快閃記憶胞方 面，其中浮置閘（floating gate)與堆疊其上之控制閘之電容 耦合。 而美國專利U.S· No, 6,084,265係揭露一種高密度渠溝式 無接點非揮發性記憶體的技術。請參閱圖一至圖九之製程示 思圖，在一半導體基板2上形成一氧化石夕層作墊氧化層4， 及氮化矽層6作氧化遮罩。藉助光阻8，以微影蝕刻技術定软 出埋藏位元線之圖形。對未被光阻8覆蓋之區域進行離子植 入，形成位元線10。 接著去除光阻8，以傳統區域氧化法（L〇Cal 〇xidatiQn ^ Silicon，LOCOS)技術高溫氧化形成場氧化層12，同時完成 以 義 of (請先閱讀背面之注意事項再填寫本頁) 一裝- 訂 &濟部中央樣準局員工消費合作衽印製 495929 Α7 _____Β7 五、發明説明（V) — ~ 位元線10之定義。去除氣化石夕層6及塾氧化層4非等向性餘則 形成渠溝區。覆上一氮氧化層14於基板2及渠溝表面上，係作 為穿遂介電層。 ^ 最後，沈積一多晶矽層，並填滿於該渠溝區域中，將其 平坦化，以形成浮置閘16。 〃 然而明顯地，該習用之LOCOS技術在高溫氧化形成場氧 化層12時，則容易因此造成鳥嘴現象（blrdbea]〇，並使得摻 雜之位元線區10造成雜質濃度不均之嚴重現象，同時，鳥^ 現象之侧向擴散亦縮小了後續浮置閘（如此％ _} _ H 且不易準確控辦置_寬度，不但因而增加製程的^雜 度，使可靠度不佳而降低良率，增加製造成本，影響其競爭 力。在積體電路製程進入次微米或深次微米魄術時，、^去 更提升快航髓的電性，也將使產品品質無法提升，^失 去市場的競爭優勢，落後其他競爭對手。 (三）發明之簡要說明： 本發明之-目的為提供-種具凹陷式浮 體的製造方法，可消弭^喈頦參, λ 雜度，使可靠度增mm 降低製㈣複 Γ為提供-種具凹陷式_，之快閃記 兩次溝渠形叙特殊技術，_ 成更皁销乂的位猶區之快閃記憶體。 本發縣達上述目的，故提種具凹 (請先閲讀背面之注意事項再填寫本頁) 訂 閃記憶體的製造方法，其難實施步驟係為··於L半4體基495929 A7 B7 V. Description of the Invention (1) Field of Invention The present invention relates to a method for manufacturing a flash memory with a recessed floating gate, especially a method that can provide a bird's beak phenomenon (blrdbeak) ), To achieve a more accurate and stable bit line area, so that the increase can be reduced quickly. The manufacturing method of the Ministry of Economic Affairs of the Central Bureau of Prospects and Staff Consumer Cooperatives (2) Description of the conventional technology: flash memory -In general, flash memory is composed of two parts: memory cell array and peripheral circuits. Among them, the flash memory array used as data storage is composed of many memory cells arranged neatly in _ interleaved words. Yuan line (Li dline) and bit line (bite). And the peripheral circuit is to provide the power supply circuit required for flash memory operation, and the data input and touch circuit. Electrode shape classification, flash memory cells in the stack gate (stack_gate) flash memory cells, where the floating gate (floating gate) and the control gate stacked on the capacitive coupling. And US Patent No. 6,084,265 series disclosed One High-density trench-type non-contact non-volatile memory technology. Please refer to the process diagrams of FIGS. 1 to 9 to form a silicon oxide layer as a pad oxide layer 4 on a semiconductor substrate 2 and silicon nitride. Layer 6 is used as an oxidation mask. With the help of photoresist 8, the pattern of buried bit lines is determined by lithographic etching. The areas not covered by photoresist 8 are ion-implanted to form bit lines 10. Next, the light is removed. Resistor 8. The field oxide layer 12 is formed by high temperature oxidation using the traditional area oxidation method (LoCal 〇xidatiQn ^ Silicon, LOCOS) technology. At the same time, complete the meaning of (Please read the precautions on the back before filling this page). & Consumption Cooperation for Employees of the Central Bureau of Procurement and Printing, Ministry of Economic Affairs, 495929 Α7 _____ Β7 V. Description of the Invention (V) — ~ Definition of bit line 10. Remove the anisotropy of gas layer 6 and tritium oxide layer 4 A trench area is formed. An oxynitride layer 14 is coated on the substrate 2 and the surface of the trench as a tunnel dielectric layer. ^ Finally, a polycrystalline silicon layer is deposited and filled in the trench area to flatten it To form a floating gate 16. 〃 However, obviously When LOCOS technology is used to form the field oxide layer 12 at high temperature, it is easy to cause the bird's beak phenomenon (blrdbea), and cause the doped bit line region 10 to cause a serious phenomenon of uneven impurity concentration. At the same time, the bird ^ phenomenon Lateral diffusion also reduces subsequent floating gates (so% _} _ H and it is not easy to accurately control the width of __, which not only increases the complexity of the process, reduces reliability, reduces yield, increases manufacturing costs, affects Its competitiveness. When the integrated circuit manufacturing process enters the sub-micron or deep sub-micron technology, the improvement of the electrical properties of the fast navigation marrow will also make the product quality unable to improve, ^ lose the competitive advantage of the market, and lag behind other competition opponent. (3) Brief description of the invention: The purpose of the present invention is to provide a method for manufacturing a recessed floating body, which can eliminate 喈 颏 喈 颏, λ heterogeneity, increase the reliability, reduce the production process, and provide 为- This kind of special flash memory has two trench-shaped special techniques, and it becomes a flash memory in a more volatile area. Benfa County achieves the above purpose, so it has a concave type (please read the precautions on the back before filling this page). Order the manufacturing method of flash memory. The difficult steps are: ...
• I- II 495929 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（》） 序沈積一墊氧化層及一第一介電層。接著，使用微影 旦非等向性蝴（amsGtiOpieetehmg)·®案化該第—介電層， 而形成若干_之_式浮置_渠，以定義纽元線之圖 二進行離子植入形成位元線（源及/汲極區），再沈積一第 -介電層填滿各該凹赋浮制溝渠，進行平坦化。 接了為本發明重點之一，移除該第一介電層，使得各該 相間之第二介電層反形成突出者。再以該第二介電層為遮 罩’進行電滎侧形成若干溝渠。形成一穿 科半 :體基板及各該溝渠表面上’沈積-第-導電層填二 朱，亚平坦化，以形成凹陷式浮置閘。 -灸再’尤積一第二介電層及一第二導電層，圖案化該第 一令電層，以形成一控制閘（control gate)。 為進—步對本發明有更私的說明，乃藉由以下圖示、 圖錢明及發明詳細說明，冀能對貴審查委員 時有所助益。 、令一邗 (四）圖式簡要說明·· 意圖圖-至圖人為習用技術快閃記憶體閘極的製程步驟示 圖九係為本發明較佳實施例中，在一半導體美 依序形成—墊氧化層及-第-介電層之示意圖^反上， 圖十為本發明較佳實施例中，圖案 形成若干相間之凹陷式浮置間溝渠之示意/圖弟一介電層， 圖十-為本發输佳實_巾，柄離顿入，形成 T I—--------訂·-------- (請先閱讀背面之注意事項再填寫本頁)• I-II 495929 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of Invention (") An oxide layer and a first dielectric layer are deposited in sequence. Next, we used amsGtiOpieetehmg · ® to pattern the first dielectric layer to form a number of _-style floating_channels to define the nucleus line and perform ion implantation. Bit lines (source and / drain regions), and then a first dielectric layer is deposited to fill each of the recessed floating trenches for planarization. This is one of the key points of the present invention, and the first dielectric layer is removed, so that the second dielectric layers between the phases are formed into protrusions instead. Then, a plurality of trenches are formed on the electrical side using the second dielectric layer as a mask. A semi-transparent layer is formed: the body substrate and the surface of each of the trenches are filled with 'deposited-first-conductive layers', and sub-flattened to form a recessed floating gate. -Moxibustion is further accumulating a second dielectric layer and a second conductive layer, and patterning the first ordering layer to form a control gate. For a more private explanation of the present invention, the following illustrations, drawings, and detailed description of the invention are intended to help your review committee. 1. Let's briefly explain the schematic diagram. · Intent diagram-to the diagram of the process steps of the conventional flash memory gate. Figure 9 is a preferred embodiment of the present invention. -Schematic diagram of pad oxide layer and -dielectric layer ^ Conversely, Fig. 10 is a schematic diagram of a pattern of forming several interdented floating floating trenches in a preferred embodiment of the present invention / Figure 1, a dielectric layer, Ten-lose the best _ towel for this hair, the handle is closed, forming TI ——-------- Order · -------- (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 495929 A7 B7 五、發明說明（ψ) 位元線之示意圖。 圖十二為本發明較佳實施例中.，沈積第二介電層填滿 各凹陷式浮置閘溝渠，再進行坦化之示意圖。 圖十三為本發明較佳實施例中，移除該第一介電層， 使得各該相間之第二介電層形成突出者。 圖十四為本發明較佳實施例中，以該第二介電層為遮 罩，進行蝕刻形成若干溝渠之示意圖。 圖十五為本發明較佳實施例中，形成一穿遂介電層於 該基板及各該溝渠表面上之不意圖。 圖十六為本發明較佳實施例中，沈積一第一導電層填 滿各該溝渠，並進行平坦化之示意圖。 圖十七為本發明較佳實施例中，沈積第三介電層及第二 導電層，圖案化以形成控制閘之示意圖。 圖號說明： 2, 100-半導體基板 4, 105-墊氧化層 6-氮化矽層 8-光阻層 10-位元線 12-場氧化層 14-氮氧化層 16-浮置閘 18-多晶矽介電層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) π裝--------訂----------線論 A7 -----^---——_ 五、發明說明（f ) 20-導電層 120-第一介電層 125-凹陷式浮置閘溝渠 130-離子植入 135-位元線 140-第一介電層 145-穿隧介電層 150-第一導電層 160-第三介電層 165-第二導電層 (五)本發明之詳細描述： 本發明係揭露一種具凹陷式浮置閘之快閃記憶體的製 造方法，其步驟係用以下圖式表示之：如圖九所示，提供一 半導體基板10，依序沈積一塾氧化層105及一第一介電層 120。其中該墊氧化層105可為一氧化矽層，可作為遮罩及離 子植入中之犧牲層；而該第一介電層120可為一氡化矽層，其 厚度介於200〜1200A之間。 經濟部智慧財產局員工消費合作社印製 接著’使用微影暨非等向性钱刻（anisotropic etching) 圖案化該第一介電層120,而形成若干相間之凹陷式浮置閘溝 渠125，以定義出位元線之圖形。需注意的是，圖 圖案化該介電層120、墊氧化層105及部分基板100，而當_ 因實務需求，只侧第-介電層120,亦可形成若干相間之凹 陷式浮置閘溝渠125。 ，Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 495929 A7 B7 V. Schematic diagram of the bit line of the invention description (ψ). FIG. 12 is a schematic view of a preferred embodiment of the present invention, in which a second dielectric layer is deposited to fill each of the recessed floating gate trenches, and then is subjected to frankization. FIG. 13 is a preferred embodiment of the present invention, removing the first dielectric layer, so that the second dielectric layers between the phases form protrusions. FIG. 14 is a schematic diagram of forming a plurality of trenches by using the second dielectric layer as a mask in a preferred embodiment of the present invention. FIG. 15 is a schematic diagram of a tunnel dielectric layer formed on the substrate and each of the trench surfaces in a preferred embodiment of the present invention. FIG. 16 is a schematic diagram of depositing a first conductive layer to fill each of the trenches and performing planarization in a preferred embodiment of the present invention. FIG. 17 is a schematic diagram of a third dielectric layer and a second conductive layer deposited and patterned to form a control gate in a preferred embodiment of the present invention. Description of drawing numbers: 2, 100-semiconductor substrate 4, 105-pad oxide layer 6-silicon nitride layer 8-photoresist layer 10-bit line 12-field oxide layer 14-nitrogen oxide layer 16-floating gate 18- Polycrystalline silicon dielectric layer This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) ------- Line theory A7 ----- ^ -------_ V. Description of the invention (f) 20-conductive layer 120-first dielectric layer 125-depressed floating gate trench 130- Ion implantation 135-bit line 140-first dielectric layer 145-tunneling dielectric layer 150-first conductive layer 160-third dielectric layer 165-second conductive layer (5) Detailed description of the present invention: The invention discloses a method for manufacturing a flash memory with a recessed floating gate. The steps are represented by the following diagram: as shown in FIG. 9, a semiconductor substrate 10 is provided, and a hafnium oxide layer 105 is sequentially deposited. And a first dielectric layer 120. The pad oxide layer 105 can be a silicon oxide layer, which can be used as a sacrificial layer in masks and ion implantation; and the first dielectric layer 120 can be a silicon oxide layer, which has a thickness between 200 and 1200 A. between. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and then using lithography and anisotropic etching to pattern the first dielectric layer 120 to form a number of recessed floating gate trenches 125 in order to Define the graphics of the bit lines. It should be noted that the pattern patterned the dielectric layer 120, the pad oxide layer 105, and part of the substrate 100. However, due to practical requirements, only the first-dielectric layer 120 can be used to form a number of recessed floating gates. Ditch 125. ,
495929 A7 丨丨丨_丨丨 ' ------------- -B7 五、發明說明（U ) 如圖十一所示，進行離子植入13〇，將雜質離子植入基 板100内，以形成位元線135 (源及/汲極區）。而雜質離子二 N型離子之磷離子、坤離子等。 如圖十二所示，沈積一第二介電層140填滿各該凹陷式 浮置閘溝渠125，再進行化學機械研磨（CMp)以平坦化， 而第一介電層120則為研磨終止層，如圖十二所示。其中該第 二介電層140係可為一氧化矽層，其厚度在5〇〇〜35〇〇人之間。 接下為本發明重點之一，如圖十三所示移除該第一介電 層120，使得各該相間之第二介電層⑽反形成突出者。再接 著以該第二介電層140為遮罩（mask)，進行電漿餘刻（pla_ etchmg)形成若干溝渠（圖中未標示），如針四所示。 形成-穿遂介電層145於該半得體基板及各該溝渠 表面上，其中該穿遂介電層145係為高介電係數層，係可為氣 化氧化層（NO)或氧化氮化氧化層（〇N〇)其中一種，如 圖十五所示。 如圖十六所示，沈積一第一導電層150填滿各該溝渠， 並進行化學機械研磨以平坦化，而穿遂介電層⑷則為研磨線 止層，以形成凹陷式浮置閘。其中該第一導電層15〇係為多晶 石夕（polysmcon)、金屬石夕化物（metal silidde)或非晶石夕 (amorphous silicon)其中一種’且其厚度在5〇〇人至4〇〇〇 間。 最後如圖十七所示，再沈積—第三介電層16〇及一第二 導電層165，接著圖案化該第二導電層，以形成一控制間 (C〇咖1_)(圖中未示），其係為多晶石夕或金屬石夕化物 本紙張尺度顧巾關家標準(CNS)A4規^7i10 x 297〖$ ill —-----_裝 (請先閱讀背面之注意事項再填寫本頁) n HI n I in 1 ϋ— ι_ϋ in · 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（7 ) ^*~ -- 或非晶石夕其中—種，而厚度在5〇〇人至·〇人間。 。縱上所述’本發明以特殊之凹陪式浮置間製程，不需如 習知技術形成場氧化層，且亦能消拜鳥嘴現象（匕祕⑷， 達成更準確穩定的位元線區，使可靠度增加之快閃記憶體製 法。 本發明於習知技術領域上無_之技術婦，已具新顆 性；本發明之技_容可確實解贼躺之問題，且方法原 $屬非根據習知技藝而易於完成者，其功效性業已經詳述， κ /、進步&，又本發明制之技術#法及所需賴本身係屬 於本技術領域，亦具產業之可利用性。因此，基於鼓勵發明 i的，專利之惠准應根據專槪與專稱查基準之精神，相 h貝審查委貞雜鲜之審查實務錄，亦能綱本案符合 專利要件及專糧神，此種技術並非—般人士所易於能思及 者’此點尚祈貴審查委員公正考量明鑒之，盼能早日核准 專利，實為感禱。 本發明之®式與描軌較佳實_說明如上，僅用於藉 以幫助了解本發明之實施’非用以限定本發明之精神，而熟 悉此領域技藝者於領悟本發明之精神後，在不脫離本發明之 知神範圍内’當可作些許更動潤飾及_之變化替換，其專 利保護範圍當視後附之申請專利範圍及其等同領域495929 A7 丨 丨 丨 _ 丨 丨 '------------- -B7 V. Description of the invention (U) As shown in Fig. 11, ion implantation 13 is performed, and impurity ions are implanted. Within the substrate 100, bit lines 135 (source and / drain regions) are formed. The impurity ions are phosphorus ions and N-type ions. As shown in FIG. 12, a second dielectric layer 140 is deposited to fill each of the recessed floating gate trenches 125, and then chemical mechanical polishing (CMp) is performed to planarize the first dielectric layer 120. Layer, as shown in Figure 12. The second dielectric layer 140 may be a silicon oxide layer, and its thickness is between 500 and 3500 people. Next is one of the key points of the present invention. As shown in FIG. 13, the first dielectric layer 120 is removed, so that the second dielectric layers between the phases form a protrusion instead. Then, the second dielectric layer 140 is used as a mask to perform plasma etching (pla_etchmg) to form a plurality of trenches (not shown in the figure), as shown in pin four. A tunneling dielectric layer 145 is formed on the semi-substrate substrate and the surface of each of the trenches. The tunneling dielectric layer 145 is a high-dielectric-constant layer, which may be a vaporized oxide layer (NO) or oxidized nitride. One of the oxide layers (ONO) is shown in Figure 15. As shown in FIG. 16, a first conductive layer 150 is deposited to fill each of the trenches, and is chemically and mechanically polished for planarization, and the tunnel dielectric layer is a polishing line stop layer to form a recessed floating gate. . Wherein, the first conductive layer 15 is one of polysmcon, metal silidde or amorphous silicon, and its thickness ranges from 500 to 400. 〇 间。 Between. Finally, as shown in FIG. 17, a third dielectric layer 160 and a second conductive layer 165 are re-deposited, and then the second conductive layer is patterned to form a control cell (C0Ca 1_) (not shown in the figure). (Shown), it is a polycrystalline stone or a metal stone, and the paper standard is based on the Chinese Standard (CNS) A4 ^ 7i10 x 297 [$ ill —-----_ equipment (please read the note on the back first) Please fill in this page for more information.) N HI n I in 1 The thickness is between 500 and .00. . According to the above description, the present invention uses a special concave-fed floating process, which does not need to form a field oxide layer as in the conventional technology, and can also eliminate the bird's beak phenomenon (Dagger Secret, achieving a more accurate and stable bit line The flash memory system method that increases reliability increases. The present invention has new characteristics in the technical women who are not in the conventional technical field; the technology of the present invention can definitely solve the problem of lying thieves, and the method is original $ Is a person who is not easy to complete based on the know-how. Its efficacy has been detailed. Κ / 、 progress & Availability. Therefore, based on the encouragement of inventions i, the benefits of patents should be in accordance with the spirit of the patent and the standard of reference. The examination practice records of the review committee can also meet the requirements of patents and patents. Food god, this technology is not easy for ordinary people to think about. 'This point is to pray that the reviewing committee can consider the lessons learned fairly and hope that the patent can be approved at an early date. It is really a prayer. The description is as above, only to help understand the present invention The implementation of 'is not intended to limit the spirit of the invention, and those skilled in the art can understand the spirit of the invention and do not depart from the scope of the god of the invention'. The scope of protection should be regarded as the scope of patent application and its equivalent