TW495918B - Manufacturing method of copper dual damascene with selectively deposited barrier layer - Google Patents

Abstract

The present invention relates to a method for manufacturing trench barrier layer of copper dual damascene, in which titanium nitride containing silicon [TiN(Si)] formed by adding silicon dopant into titanium nitride (TiN) is used as the barrier layer material of dual-damascene trench. Titanium nitride containing silicon [TiN(Si)] has the characteristic of selective deposition rate for different materials such that the chemical vapor phase deposition rate on the copper is lower than that on the other inter-metal dielectric layer. By appropriately controlling the deposition time, a barrier thin film of titanium nitride containing silicon with a certain thickness is formed on the dielectric layer of the trench sidewall in order to prevent the electric migration between the conducting copper wire and the dielectric layer. On the other hand, noticeable deposition of barrier layer is not formed on the copper during the same time. Therefore, the resistivity between the upper and the lower conducting wires is decreased such that the effect of too high RC time delay can be avoided and the speed performance of device can be improved.

Description

495918 V. Description of the invention (1) Field of the invention: The present invention relates to a copper dual damascene process method for semiconductors, especially a dual damascene barrier material containing titanium silicon nitride [T 1 N (S i)] for different materials. Process method for selective chemical vapor deposition rate. Background of the invention: In order to achieve the purpose of reducing the size of components and reducing costs, the semiconductor industry is moving towards the trend of arranging components and their connecting metal wires on a wafer at a high density. Therefore, the metal wires are relatively thinner, which increases the resistance of the wires. . Due to the resistance value R of the wire, there will be a capacitance C between the upper and lower wires and the adjacent wire of the same layer. The lower the RC value, the lower the time delay. Therefore, the appropriate process technology is developed to reduce the RC time of the wire. Delay has become the goal of the semiconductor industry. At the same time, as the metal wires of components become thinner and denser, the accompanying barrier layer should be relatively thin without affecting its barrier properties. The dual damascene process method is a multilevel interconnect technology that can form both vertical and horizontal connections. The traditional copper dual damascene process first uses a traditional dry etching technique to complete the dual damascene trench pattern of the wire trench pattern and the via hole structure. Next, one of the techniques is to deposit the surface of the dual damascene trench by a physical vapor deposition method (Ph y s i c a 1 V a p0r De e p o s i t i ο n) method or a chemical vapor deposition method.

495918 V. Description of the invention (2) Form a barrier layer with uniform thickness, and then use the electroless copper method, physical vapor deposition method, or chemical vapor deposition method to form a copper seed layer on the side wall of the wire trench and the via hole and On the bottom. Another newer technology uses a physical vapor deposition method to form a trench barrier layer after forming a dual mosaic pattern, and then immerses it in an activating solution to form a copper seed layer on the barrier layer. Next, electroplated copper is used to fill the trenches and vias. Finally, the wafer surface is flattened by chemical mechanical polishing. At the same time, the vertical plug and the horizontal connection have been deposited. Π • 1 The ta layer Γ g the dielectric im-rt perimeter c θ Zhou'_ Ε and C line migration and copper migration of the copper internal electrical channel canal anti-ditch anti-embedding is intercalated with a double-layer barrier. 1 degree t miserable , C, thick η layer, U, J, and C are mixed at a low level to make W to increase W and increase 1 and disperse 0 'to extend the life of a child P life 0 copper of the original D 6 due to V load 6, Number of L-medium P less 6 layers CD medium D electric C body conduction semi-low current reduction inlaying double copper The pieces need to be mediated by the sound layer. , Corresponding to copper effect, migration, etc. Please refer to Figure 1. This is the cross section of a conventional copper dual damascene trench. The double damascene trench pattern is formed in a multilayer formed on a substrate that already includes a dielectric layer 2 and a metal wire 8 therein, and includes two layers composed of carbonized carbide or nitride. # 刻 止 层 1 8 and 20, a masking layer 22 composed of oxynitride, and two dielectric layers 4 and 6 sandwiched therebetween. Next, a barrier layer 11 is formed in the dual damascene trench pattern, and then

Page 5 495918 V. Description of the invention (3) The copper 16 fills the double damascene trench pattern, and finally the chemical mechanical polishing process is used to flatten the wafer surface. When physical vapor deposition is used, when a conventional dual damascene barrier material is used to form a barrier layer 1 1 on the dielectric layer of the trench sidewall, which is sufficient to prevent the electrical migration of copper, the surface of the copper wire under the dielectric hole is simultaneously A barrier layer of the same thickness is formed. However, as mentioned earlier, the RC value between the conductor lines is an important factor for the speed of the device. Therefore, if a significant barrier layer exists between the upper and lower metal wires, the resistance value will be increased, and the RC time delay will be increased, which will affect the speed of the component. which performed. Therefore, how to prevent the electrical migration of copper without sacrificing the speed performance of the components has become one of the important topics of copper dual damascene process technology. In addition, the traditional dual damascene process method generally uses a physical vapor deposition method to form a trench barrier layer, and the resulting barrier layer is thicker than that obtained by a chemical vapor deposition method, which affects the development of denser and smaller components. Summary of the invention: The main object of the present invention is to provide a process method for forming a barrier layer on the surface of a lead trench and a side surface of a dielectric hole in a copper dual damascene process, so as to effectively isolate the dielectric layer and the copper wire to prevent Electrical migration effect of copper. Another object of the present invention is to apply the same process method to eliminate the barrier material to form a significant barrier layer on the surface of the copper wire at the bottom of the via hole, that is,

495918 V. Description of the invention (4) Reduce the resistance value between the upper and lower wires to avoid excessively high R C time delay to improve the speed performance of the component. Because of its good thin film characteristics, titanium nitride (TiN) is often used as a barrier layer material to improve the metal adhesion ability and prevent the metal and the dielectric layer or silicon from diffusing with each other. Titanium nitride is used as the material of the barrier layer between the copper and the dielectric layer of the copper double-mounting process, because titanium nitride has the same deposition rate for the two materials of copper and the dielectric layer. A barrier layer of the same thickness is formed thereon, please refer to the barrier layer 11 of the cross-section of the copper dual damascene trench structure shown in FIG. However, when Titanium Nitride (T i N) is added to the doped stone (S i) to form silicon-containing titanium nitride [T i N (S i)], this material is suitable for copper and dielectric layers. The two different materials have unequal deposition rates, that is, selective deposition rates for copper and dielectric layers. Applying the characteristic that the deposition rate of silicon-containing titanium nitride [T i N (S i)] on copper is slower than that on the dielectric layer, the present invention uses silicon-containing titanium nitride as the copper and dielectric of the copper dual damascene process. Barrier material between electrical layers. The deposition time of the barrier layer is appropriately controlled, and the titanium-containing silicon nitride forms a certain deposition thickness on the conductive trenches of the double damascene trench and the dielectric layer on the side of the dielectric hole, which can effectively isolate the copper conductor and its surroundings. A dielectric layer to prevent the electrical migration of copper. However, at the same time, silicon-containing titanium nitride has not yet formed a significant deposit on the copper wires at the bottom of the via, thereby reducing the copper double-mounting.

495918 V. Description of the invention (5) The resistivity between the upper and lower wires is improved, and the speed of the component is improved. Line — the detailed guideline of the process is “b barrier layer fiber gold M resistance barrier to the inlay resistance line up to ^ enough double-slot guide to the JS foot system of the ridge, with the embedding said Inch gold thin Η is still inlaying and changing ^ but take the double pairing, >, the method is to be a thin product, should be, / / is Shen Wei, that is, α is a perfect match, the layer "quote, ia, Obstacles to the law of law hinder the accumulation of the accumulation of the accumulation of Shen Yi Shen and follow. The qi of the companion of the phase of the phase of the phase of the consciousness of this matter. The cost-effective concentration layer is used to reduce the barrier cost. Compared with the traditional copper dual-mosaic barrier layer, the copper dual-mosaic layer with selective growth of silicon nitride nitride barrier layer is applied. The resistance value between the wires is lower than that of the conventional non-selectively grown titanium nitride barrier layer and the traditional physical vapor deposition method in the via. On the other hand, the thickness of the silicon-containing titanium nitride barrier layer obtained by using the conventional physical vapor deposition method is about 50 to 150 angstroms, and the thickness of the silicon nitride-containing titanium nitride barrier layer obtained by the chemical vapor deposition method is The reduction is about 5 to 25 Angstroms. Therefore, the application of chemical vapor deposition to form silicon-containing titanium nitride as a copper dual damascene barrier layer can simultaneously achieve the three goals of preventing the electrical migration of copper, improving the speed performance of components, and reducing and denser metal connections. Detailed description of the invention: The copper dual damascene process method for selectively depositing a barrier layer according to the present invention will be described in detail with reference to the drawings.

495918 V. Description of the invention (6) Please refer to Figure 2. Before the copper dual damascene etching process, the wafer must have completed the dual damascene multilayer structure deposition process, including the following steps: First, a dielectric layer has been formed. 2 and the substrate with at least one metal wire 8 formed on the substrate to form a 14-point stop layer 18 composed of carbide or nitride, and then a dielectric layer 4 is formed on the etch stop layer 18, and then After the second etch stop layer 20 composed of silicon carbide or silicon nitride is formed on the dielectric layer 4, the second dielectric layer 6 is formed on the second etch stop layer 20, and the last layer is made of nitrogen. A mask layer 22 composed of silicon oxide is formed on the second dielectric layer 20. Next, the copper dual damascene process procedure is implemented. Please refer to FIG. 2 to apply the dry-etching technology, which has two dielectric layers 4 and 6, two # -etch stop layers 1 8 and 20, and a mask layer 2 A double mosaic pattern including a wire trench pattern 9 and a via structure 10 is formed in the multilayer of 2. Then, use 2 5 (TC to 400 ° C clean reaction hydrogen or hydrogen and argon ion mixture to bombardment the wire trench pattern 9 and the interlayer hole structure 10 double mosaic pattern to bombard the sidewall of the pattern And the impurities on the metal surface are cleaned up, this procedure is shown in Figure 3. Then referring to Figure 4, the chemical vapor deposition method is applied to the double-damascene pattern of the wire trench 9 and the interlayer hole structure 10 and the mask layer 2 On the surface of 2, a barrier layer 1 composed of silicon-containing titanium nitride formed by adding titanium nitride (T 1 N) to doped silicon (S 1) is formed. Because silicon-containing titanium nitride [T i N (S i)] Yes

495918 V. Description of the invention (7) The metallic copper 8 and the dielectric layers 6 and 4 have the characteristics of selective deposition rate. The deposition on the surface of the copper 8 at the bottom of the dielectric hole is higher than that on the dielectric layers 6 and 4. The deposition on the sidewalls is slow. Therefore, the deposition time is properly controlled, and a sufficient silicon-containing titanium nitride is formed on the surface of the side wall of the dielectric trench of the dual damascene trench 9 and the dielectric hole 10 (the deposition degree is about 10 angstroms to 80 angstroms). ), Can effectively isolate copper electroplating 8, 16 and the surrounding dielectric layers 2, 4, 6 to prevent the electrical migration of copper. This is a silicon-containing titanium nitride barrier layer obtained by chemical vapor deposition. The thickness is about 5 Angstroms to 25 Angstroms. However, at the same time, the silicon-containing titanium nitride has not yet formed a significant deposit on the surface of the copper wire 8 at the bottom of the via 10, so the resistivity between the upper and lower wires is effectively reduced compared with the traditional copper dual damascene process, thereby improving Component speed performance. Then, as shown in FIG. 5, using one of the process methods of electroless copper plating, physical vapor deposition, chemical vapor deposition, or immersion in the activation solution method, the aforementioned silicon-silicon-titanium-containing barrier layer 1 2 On the surface, a copper seed layer 14 is formed on the surface of the copper wire 8 including the bottom of the via hole structure 10. As shown in FIG. 6, a double-surface-embedded electric ore copper wire 16 is formed on the surface of the aforementioned copper seed layer 14 by electroplating copper method, and the wire trench 9 and the interlayer hole 10 are filled back. Finally, a chemical mechanical polishing process is performed, using the aforementioned silicon oxynitride mask layer 22 as a polishing termination layer, and polishing the aforementioned copper inlay 16 to flatten the surface of the wafer to complete the vertical and horizontal conductor connection at the same time. After the line, please refer to Figure 7. The foregoing is a detailed description of the present invention using a preferred embodiment, rather than

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495918 Brief description of the drawings Figure 1 is a cross section of a semiconductor wafer to illustrate the copper dual damascene structure with a traditional barrier layer on which the present invention is based. Figure 2 is a cross section of a semiconductor wafer to Illustrates the double-inserted wire trench and via structure according to the present invention. FIG. 2 is a cross-section of a semiconductor wafer to illustrate the bombardment of the double-inserted wire trench and via structure based on the present invention. Procedure 0. Figure 4 is a cross-section of a semiconductor wafer to illustrate the structure of the dual damascene conductor trenches and vias after the deposition of a silicon-containing titanium nitride barrier layer according to the present invention. 0 Figure 5 is a semiconductor crystal. The circular cross-section shows the double-damascene wire trench and via hole structure after the copper seed layer is deposited according to the present invention. Figure 6 is a cross-section of a semiconductor wafer to illustrate this. Double damascene wire trench and via structure after backfilling electroplated copper based on the invention. Figure 7 is a cross-section of a semiconductor wafer to illustrate the copper double damascene structure after chemical mechanical polishing according to the present invention. Description of number: 2 substrate 4 first-dielectric layer 6 second dielectric layer 8 metal wire copper 9 wire trench pattern 1 丨 0 via hole 1 1 trench-receiving barrier layer 1: 2 silicon nitride barrier layer 14 copper ”seed layer 1 6 electroplated copper 1 8 first 1 etch stop layer 20 j second etch stop layer 2 2 mask layer

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Claims (1)

495918 VI. The scope of application for patents includes the mosaic of double-layered barriers that are based on the method of French equations: copper seeding steps in a row and 1 bottom board foundation = mouth structure; more in the layer The linear guide copper belongs to the gold level one, the few plates to the base, and a layer of power supply. The forming interlayer layer one or two, the interlayer stop layer final engraved mask # and the two layers, including the final package engraved one etched into three layers This board is separated from the base clip, and the layered plan is embedded with the structure of the double layer and the plan slot. The line guide structure contains a multi-layered layer ^ a surface. The case diagram of the dielectric layer on the side of the surface wall is embedded with a double •. The anterior structure is described by the formation of the barrier layer. The upper layer of the hole includes the copper wire, and the face surface on the surface. The bottom hole barrier layer resists the barrier layer. The barrier layer is seeded into a copper shape, but it is not formed. The front surface is fully filled and the top surface c-nul seed crystal copper is described above. A copper trench line leads The shape of the insert portion of the double bottom and with the drive system to the mechanical rubbing of the learning machine to said front surface of the copper sheet quality materials. The description of Shihua Tanping Fafang's description of the base of the board is preceded by: the layer encloses the end of the package, and the scale abruptly etches the step of the step. Please make a statement of the structure of the structure. The formation of the first formation of the above; the last layer of the last layer of the engraving layer 14 to stop the end of the second layer of the dielectric layer # " a different before the layer is terminated at the final layer of electrical Dielectric layer Page 13 495918 6. Scope of patent application Form a mask layer on top of the aforementioned second dielectric layer. 3. The method according to item 2 of the scope of the patent application, wherein the first #etch stop layer is composed of carbonized or nitrided. 4. The method according to item 2 of the scope of patent application, wherein the second layer is a termination layer consisting of carbonized or nitrided. 5. The method according to item 2 of the scope of patent application, wherein the mask layer is composed of oxynitride. 6. The method according to item 1 of the scope of patent application, wherein before forming the barrier layer, further comprising applying an ion bombardment process on the aforementioned dual damascene trench pattern. 7. The method according to item 6 of the scope of patent application, wherein in the bombardment procedure, the bombardment particles used are clean reaction hydrogen or a mixture of hydrogen and argon ions at 250 ° C to 400 ° C. 8. The method according to item 1 of the patent application scope, wherein said barrier layer is composed of silicon-containing titanium nitride. 9. The method according to item 7 of the scope of patent application, wherein said silicon-containing titanium nitride is formed by adding titanium nitride doped with silicon. Page 14 495918 6. Application scope of patent 10. The method according to item 1 of the scope of patent application, wherein the thickness of the barrier layer formed on the side wall of the dielectric layer of the dual damascene pattern is about 10 Angstroms to 8 0 Angstroms. 1 1. The method according to item 1 of the scope of patent application, wherein the thickness of the barrier layer on the metal wire copper in the via of the interlayer is about 5 to 25 angstroms. 12. The method according to item 1 of the scope of patent application, wherein the chemical mechanical polishing process uses the aforementioned mask layer as a polishing stop layer. 1 3. The method according to item 1 of the scope of patent application, wherein said copper material comprises electroplated copper. Page 15