TW495844B - Method for preventing overlay shift from occurring to device deposited with epitaxial silicon - Google Patents

Abstract

A method to precisely aligning plural photo-lithographic patterns on a wafer during photolithography process is disclosed. A first alignment mark is defined on the surface of a wafer. The wafer is then subject to a first photolithography process with reference to the first alignment mark to define a first photo-lithographic pattern. Next, epitaxial silicon layer is deposited on the surface of the wafer. The first alignment mark is replicated upward and transferred to the surface of the epitaxial silicon layer as a second alignment mark. Subsequent photolithography processes are continued with reference to the second alignment mark. Specifically before conducting each photolithography process, the material layer on top of the second alignment mark is removed to expose directly the second alignment mark.

Description

495844 V. Description of the invention (1) Field of the invention: The present invention relates to an alignment procedure in the semiconductor industry, in particular, a related process applied to epitaxial silicon deposition elements to prevent 1 overlapping film layer. An over lay shift occurs with the associated lithography process. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra-large integrated circuits (ULSI), in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. Due to the continuous shrinking of components, the related semiconductor process often encounters unprecedented difficulties, and the process complexity continues to increase. Furthermore, as the functional requirements of the overall circuit become more complicated, it is often necessary to overlay countless film layers on the semiconductor wafer, and the pattern of each film layer is defined by complex lithography etching steps'. In the meantime, in order for the successively laminated film layers' to accurately wedge with the previous film layer pattern, the related alignment technology becomes a very important key. σ month tea, ¾ brother one picture 'This picture is not as good as the typical alignment mark 10 made on the wafer surface. From the angle of looking down on the wafer surface, ^ look at these alignment marks. 10 is often composed of several square patterns, and each square pattern includes a plurality of neatly arranged and straight dense lines.

Page 4 495844 V. Description of the invention (2) Grain. Please refer to the second figure again. When viewed from the cross section of the wafer 15, Be 1J can see that the square pattern in the alignment mark 10 above is actually caused by a plurality of shallow trench structures. Therefore, at the beginning of the relevant process, the machine will easily lock these alignment marks 1 (^ and adjust the relevant angle and position of the wafer 15 by optical detection. Then, Then the required film layers are sequentially deposited or the relevant lithography process is performed, so that the required film layer or pattern can be accurately defined. Generally speaking, for a process that requires a stupid crystal process, it can be First, epitaxial silicon deposition is performed on the wafer, and then the corresponding lithographic etching process is used to define the alignment mark, and then a series of process steps can be performed. As for some more special circuits, such as image sensing circuits, linear Mixed-signal circuits and so on, because it will perform a lithography before the silicon epitaxial process. The process of defining the potential energy well in the wafer, so you need to define the required alignment mark before the epitaxial process. Then use this alignment mark to perform the ion implantation operation. However, it is worth noting that during the Shi Xi stupid procedure, the grains will be stacked along the lattice direction, so the alignment mark will have a considerable range. See Figure 3, which shows that for wafers with a lattice direction of <1 0 0>, the deposited silicon grains will overlap along an oblique direction, causing the entire The crystalline silicon layer 16 grows in an oblique direction, causing the entire alignment mark to shift. As a result, subsequent deposition layers or processes will cause serious alignment deviations from the previous lithographic pattern. In addition, as the deposited spermite film layer 16 will tilt along the lattice direction

495844 V. Description of the invention (3) Slanting means that in addition to the offset of the alignment mark, the original shallow trench shape will also be deformed and tilted as shown in the third figure. Therefore, for the subsequently deposited film layer 18, it will be susceptible to extremely uneven structural reactions, forces, and severe distortion and deformation. In this way, in addition to making the offset deviation larger, it will also cause difficulties in alignment. Refer to Figure 4 'This figure does not show the shift of the defined pattern when performing multiple lithography procedures on the wafer. Among them, the first lithographic pattern 20 is directly defined using the alignment mark on the surface of the wafer 15, so it does not cause an offset compared to the wafer 15 itself. As for the second lithographic pattern 22 after the epitaxial silicon layer has been deposited, the second-order lithographic pattern 22 is affected by the above-mentioned shift in the lattice direction, and a considerable degree of misalignment occurs. As for the third lithographic pattern 2 4 that is subsequently defined, in addition to being affected by the offset, it will also be affected by the distortion of the film layer, resulting in a more serious alignment error of the board to the surface of the wafer 1 5 . In addition, the fourth lithographic pattern 26, the fifth lithographic pattern 28, etc., which will be defined later, will be shifted toward the oblique direction. In this way, the offset error between the first lithographic pattern 22 and the fourth lithographic pattern 26 or the fifth lithographic pattern 2 8 defined later may exceed the allowable process window. To the extent that the produced ❿ circuit or chip cannot operate normally. In order to overcome the above-mentioned problems, in the current semiconductor process, when defining the relevant lithographic pattern, the operator will offset the lithographic pattern in the opposite direction based on empirical data and related process parameters to make corrections. The defined lithographic pattern does not shift too much.

495844 V. Description of the invention (4) And 'It is worth noting that the current chip is used to replace the health'. The same: a production line may take into account several products at the same time, so the second:; 1: ί f Changes and revisions. In this case, measure and observe ’to determine the actual offset error for different process steps and conditions 22 = 3. For example, the meaning of the pattern can reduce Xibu, and the production and reliability are reduced due to the manufacturing process: enough to increase the cost of the process: τ, the yield of the related integrated circuit

The purpose and summary of the invention: The main purpose of this invention is to provide a method that can accurately align a plurality of lithographic patterns, so that the stone books can be sequentially defined on the circle, and the other purpose of the Ming is to provide a The method of shifting the alignment marks caused by the silicon layer of the day and day is reduced when the lithography process is reduced. The present invention provides an accurate pairing of lithography patterns: zhi = circle, when the lithography process is performed, multiple alignment marks And make batches. First, define the number / path length L on the surface of the wafer and define the number next to the circle ~ the primary silicon layer. Among them, the two = 妾, from the top surface of the wafer to the surface of the epitaxial silicon layer, and form the "" :: number will be copied upwards and passed to the _ brother pair of bit marks. Then proceed to page 7

Two lithographic procedures to place on the wafer The second lithographic procedure uses the second alignment: lithographic pattern. Wherein, before performing the second lithography process, a c-alignment process is further included, and the material layer is 'in order to directly expose the material on the second alignment j = two-alignment mark. Detailed description of the invention: as before' The situation is defined beforehand. The spar evening layer will be subsequently superimposed. That is to say, the alignment error in the pattern 2 2 is shifted due to the effect of its alignment action. In the fourth figure, the alignment mark is used for the wafer 15 and the second film is placed on the wafer 15 as shown in the third figure. As for, it may be that the related system will make the first number one, and the third alignment shift and twist 24, which defines a large deviation due to the heavy deviation of the direction of the shadowing process grid, are shown. For the required situation, When the surface alignment is completed for the first micro-show, along with the crystal layer 18, when a strict lithography process is generated, a considerable distance will be generated for the subsequent redefinition of the film layer 18, which is three times offset. Lithographic pattern line Silicon epitaxial program Sub-lithographic pattern 2 〇 There will be no deviation, the deposition is to produce offset, and create, distort, and change the second micro-view shift ' Yan J times lithography pattern 2 4 iff number, to carry out the |

In order to prevent the above-mentioned problems from occurring, a related method is proposed in the present invention to accurately determine the alignment marks and prevent the alignment marks from being affected by the above-mentioned warping, offset, and the like. First, as shown in Figure 5,

Page 8 495844 V. Description of the invention (6) &lt; 1 0 0 &gt; Crystal orientation single crystal silicon wafer 50. Generally speaking, other types of semiconductor materials, such as galHum arsenide, germanium, or silicon on insiU a tor (SOI), can be used. In addition, although the characteristics of the surface of the semiconductor substrate for the present invention will cause subsequent epitaxial shifts in different directions or degrees of privacy, due to the method of the present invention, the related problems will be effectively overcome. The crystal orientation can also select &lt; 丨 丨 〇 &gt; or &lt; 丨 丨 丨 &gt;.

The receiver is like performing the related micro-alignment mark engraving process, but the alignment mark is used to detect whether this is consistent with the angle and utilize the anisotropy. Reactive i on This step uses 3 / Cl2, HBr / CL Defines the lithography I worm as the position of the operator. Steps are, BC1

The aforementioned 'because the shadowing step' is performed on the semiconductor wafer 50 before the subsequent epitaxial process is performed. Among them, a plurality of shallow trench openings 5 2 can be defined on the surface of the semiconductor wafer 50. In this way, in the subsequent processes, the position of the shallow trench opening 52 and the length of the wafer 50a are judged in a preferred embodiment. This is an anisotropic reaction etch process. RIE) to etch the above film layer: The etchant for etching the silicon substrate can be selected from SiCl4 / Cl2 / 02, HBr / 〇2, Br2 / SFe or. Subsequently, the first lithography step can be performed by the aforementioned shallow circle 50. The lithography step defined in a lithography step to the wafer 50 does not cause the ′ channel 5 2 to be used as the alignment mark, but the crystal. Refer to Figure 26, which shows the first lithographic pattern 70, which will accurately offset too much. Then, as in the seventh figure

V. Description of the invention (7) -------------- As shown, Shi Xishi s can be carried out at this time, due to the deposition of Erhuiyuan 50 on the formation of Wormstone Xi layer 54. As a result, the epitaxial silicon layer 54 is stacked one by one in the lattice directions, and the grooves passing upwards on the surface of the circle 50 ′ are shifted and tilted by 3. For this reason, in addition to &gt; shifting to the side, the crystal will have a shape of Θ, as shown in the seventh figure, in the second position on the epitaxial silicon layer 54, the state of tilt. In other words, a shift in position. It ’s said that it will cause a considerable amount of corrosion to the side. Therefore, for the subsequent deposition of the film layer 5β, the stress will be generated under the cloth condition. Significant shifts in double-to-very uneven pairwise marks. ^ Curving and deformation in the seventh figure, and the film formation layer 56 is subjected to an etching process, and the above problem can be effectively solved, and the layer 56 can be processed. In other words, the epitaxial silicon layer 54 and its trench number can be removed by removing a part of the film layer 56 on the part of the film opening above the alignment mark and exposing it in two steps. In this way, for the subsequent second, the process of registering the epitaxial silicon layer 5 4 on the surface of the epitaxial silicon layer 54 and the registration process on the surface of the silicon layer 54 is because the film layer 5 is directly used and the shift is more serious. 6 ^ 'instead of using the more distorted shape of the pattern for the epitaxial stone layer 5 or 4 2 as a basis for alignment, so its definition of 9 $' will not cause excessive shift.

Tongue Tea Day Calling Pen with the same »Subcomma @ 图, the 1 ^ θ wood defined after the epitaxial silicon layer 54 is deposited, as described above, subject to the counterpoint I on the epitaxial silicon layer 54 There will be a deviation from the alignment mark of the wafer 50. The Xixi layer, "the second lithographic pattern 72 will not produce", can be epitaxial silicon layer 5 by the above-mentioned lithographic etching process.

Page 10

The film layer on the parallax is removed, and the channel table a μ ^ of the epitaxial silicon layer 54 is directly used as the alignment basis for the next lithography step. In this way, for the third lithographic pattern defined by the third ^ micro ~ private sequence, because it is the same as the second micro two figure j case, it is the same: the alignment mark on the surface of the stupid stone layer W In the next step, the second lithographic pattern will not cause an offset compared to the second lithographic pattern.

It is clear that, in the first embodiment of the present invention, regardless of the number of the film layers on the surface of the sunken crystalline silicon layer 54, the hanri sun stone layer will be made by an etching process. 5 The alignment marks on the surface are exposed, and then the next lithography private sequence is performed. That is, 'in any step of the entire process, as long as it is necessary to use alignment &quot; for lithography, the material layer on the epitaxial silicon layer 5 4 alignment mark surface needs to be removed and directly The epitaxial silicon layer 54 is exposed. In this way, since the lithography process performed each time uses the alignment mark on the surface of the stupid silicon layer 5 4 as a basis, the lithographic patterns defined one after another, such as the third lithographic pattern 7 4 and the fourth The lithographic pattern 7 6, the fifth lithographic pattern 7 8,... Will not cause excessive offset compared to the epitaxial silicon layer 5 4. ° As for the second embodiment of the present invention, the film layer above the epitaxial silicon layer 5 4 alignment mark can be selectively removed. The film layers deposited on the epitaxial silicon layer 54 in this order include a light-transmitting film layer and an opaque film layer. Therefore, when the deposited material layer is a light-transmitting film layer, the subsequent lithography process can still be performed by the alignment mark on the surface of the stupid stone layer 54.

Page 11 495844 V. Description of the invention (9) Required alignment action. That is, when the relevant lithography process is to be performed, an optical device that performs crystal circle alignment can detect the alignment mark on the surface of the epitaxial silicon layer 5 4 through the light-transmitting film layer. Therefore, although these light-transmitting film layers are not removed, alignment can be performed by using the epitaxial silicon layer 54 so that the lithographic pattern does not cause deviation 1. Conversely, when the deposited film layer is an opaque film layer, before the subsequent lithography process is to be performed, it is necessary to move a part of the opaque film layer above the registration mark by an etching process. Except that the alignment mark of the underlying epitaxial silicon layer 54 is exposed. To be oblique, so that the counterpoint registration will produce a shadow program surface definition, that is, later, and then again, the lithography chart specifically explains that the registration mark generates the side number definition of the first micronumber definition of the second Micro. Relative offset. Yes, the operator can perform the first lithography process when the first lithography pattern may be generated according to the bit mark. According to the stupidity, it is possible to make the case 72, because the stupid stone shifts in the evening direction. Shadow pattern 7 0, shadow pattern 7 2. So, the offset distance of stupid crystals to be deposited on the stupid crystals can be based on the sequence time, which can be generated after the crystals. The precise layer 54 of the lithographic pattern 74 will follow along with the thickness and direction of the silicon entered in accordance with the third lithography process of the stupid crystal. For example, experience values are used. Use wafer 50 to perform pattern alignment. Lattice square Wafer 50 Shi Xi layer 5 4 Case 74 and so on to calculate this, perform corrections to adjust the adjustment of the subsequent tilting surface, etc., a little out of its author. Also whole. Secondly, although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Familiar with this

Page 495 844

Page 495844 Brief description of the drawings The above description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, of which: The first figure is a top view of a semiconductor wafer, showing the current technology The alignment marks defined on the wafer surface; the second image is a cross-sectional view of a semiconductor wafer, showing that the alignment marks on the wafer are formed by a plurality of trench openings; the third image is a cross-sectional view of a semiconductor wafer, showing After the epitaxial silicon and the material layer are deposited, the offset and distortion caused by the alignment mark; The fourth figure is the lithographic pattern position offset map, which shows the offset of the alignment mark caused by the deposition of stupid stones. The position of the lithographic pattern is incorrect; the fifth image is a wearing view of a semiconductor wafer, showing a plurality of dense shallow trench openings made on the wafer according to the present invention to define alignment marks; the sixth image is a lithographic pattern Position shift diagram, showing that after using the method of the present invention, the shift of the lithographic pattern can be effectively reduced; the seventh figure is a cross-sectional view of a semiconductor wafer, which shows no stupid stones Offset and distortion caused by alignment marks after contacting with the material layer; and FIG. 8 is a cross-sectional view of a semiconductor wafer, showing the removal of the material layer on the alignment mark according to the present invention to expose the surface of the epitaxial silicon layer Alignment mark. Drawing number comparison table: Counterpoint 5 Tiger 1 0 Wafer 1 5

Page 14 495844 Schematic illustration of the stupid crystal $ Xi layer for the first time the third micro-fifth. Lithographic shallow trench 1 channel opening stupid stone layer for the second time the fourth micro-lithography 1 6 film layer 1 8 Shadow pattern 20 Second lithographic pattern Shadow pattern 24 Fourth lithographic pattern 26 Pattern 28 Monocrystalline silicon wafer 50 α 52 First lithographic pattern 70 54 Film layer 56 Shadow pattern 72 Second lithographic pattern 74 Pattern 76 No. Five lithographic patterns 78 22

Claims (1)

495844 6. Scope of patent application 1. A method for accurately aligning a plurality of lithographic patterns during a lithographic process on a wafer. The method includes at least the following steps: defining a first alignment mark on the surface of the wafer; Use the first alignment mark to perform a first lithography process on the wafer, and define a first lithography pattern; deposit a stupid stone layer on the surface of the wafer, where the first alignment mark Will be copied upward and transferred to the surface of the epitaxial silicon layer to form a second alignment mark; and a second lithography process is performed to define a second lithography pattern on the wafer, wherein the second lithography process is to use The second alignment mark is subjected to an alignment process, and before the second lithography process is performed, the material layer on the second alignment mark is removed, so as to directly expose the second alignment mark. 2 As for the method of the first scope of the patent application, which further includes the subsequent lithography procedures, all follow the steps of the second lithography procedure. Before performing the lithography procedure, first remove the second registration mark. Layer of material to expose the second alignment mark. 3. The method according to item 1 of the patent application range, wherein the removed material layer only includes an opaque layer. $ 4. The method according to item 1 of the scope of patent application, wherein when the first lithography process is performed on the wafer using the first alignment mark, the epitaxial silicon layer can be adjusted according to the thickness of the epitaxial silicon layer subsequently deposited. Position of the first lithographic pattern so that Page 16 495844 6. Scope of patent application The first lithographic pattern can accurately align the second lithographic pattern. 5. A method of finely aligning and aligning a plurality of lithographic patterns when performing a lithography process on a wafer, in which a first registration mark is first defined on the surface of the wafer) and then the first registration mark is used , A first lithography process is performed on the wafer, and a first lithography pattern is defined, and then an epitaxial silicon layer can be deposited on the upper surface of the wafer, wherein the first alignment mark is copied upward and transferred to the epitaxial A second alignment mark is formed on the surface of the crystalline silicon layer, and then the second alignment mark can be used for subsequent lithography procedures, which are characterized by: removing the second pair before performing each lithography procedure A layer of material on the bit mark so as to directly expose the second pair of bit marks. 6. The method of claim 5 in which the removed material layer only includes an opaque layer. 7. If the method of claim 5 is applied, when the first lithography process is performed on the wafer using the first alignment mark, the first epitaxial silicon layer can be adjusted according to the thickness of the epitaxial silicon layer subsequently deposited. The position of a lithographic pattern allows the first lithographic pattern to accurately align the second lithographic pattern. Φ 8. A method of accurately aligning a plurality of lithographic patterns when performing a lithographic process on a wafer, in which a first alignment mark is first defined on the wafer surface, and then the first alignment mark is used to The wafer is subjected to a first lithography process, and a first lithography pattern is defined, which can then be deposited on the upper surface of the wafer Page 17 495844 VI. Patent application epitaxial silicon layer, in which the first alignment mark will be copied upwards and transferred to the surface of the epitaxial silicon layer to form a second alignment mark, and then the second pair can be used again. After performing a lithography process, the following features are: &lt; Before each lithography process, remove the non-transparent material layer on the second alignment mark to directly expose the second Registration mark. Φ Page 18