TW492177B - Electrostatic discharge protection device for silicon controlled rectifier with adjustable trigger potential - Google Patents

Electrostatic discharge protection device for silicon controlled rectifier with adjustable trigger potential Download PDF

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TW492177B
TW492177B TW90113739A TW90113739A TW492177B TW 492177 B TW492177 B TW 492177B TW 90113739 A TW90113739 A TW 90113739A TW 90113739 A TW90113739 A TW 90113739A TW 492177 B TW492177 B TW 492177B
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electrostatic discharge
silicon
controlled rectifier
discharge protection
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TW90113739A
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Chinese (zh)
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Suei-Hung Chen
Jian-Shing Li
Jiau-Ren Shr
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Taiwan Semiconductor Mfg
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Abstract

The electrostatic discharge protection device with silicon controlled rectifier according to the present invention comprises a P-well, a N-well formed in the P-well, a first p-type doping region formed in the N-well, a n-type doping region formed in the P-well, and a second p-type doping region formed in the P-well. The present invention is characterized in using the distance from the edge of the first p-type doping region in the N-well to the intersection of the N-well to adjust the trigger voltage of the SCR, and saving the area for producing the transistors.

Description

492177 五、發明說明α) 發明領域 本發明係有關於一種靜電放電保護元件,特別是一種 可調式電位矽控制整流器(Silicon Controlled Rectifier; SCR)靜電放電保護元件(Electrostatic Discharge;ESD)° 發明背景 次微米製程技術已廣泛地被運用來增進積體電路之性 能和運算速度以降低每顆晶片之成本。但次微米積體電路 & 產品在靜電放電之防護能力卻因元件尺寸之縮小而降低, 故次微米M0S積體電路因ESD而損傷的情形更加嚴重,對於 積體電路之技術及產業而言,靜電放電(Electr〇static Discharge ;以下簡稱為ESD)損壞是影響積體電路產品之 , 良率與可靠度之一項重要的因素。 對於以金氧半場效電晶體所形成的積體電路而言,外 界所輸入的訊號係連接至所述金氧半場效電晶體的閘極。 若外界所輸入訊號的電壓過大,則閘極介電層會崩潰 (Breakdown)而使元件損害。所述閘極介電層通常是一埶 氧化層,其抗電壓之強度約為i E 7至2 E 7伏特/公分。以 次微米製程而言,閘極介電層的厚度僅約為4〇A,亦僅 能抵抗4至8伏特的電壓,若外界所輸入訊號大於8伏僅 則間極介電層會崩潰。雖然目前積體電路通用的工作寻電壓 丄 / / 五、發明說明(2) 一般為3 . 3或2 · 5伏特,低於 件戋是記忾體,### 述的8伏特。不論是邏輯元 能高於2_伏特,甚至2 f::具極高電壓的靜電(可 路内部元件的損壞。因=::特):因而造成積體電492177 V. Description of the invention α) Field of the invention The present invention relates to an electrostatic discharge protection element, particularly an adjustable potential silicon controlled rectifier (SCR) electrostatic discharge protection element (ESD) ° Background of the invention Micron process technology has been widely used to improve the performance and operating speed of integrated circuits to reduce the cost of each chip. However, the protection ability of sub-micron integrated circuits & products in electrostatic discharge is reduced due to the reduction in component size. Therefore, the damage of sub-micron M0S integrated circuits due to ESD is more serious. For the technology and industry of integrated circuits Electrostatic discharge (ESD) damage is an important factor affecting the yield and reliability of integrated circuit products. For an integrated circuit formed of a metal-oxide-semiconductor field-effect transistor, the externally input signal is connected to the gate of the metal-oxide-semiconductor field-effect transistor. If the voltage of the external input signal is too large, the gate dielectric layer will break down and damage the device. The gate dielectric layer is usually an oxide layer, and its anti-voltage strength is about i E 7 to 2 E 7 volts / cm. In terms of the sub-micron process, the thickness of the gate dielectric layer is only about 40A, and it can only withstand voltages of 4 to 8 volts. If the external input signal is greater than 8 volts, the dielectric dielectric layer will collapse. Although the current working voltage of the integrated circuit is generally 丄 / / V. Description of the invention (2) is generally 3.3 or 2.5 volts, which is lower than the 8 volts described in ###. Whether the logic element can be higher than 2_ volts, or even 2 f :: static electricity with extremely high voltage (the internal components of the circuit can be damaged. Because = :: special): resulting in integrated electricity

十對積體電路母一接腳的接合墊 (Bonding Pad),在接人執^咖如-,L φ ^ ^ ^ 接ϋ墊和内邛疋件之間都必須有靜電 放電防4電路,以便在外來的高壓靜電放電進人内部元件 之前便將其接地。目前之課題是如何保護積體電路元件以 避免受到高壓靜電放電的影響,目前業界的規格是必須能 夠承受較大之ESD電壓,以確保產品的可靠度。 一相關於E S D之形成方法可參閱美國專利u s ρ ν 0.Ten pairs of integrated circuit female one-pin bonding pads (bonding pads) must be equipped with static discharge prevention circuits between the connection pads such as-, L φ ^ ^ ^ ^ In order to ground the external high-voltage electrostatic discharge before it enters the internal components. The current topic is how to protect integrated circuit components from being affected by high-voltage electrostatic discharge. At present, the industry standard must be able to withstand large ESD voltages to ensure product reliability. A method for forming E S D can be found in U.S. patent u s ρ ν 0.

United States Patent 6, 011,420,發明人為 Watt等,發 明名稱為 ’’ESD protection apparatus having floating r ESD bus and semi conductor structure”,其中揭露一種 _ 靜電放電保護電路。另一相關於ESD之形成方法可參閱美 國專利 USP No. United States Patent 5, 872, 379,發明 名稱為"Low voltage turn-on SCR for ESD protect ionn,發明人為本案發明人之一,其專利讓渡於 本案之申請人。另一種達到靜電放電保護之結構之一為使 ¥ 用石夕控制整流器(Silicon Controlled Rectifier; SCR) 之結構,用以將電荷導離,一般包含P型/ N型/ P型/ N型 的結構。一種稱做低臨界電壓矽控制整流器(L 〇 w - V ο 11 a g e Triggered Silicon Controlled Rectifier; LTVSCR)也 、United States Patent 6, 011, 420, the inventor is Watt, etc., the invention name is "ESD protection apparatus having floating r ESD bus and semi conductor structure", which discloses one kind of _ electrostatic discharge protection circuit. Another is related to the method of forming ESD See USP No. United States Patent 5, 872, 379, the invention name is " Low voltage turn-on SCR for ESD protect ionn, the inventor is one of the inventors of this case, and the patent is transferred to the applicant of this case. One of the other structures to achieve electrostatic discharge protection is the structure using a Silicon Controlled Rectifier (SCR) to conduct the charge away. Generally, it includes P-type / N-type / P-type / N-type structures A type is called low critical voltage silicon controlled rectifier (L 〇w-V ο 11 age Triggered Silicon Controlled Rectifier; LTVSCR),

第5頁 492177 五、發明說明(3) 已被發展,在開啟狀態利用低電阻來保護敏感之元件。1^ LVTSCR則包含一電晶體結構,其汲極與源極區域跨於N变 井形成於P型基板之間。 此外,美國專利 USP No. United States Patent 5,465,189。其中上述先前技術使用NMOS做為觸發源 (tr i gger source ),但是觸發電位依靠NM0S之崩潰電壓而 定。先前技術之SC_發電位對ESD保護而言太高,所以必 須加入NM0S用以降低SC觸發電路。而上述NM0S將佔用面 積。 發明目的及概述: 鑑於先前技術各有不同之缺點,因此本發明之目的為 &供種可调式觸發電位之靜電放電保護元件。 本發明之矽控制整流器(SiliC(Dn hntNiied m/m、)靜電放電保護元件包含:p型基板或p型 雜&域,带成^ \•於上述p型基板或p型井之中;第一p型摻 雜區域’形成於上述N型井中· _ P型基板或P型井之中;第二_ 摻雜區域,形成於上述 基板或P型井之中;及可以 ^區域,形成於上述搜 區域邊緣至上述d; 型井之第-P型摻雜 電壓,並節省製作電晶體之斤面構積成。之距離以調變·觸發 492177 五 發明說明(4) 發明詳細說明: 本發明揭露一種石夕控制整流器(Silic〇n c〇ntrollecl feet i f ieT ; SCR)靜電放電保護元件。本發明在產生“账 態=:可以具有較佳之靜電放電保護效果,且本發明不需 『:=加NMOStc件用以觸發電位,且可以降低發電 立 者,本發明可以利用一物理間距用以調整觸發電 位0 本發明揭露之靜雷放雷彳疋# - ^ / 社摄干夕认固保濩兀件(ESD Protect ion)的 、·、口構不之於圖一。其構造包含矽控Page 5 492177 V. Description of the invention (3) It has been developed to use low resistance in the on state to protect sensitive components. 1 ^ LVTSCR includes a transistor structure, the drain and source regions of which are formed between the P-type substrate across the N-well. In addition, USP No. United States Patent 5,465,189. The previous technology mentioned above uses NMOS as the trigger source (tr i gger source), but the trigger potential depends on the breakdown voltage of NMOS. The SC_generating bit of the prior art is too high for ESD protection, so NMOS must be added to reduce the SC trigger circuit. And the above NMOS will take up area. Object and Summary of the Invention: In view of the different disadvantages of the prior art, the object of the present invention is to provide an electrostatic discharge protection element with adjustable trigger potential. The silicon controlled rectifier (SiliC (Dn hntNiied m / m)) electrostatic discharge protection element of the present invention includes: a p-type substrate or a p-type impurity & domain, formed into a p-type substrate or a p-type well; The first p-type doped region is formed in the above-mentioned N-type well _ P-type substrate or P-type well; the second _-doped region is formed in the above-mentioned substrate or P-type well; and the region may be formed From the edge of the search area to the -P type doping voltage of the d; well, and save the surface area of the transistor. The distance is adjusted and triggered. 492177 Five invention descriptions (4) Detailed description of the invention: The present invention discloses an electrostatic discharge protection element of a Silicone Control Rectifier (Siliconctrotrolcl if ifT; SCR). The present invention generates a "account state =: can have a better electrostatic discharge protection effect, and the present invention does not require": = Add NMOStc parts to trigger the potential, and can reduce the generation of power generation, the present invention can use a physical distance to adjust the trigger potential 0 The static thunder release thunder exposed by the present invention #-^ / Sheshe Qianxi Warranty濩 件 (ESD Protect ion), ... The one in Fig. Configured comprising a silicon-controlled

Controlled Rectifier· (Slllcon 形成於p型基板或p型井之中,兑σ,二主要結構包含賭井 域,另外,Ρ型基板或ρ型井中/包人』:,含鸣摻雜區 其中。 ^ 3 Ν型及Ρ型摻雜區域成於 形成於ρ型基板或ρ型井中 基板中之Ρ型摻雜區域接地。里摻雜區域與形成於Ρ型 $金屬墊4。利用Ν型井之ρ型摻雜^型井之Ρ型摻雜區域耦Controlled Rectifier (Slllcon is formed in a p-type substrate or p-type well, and σ, the two main structures include the gambling well domain. In addition, a P-type substrate or a p-type well in / inclusive of ":, including the doped region. ^ 3 N-type and P-type doped regions are formed in the P-type doped region formed in the p-type substrate or in the substrate of the p-type well. The inner doped region is formed with the P-type $ metal pad 4. The N-type well is used. P-type doped region coupling for p-type doped ^ -type wells

界所構成之距離d可以調變邊考缘至Ν型井與?型 $作電晶體之面積。亦即觸發 SCR之處發電壓,以節省 雜區域之距離有關,所以可二卜墼值與Ν型井至其中ρ型摻 小。 先前技術之LVTSCR之面積The distance d formed by the boundary can be adjusted from the edge to the N-type well? Type $ is the area of the transistor. That is to say, the voltage at the SCR is triggered to save the distance of the miscellaneous area, so the value of the dioxin can be small with the N-type well to which the p-type is mixed. Area of LVTSCR of the prior art

492177 五、發明說明(5) 圖一及圖三為本發明之佈局俯視圖。其中包含一 P+護 環6,耦合於電位VSS,一 N型井8形成於上述護環6之内, 一般可以為矩形空間(圖三所示)或是兩端具有擴展部之矩 形空間(圖一所示)’上述擴展部包含N +接觸蟄(pad)l 0配 置於其上。P +接觸墊(pa(j) 1 2則配置於矩形空間之主體 部。N+佈植區域1 4則配置於上述之n型井兩側。上述之P + 護環6與N+佈植區域14均麵合至VSS(或接地)。上述p +接觸 墊(pad)l 2周邊至N型井邊緣之距離,用以決定觸發電路之 值。是故,本發明可以利用特定之物理參數決定靜電放電 保護電路之電性。 圖四所示為先前技術與本發明電性比較圖。方塊曲線 所代表的是先前具有NMOS之靜電放電保護電路之電性,在 以人體模型測試中,以2千伏之狀態下,其電流約為 9 6 0 m A ;而本發明以人體模型測試中,以5千伏之狀雜下, 其電流約為2 · 5 5 A ’示之於圓圈曲線,本發明之電性铁 優於先前技術。 ..... 綜上所述,本發明利用N型井之P型摻雜區域邊緣至賭 井與P型井之交界所構成之距離d可以調變SCR之處發電 壓,其不但可以用以調變觸發電位而且可以節省製作電曰 體之面積。而電性亦較先前技術為優良。 Βθ 本發明雖以一較佳實施例闡明如上,然其並非 ^ I pv.492177 V. Description of the invention (5) Figures 1 and 3 are top views of the layout of the present invention. It contains a P + guard ring 6, which is coupled to the potential VSS. An N-type well 8 is formed in the guard ring 6, which can generally be a rectangular space (shown in Figure 3) or a rectangular space with extensions at both ends (Figure (1)) The above-mentioned extension includes an N + contact pad (pad) 10 disposed thereon. P + contact pads (pa (j) 1 2 are arranged on the main body of the rectangular space. N + planting areas 1 4 are arranged on both sides of the above-mentioned n-type wells. The aforementioned P + guard rings 6 and N + planting areas 14 The surface is uniformly connected to VSS (or ground). The distance from the periphery of the p + contact pad 2 to the edge of the N-type well is used to determine the value of the trigger circuit. Therefore, the present invention can use specific physical parameters to determine static electricity. The electrical property of the discharge protection circuit. Figure 4 shows the electrical comparison between the prior art and the present invention. The square curve represents the electrical property of the previous electrostatic discharge protection circuit with NMOS. In the state of volts, its current is about 960 m A; and in the human body model test, the current is about 2.5 kV, and its current is about 2.55 A. The electrical iron of the invention is superior to the prior art .... In summary, the present invention utilizes the distance d formed by the edge of the P-type doped region of the N-type well to the boundary between the gambling well and the P-type well can be adjusted. The SCR generates a voltage, which can not only be used to adjust the trigger potential, but also save the area of the electric body. The electrical properties are also better than the prior art. Βθ Although the present invention is explained above with a preferred embodiment, it is not ^ I pv.

第8頁 492177 五、發明說明(6) 定本發明精神與發明實體僅止於此一實施例爾,如形成摻 雜區域之型態可以相互轉調,而熟悉此領域技藝者,在不 脫離本發明之精神範圍内,當可作些許更動潤飾,其專利 保護範圍更當視後附之申請專利範圍及其等同領域而定。 例如上述之導電型雜質N型和P型相互互換,本發明也同樣 適用。Page 8 492177 V. Description of the invention (6) It is determined that the spirit and the invention entity of the present invention are limited to this embodiment. For example, the forms of doped regions can be transposed, and those skilled in the art will not depart from the present invention. Within the scope of the spirit, it can be modified slightly, and the scope of its patent protection depends on the scope of the attached patent application and its equivalent. For example, the above-mentioned conductive type impurities, N-type and P-type are interchangeable with each other, and the present invention is also applicable.

第9頁 492177 圖式簡單說明 圖一所示為本發明靜電放電保護元件之截面圖。 圖二所示為本發明靜電放電保護元件之俯視佈局圖。 圖三所示為本發明靜電放電保護元件之俯視佈局圖。 圖四所示為先前技術與本發明電性比較圖。 符號對照: 基板 2 金屬塾 4 護環 6 N型井 8 N+接觸墊(pad) 10 P+接觸墊(pad) 12 N+佈植區域 14Page 9 492177 Brief description of the drawings Figure 1 shows a sectional view of the electrostatic discharge protection element of the present invention. FIG. 2 is a plan layout view of the electrostatic discharge protection element of the present invention. FIG. 3 is a plan layout view of the electrostatic discharge protection element of the present invention. FIG. 4 shows a comparison of electrical properties between the prior art and the present invention. Symbol comparison: base plate 2 metal cymbals 4 guard ring 6 N-type well 8 N + contact pad (pad) 10 P + contact pad (pad) 12 N + planting area 14

第10頁Page 10

Claims (1)

六、申請專利範圍 1·一種矽控制整泣w SCR)靜電放雪 々,L 益(Silicon Controlled Rectifier; p型其4保護元件包含: a基板或P型丼. N型井,,土汴, 第—㈣Z成於上述p型基板或p型井之中; N型摻雜W區域/形成於上述N型井中; 第二P型摻域/形成於上述p型基板或p型井之中; 中;及 ’雜區域’形成於上述P型基板或p型井之 可以利用卜'、 型井交界所槿杰述N型井之第一 ?型摻雜區域邊緣至上述N 作電.晶體之面積之距離以調變SCR之觸發電壓,並節省製 2 ·如申睛專利範圚 件,其中上述之當 、之矽控制整流器靜電放電保護元 上达之第一 P型摻雜區域連接至—金屬墊。 如:: : nf 1項之矽控制整流器靜電放電保護元 中上逑之第二P型摻雜區域麵合至接地。 保護元 ❿ 4·如申請專利範圍第1項之泣 件,直中卜、+、々心丨边 控制正,瓜益靜電放電 ,、上述之’摻雜區域耦合至接地。 5.一種矽控制整流器靜電放電保護元 p+護環; 3 . N型井,形成於上述護環之内;Sixth, the scope of patent application 1. A silicon controlled w SCR) electrostatic discharge snow ridge, L type (Silicon Controlled Rectifier; p type and its 4 protection elements include: a base plate or P type 丼. N type well ,, soil 汴, The first ㈣Z is formed in the p-type substrate or p-type well; the N-type doped W region / formed in the N-type well; the second P-type doped domain / formed in the p-type substrate or p-type well; And 'hetero-regions' formed on the above-mentioned P-type substrate or p-type well can be used as the first type-doped region edge of the N-type well at the junction of the type-well junction to the above-mentioned N for electricity. The distance of the area is used to adjust the trigger voltage of the SCR and save the system. 2) Such as the patented patent document, where the first P-type doped region on the silicon controlled rectifier electrostatic discharge protection element is connected to— Metal pads, such as:: nf 1 The silicon-controlled rectifier electrostatic discharge protection element of the second P-type doped region in the upper surface of the silicon element is grounded to the ground. Protection element 4 · If the first item of the scope of the patent application, Straight in the middle, +, and the heart 丨 while controlling positive, Gua Yi static discharge, the above 'doping The area is coupled to the ground. 5. A silicon-controlled rectifier electrostatic discharge protection element p + guard ring; 3. N-type well formed inside the guard ring; 492177 六、申請專利範圍 P+接觸墊,配置於上述N型井之主體上; N+佈植區域,配置於上述N型井兩側;及 上述P+接觸墊周邊至上述N型井邊緣之距離,用以決定 觸發電路值。 6. 如申請專利範圍第5項之矽控制整流器靜電放電保護元 件,其中上述N型井更包含擴展部,上述擴展部包含N+接 觸墊配置於其上。 7. 如申請專利範圍第5項之矽控制整流器靜電放電保護元 件,其中上述上述P+護環接地。 8. 如申請專利範圍第5項之矽控制整流器靜電放電保護元 件,其中上述上述N +佈植區域接地。 9. 一種石夕控制整流器(Silicon Controlled Rectifier; SCR)靜電放電保護元件包含: N型基板或N型井; P型井,形成於上述N型基板或N型井之中; 第一 N型摻雜區域,形成於上述P型井中; P型摻雜區域,形成於上述N型基板或N型井之中; 第二N型摻雜區域,形成於上述N型基板或N型井之 中;及 可以利用上述P型井之第一 N型摻雜區域邊緣至上述P492177 VI. Patent application scope P + contact pads are arranged on the main body of the N-type well; N + planting area is arranged on both sides of the N-type well; and the distance from the periphery of the P + contact pad to the edge of the N-type well, use To determine the trigger circuit value. 6. For example, the silicon-controlled rectifier electrostatic discharge protection element of the scope of patent application No. 5, wherein the N-type well further includes an extension part, and the extension part includes N + contact pads arranged on it. 7. For the silicon-controlled rectifier electrostatic discharge protection element of the scope of the patent application, the above-mentioned P + guard ring is grounded. 8. If the silicon-controlled rectifier electrostatic discharge protection element of item 5 of the patent application scope, wherein the above N + planting area is grounded. 9. A Silicon Controlled Rectifier (SCR) electrostatic discharge protection element includes: an N-type substrate or an N-type well; a P-type well formed in the N-type substrate or an N-type well; a first N-type doped The impurity region is formed in the P-type well; the P-type doped region is formed in the N-type substrate or the N-type well; the second N-type doped region is formed in the N-type substrate or the N-type well; And can use the edge of the first N-type doped region of the P-type well to the P 第12頁 492177 六、申請專利範圍 型井交界所構成之距離以調變SCR之觸發電壓,並節省製 / 作電晶體之面積。 1 0 .如申請專利範圍第9項之矽控制整流器靜電放電保護元 件,其中上述之第一 N型掺雜區域連接至一金屬墊。 11.如申請專利範圍第9項之矽控制整流器靜電放電保護元 件,其中上述之第二N型摻雜區域耦合至接地。 1 2 .如申請專利範圍第9項之矽控制整流器靜電放電保護元 $ 件,其中上述之P型摻雜區域耦合至接地。 1 3. —種矽控制整流器靜電放電保護元件包含: N +護環; — P型井,形成於上述護環之内; 产 N+接觸墊,配置於上述P型井之主體上; P+佈植區域,配置於上述F型井兩側;及 上述N +接觸墊周邊至上述P型井邊緣之距離,用以決 定觸發電路值。 1 4.如申請專利範圍第1 3項之矽控制整流器靜電放電保護 元件,其中上述P型井更包含擴展部,上述擴展部包含P + 接觸墊配置於其上。Page 12 492177 VI. Scope of patent application The distance formed by the junction of the wells can be used to modulate the SCR trigger voltage and save the area of making / making transistors. 10. The silicon-controlled rectifier electrostatic discharge protection element according to item 9 of the patent application scope, wherein the above-mentioned first N-type doped region is connected to a metal pad. 11. The silicon-controlled rectifier electrostatic discharge protection element according to item 9 of the patent application scope, wherein the second N-type doped region is coupled to ground. 1 2. The silicon-controlled rectifier electrostatic discharge protection element according to item 9 of the scope of the patent application, wherein the aforementioned P-type doped region is coupled to the ground. 1 3. — A kind of silicon-controlled rectifier electrostatic discharge protection element includes: N + guard ring; — P-shaped well formed in the above-mentioned guard ring; N + contact pads are produced and arranged on the main body of the P-shaped well; P + planting The area is arranged on both sides of the F-type well; and the distance from the periphery of the N + contact pad to the edge of the P-type well is used to determine the trigger circuit value. 1 4. The silicon-controlled rectifier electrostatic discharge protection element according to item 13 of the scope of the patent application, wherein the P-shaped well further includes an extension part, and the extension part includes P + contact pads arranged on it. 第13頁 492177 六、申請專利範圍 1 5 .如申請專利範圍第1 3項之矽控制整流器靜電放電保護 元件,其中上述上述N +護環接地。 1 6 .如申請專利範圍第1 3項之矽控制整流器靜電放電保護 元件,其中上述上述P+佈植區域接地。Page 13 492177 VI. Scope of patent application 1 5. For the silicon-controlled rectifier electrostatic discharge protection element of item 13 of the patent application scope, the above-mentioned N + guard ring is grounded. 16. The silicon-controlled rectifier electrostatic discharge protection element according to item 13 of the scope of patent application, wherein the above-mentioned P + planting area is grounded.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100454534C (en) * 2005-07-04 2009-01-21 崇贸科技股份有限公司 Single-segment and multi-segment triggering type voltage-adjustable static-electricity discharging protection semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100454534C (en) * 2005-07-04 2009-01-21 崇贸科技股份有限公司 Single-segment and multi-segment triggering type voltage-adjustable static-electricity discharging protection semiconductor structure

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