TW492155B - Method for making an active pixel sensor - Google Patents

Abstract

A plurality of active pixel sensors are formed on the surface of a semiconductor wafer. The semiconductor wafer comprises a P-type substrate, an active pixel sensor region and a periphery circuit region. A first active pixel sensor block mask (APSB mask) is formed to cover the active pixel sensor region, then at least one N-well on the surface of the semiconductor wafer not covered by the first APSB mask is formed. A second APSB mask and at least one N-well mask are formed to cover the active pixel sensor region and the region outside the P-well region. At least one P-well on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask is formed. Finally, at least one photodiode and at least one complementary metal-oxide semiconductor (CMOS) transistor are formed on the surface of the active pixel sensor region.

Description

492155 V. Description of the Invention (1) Field of the Invention The present invention provides a method for manufacturing an active pixel sensor, especially a quantum efficiency (quantum efficiency, QE) active pixel sensor manufacturing method. Background: An active pixel sensor is an N-typecha metal oxide semiconductor (N-typecha η ne 1 meta 1-ο X ide semiconductor (NMOS) transistor or complementary transistor) and a light sensor. A semiconductor device composed of a photodiode is generally used in an image sensor of an optical product such as a camera or a scanner. At present, the semiconductor manufacturing process is to simultaneously fabricate the active pixel sensor of the metal oxide semiconductor of the active pixel sensor and the f ί iHPi% r \ Urcuit) containing other components on a chip. Peripheral circuits include CMOS Lei Yue #% FET (PM0S) transistor by N-channel metallization (NM0S) transistor and P-channel metal service main channel ^ milk 1G transistor, The complete CMOS electric sun and sun body, including some resistors (^ sis (capacitor) and other components. In the electrical process, because it must be integrated with the surrounding ^ ^ image sensor ancestor production too CMOS transistor in Wangkou peripheral circuit and main

Page 5 492155 V. Description of the invention (2) N-channel metal oxide semiconductor transistors and photodiodes in the sensing area of the moving pixel, so they will generally follow the standard process of CMOS transistor, The ion implantation process is used as the first ion implantation process in the fabrication of the image sensor wafer. Please refer to FIG. 1, which is a schematic diagram showing a structure of a conventional active pixel sensor. The light sensing area 20 of the conventional active pixel sensor 〇 is provided on the semiconductor wafer 11. The semiconductor wafer Η includes a silicon substrate 12 'and a p-weli i4 provided on the stone substrate 12. The active pixel sensor 10 includes an N-type channel metal-oxide semiconductor (NMOS) transistor 16, which is disposed on the surface of the p-type well 14 and a light sensing area 2. 'Formed on the surface of the p-type well 14 and electrically connected to the drain (drai η) of the NMOS transistor 16. The semiconductor wafer 11 further includes a plurality of field oxide layers 18, and a silicon substrate 12 is provided on the surface and surrounds the photo-sensing area 2o as a dielectric.

Insulating layer of insulating material to avoid short circuit due to contact between the light sensing area 20 and other components. As shown in J.7, FIG. 2 is a schematic diagram of the common structure of the active pixel sensor 10 in the conventional active pixel sensor 10. It is not intended. In some embodiments, the ⑽⑽ region 20 (Sour UrCe) or Drain Urain), which is directly shared with the light sensor 穑 20 = Miscellaneous region 22 'to reduce the size of the active pixel sensor. Second, and Middle, the drain 17 is a high concentration doped region (N +), and It is a low-concentration doped region (N-). Mind & 22

492155 V. Description of the invention (3) As mentioned above, the conventional method for making an active pixel sensor 10 is to perform an N-well implantation process on the entire image sensor wafer, and the N-well The implantation process involves implanting scale ion (ph 〇sph 〇r 〇us) ions 'with a dose of about 1013 / cm' into the wafer with an implantation energy of 100 ~ 200 eV to form an N-type well. Then, a P-type well 14 is implanted in the active pixel sensing area in the image sensing chip to form a p-type well 14, and the implantation of the P-type well 14 is also a high-energy Ion implantation process, and its dose is about 10i3 / cm2, and the dopant is boron ion. Due to the formation of the p-type well 14, a full wafer (b 1 anketimp 1 ant) N-type well implantation process is performed first, and then a p-type well implantation process is used to neutralize the N-well implantation. Therefore, the p-well implantation process is also called a compensation implantation process. However, these two high-implantation ion implantation processes often cause damage to the monocrystalline structure on the surface of the P-type well 1 4, which in turn leads to increased leakage current and high reliability (hi-rel iabi 1 i ty) and other disadvantages. Please refer to FIG. 3, which is a schematic diagram of implanting N-type wells and p-type wells in a conventional image sensing chip 24. The relative positions of the two ion implantation processes on the wafer are shown in Fig. 3A, respectively. The N-well implantation process is performed on the entire image sensing wafer 24, that is, the oblique area in Fig. 3a. , Including the entire active pixel sensing area 2 6. Among them, the area covered by the n-type well cover is the area used to form components such as PMMOS transistors in the peripheral circuit area. However, as shown in FIG. 3B, the P-well implantation process is implanted on all image sensing chips 24 except N-well mask 28, which is shown in FIG. 3β

Page 7 492155 V. The oblique area (P-well implantation range) in the description of the invention (4) also contains the entire active pixel sensing area 26. Due to the sensitivity of a photodiode, the leakage current (1 e a k a g e c u r r e n t) is usually an important indicator. The light leakage current (1 ight current) of the light sensing area of the photodiode under the light represents the signal, and the dark cur rent under no light represents the noise. . Photodiodes use the strength of the signal to noise ratio to process signal data. At present, most methods for improving the quality of the photodiode in the semiconductor industry are to increase the intensity of the signal represented by the leakage current of the light sensing area of the photodiode under light to increase the intensity ratio of the signal to the noise to enhance the signal. Contrast to increase the sensitivity of the light sensing area of the photodiode, thereby improving the quality of the photodiode. Please refer back to FIG. 1. The arsenic ions in the light sensing region 20 of FIG. 1 are along the PN junction of the doped region 22, and form a depletion region with the adjacent p-type wells 14. ) 24, the manufacturing method is to use a south agent ϊKun ion as the main dopant to carry out the ion implantation process. This ion implantation process forms an N-type ion dopant on the surface layer of p-type well 1 4 so that the leakage current passing through the empty region 24 under the light receiving and non-light receiving states = 2 2 is small, which can be used to represent signals and impurities, respectively. News. In Fig. 1, the area with a large dashed line f is the empty area 2 4. Because the N-type doped region 22 in the conventional photodiode and body-sensing sensing region 20 is based on the use of high doses of arsenic and early morning water ~ 1 0

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f Mu quality, this pj well 14 with a high concentration of zirconium, which is completely opened by the heavy doping process, has a high pj ^ after the joining of the pj ^: impurity region 22, and the doping-a narrower width (width) Then, the size of 24 real active regions in the second empty space is reduced, and the actual photoreceptive area 20 of the gas sensing area 20 receiving 10 is passed through the photodiode in the light receiving state. In addition, under the field oxide layer 18 ;; J = at the junction under the current f, ☆ It is easy to have type 2/14 ling when it is not in the light state, and increase noise, reducing the signal noise ratio. . The light sensing region 20 is further weakened. In order to avoid the problem of reducing the common area caused by the above-mentioned heavy doping process, it is now convenient to make the source or drain and doped region 22 ^ + j structure ^ Significantly improve the disadvantages of the structure of Figure 1. Please refer to FIG. 2, which shows that the higher-concentration drain electrode 17 is not connected to P-type well i 4, and the lower-concentration erbium-doped region 22 is directly connected to P-type well 14. Person 4 However, the structure in FIG. 2 still cannot avoid the problem of wafer structure damage caused by the secondary high-energy ion implantation process. Please refer to FIG. 4. FIG. 4 is a schematic diagram showing the structure of an active pixel sensor 30 of a part of the p-well. The light sensing area 40 of the active pixel sensor 30 is provided on the semiconductor wafer 31. The semiconductor wafer 31 includes a silicon substrate 32 and two P-type wells 33 and 34 disposed in the silicon substrate 32. The semiconductor wafer 31 further includes two field oxide layers 3 5 and 36 on the surface of the silicon substrate 32. The active pixel sensor 30 includes an NMOS transistor 38 disposed between the two field oxide layers 35 and 36, and an

492155 V. Description of the invention (6) The light sensing area 40 is formed on the surface layer of the silicon substrate 32 and shares the same area with the drain 39 of the nmos transistor 38. Two-field oxide layers 35 and 36 are provided on the surface of the silicon substrate 32 and surround the NMOS transistor 38. They are used as an insulating layer of a dielectric insulating material, so as to prevent the light sensing area 40 from contacting with other components and causing a short circuit. . The drain 39 of the NMOS transistor 38 is shared with the doped region 42 to reduce the area of the pixel sensor 30. The drain electrode 39 is a high-concentration doped region (N +), and the doped region 42 is a low-concentration doped region (N_). Pass away? Reference is made to FIG. 5. FIG. 5 is a schematic diagram of performing N-type implantation in the conventional image sensing chip 44. ^ It is a schematic diagram of P-type well implantation. The N-type well implantation process in FIG. 6 in the light sensing area outside 40. Although there are some components in the area junction area, such as the ^ t cover that is scheduled to form a 0s transistor, it is not specifically marked in Figure 5A. come out. Then, in the sensing area β, the P-well implantation process is performed in the area outside the dagger 40 when the light is in the active pixel sensing area 46. The photo-sensing area 40 above the N-type and p-type wells will be covered by a photomask. In the structure disclosed in FIG. 4, although the portion occupied by the p-type well is reduced to avoid all the P-type silicon substrates 32 under the sensing area 40, it can be implanted for the first and the second high energy. It was destroyed to solve the bottleneck encountered in the above Figures 1 and 2. But new problems have emerged. Figure 4 shows the place where the soil well 3 3 is connected to the drain electrode 3 9, and the P-type well 34 is connected to the drain electrode 3 9. However, the well 'is easily driven by the subsequent high temperature (drive — i η ) Process, and there are 33, 34 encroachment. Once this phenomenon 492155 V. Description of the invention (7), the actual area of the photodiode will be reduced. In addition to the reduction of the light receiving area, the area of the light sensing area 40 of the different photodiodes 30 ( sensor area), there will be inconsistencies (nonuniformity), resulting in mismatch between different photodiodes, these are the main factors that make the image quality worse. Therefore, how can a new type of active pixel sensor structure be developed to avoid the problem of wafer structure damage and P-well erosion of photodiodes caused by the above-mentioned secondary high-energy ion implantation process, and can form an appropriate The width of the empty area and fewer structural defects to reduce noise and promote the absorption of red light have become very important issues. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide an active pixel sensor structure and a manufacturing method thereof, so as to improve the uniformity of the photosensitive area of the light sensing area of the photodiode and increase the sensitivity of the photodiode. To solve the above problems.

In a preferred embodiment of the present invention, the method first forms a first active pixel sensing block mask (APSB mask) to cover the active pixel sensing area, and then covers the area without the first APSB mask. At least one N-well is formed on the surface of the covered semiconductor wafer. Then remove the first APSB

492155 5. Description of the invention (8) mask, and forming a second APSB mask and at least one N-type well mask on the surface of the semiconductor wafer to respectively cover the active pixel sensing area and the non-P-type in the peripheral circuit area Area of the well. Subsequently, at least one P-well is formed on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask. Finally, the second active pixel sensing block mask and the N-well mask are removed, and at least one photodiode and at least one complementary metal-oxide-semiconductor (CMOS) are formed on the surface of the active pixel sensing area. ) Transistor. It is distinguished by the pixel circuit. The defect of the polar body of the direct sensing element is the good quality of the polar body. The effect of the invention is to use the active pixel sensing block mask (APSB mask) of the present invention. After the N-type well region of the PMOS circuit in the periphery is exposed and the rest of the wafer is shielded, the N-type ion implantation process is performed. In the subsequent production of active image elements, p-type well implantation will no longer be performed, so as to be fabricated on a P-type substrate. Therefore, there are no p-type wells around the light sensing area of the present invention, so there are fewer p-wells, lower leakage current, and less noise. At the same time, the inconsistency in the area of the sensing area of the “## + two-light sensing area” will be significantly improved, and then when the second light is 5 5 0 _, the rate of the photoelectric ° diode of the present invention will be increased to greater than 60. DETAILED DESCRIPTION OF THE INVENTION The present invention provides a light sensing area 70 and a t-moving pixel sensor 60.

492155 V. Description of the invention (9) 1 --- f production method, the following takes a semiconductor wafer 6 1 with a P-type doped silicon substrate 6 2 as an example to describe the light sensor of the active pixel sensor 6 0 of the present invention. The process of measuring area 70. Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of an active pixel sensor 60 of the present invention. The semiconductor wafer 61 includes a p-type silicon substrate 62, a photo-resistive transistor 86, a photodiode region 8 9 and a photo-sensing region 7 0 located in the photodiode region 8 9 Above, a field oxide layer 74 is provided on the surface of the silicon substrate 62 and surrounds the phototransistor 86. The photoelectric induction transistor 8 6 further includes a source electrode 8 7 and a drain electrode 8 8, which are disposed on the surface of the P-type stone evening substrate 62. Among them, the drain electrode 8 8 is a high-concentration doped region (N +) ′, and the n-type sensor implant region 90 in the light sensing region 70 of the photodiode region 89 is A low concentration doped region). The N-type doped region 90 is doped with phosphorous (P) at a concentration of 10 12 / cm, and the drain 88 is doped with phosphorous (P) at a concentration of 1014 / cm. The active pixel sensor 60 of the above embodiment is disposed on a silicon substrate 62 having a P-type dopant. If the silicon substrate 62 is a silicon substrate of an N-type semiconductor, the metal oxide semiconductor provided thereon is PMOS, and the two doped regions included in the light sensing region provided thereon are doped with P-type dopants. Miscellaneous area. In addition, the phototransistor 86 may be replaced by a CMOS transistor. Please refer to FIGS. 7 to 14, which are schematic diagrams of the manufacturing process of the active pixel sensor 60 of the present invention. In the following, an active pixel sensor according to the present invention will be described by taking a semiconductor wafer 61 having a P-type doped silicon substrate 6 2 as an example.

Page 13 492155 V. Description of invention (ίο) 60G light-sensing area 7G manufacturing method. As shown in FIG. 7, the method of the light-sensing region 70 of the light-emitting diode 60 is to first clean the semi-f-body wafer 61 having a P-type silicon substrate ^ and then send the semiconductor wafer% into the heat. Inside the furnace, a silicon oxide layer 63 having a thickness of several hundred angstroms (angstrom) is formed on the surface of the silicon substrate 62 by thermal oxidation in an oxygen-containing environment. Among them, the silicon oxide layer 63 is used as a sacrificiai layer in subsequent ion implantation to increase the scattering of implanted ions and avoid the occurrence of channel phenomenon. x

Then, a chemical vapor deposition (CVD) process is used to fully deposit a silicon nitride (SiD layer 64) having a thickness of about 1000 to 20 = 0 angstroms. Subsequently, a first κ The light process' defines the active area 67 of the CMOS transistor in the peripheral circuit area 65 and the active area 67 of the pixel unit in the active pixel sensing area 69, and then performs a dry etching process to remove the light The protective silicon nitride layer 64 is removed, and the photoresist layer is finally removed. As shown in FIG. 8, an active pixel sensor block mask (APSB mask) is then used to determine

The N-type well region of the PMOS transistor in the peripheral circuit area 65 is defined, and the photoresist layer 73 is used to cover the other areas in the peripheral circuit area 65 and the entire active pixel sensing area 69. = = 10 13 / cm phosphorous (P) ion is the first ion doped

Page 14 492155 V. Description of the invention (π) Planting process' to form at least one N-type well area 71. As shown in FIG. 9 ', the photoresist layer 73 is removed first, and then the nitrogen stone layer 64 remaining on the semiconductor wafer 61 is used as a mask in the area oxidation (LOCOS) process. A field oxide layer 74 (FOX layer) is formed on the semiconductor wafer 61 to isolate the NMOS, PMOS, and the phototransistor transistor formed later. Then use a heated phosphoric acid (H sP oJ as an etching solution) to strip the nitrogen silicon layer 64 in a wet manner. Before forming the field oxide layer 74, a PMOS transistor can be used to cover the peripheral circuit area with a photoresist (Not shown) and the active pixel sensing area, and a P-type ion implantation process is performed on the surface of the wafer to form a channel stop (not shown) on both sides of the NMOS transistor. The silicon oxide layer 63 is completely removed, and a second ion implantation process is performed on the surface of the semiconductor wafer 61 to adjust the threshold voltage adjustment in the active region 67. The second ion implantation process uses a dose of l 〇i2 / cm lacks trivalent boron or BF2 + as a dopant, and the implantation energy is between several dozen KeV. As shown in FIG. 11, a dry oxidation process is performed using a hot furnace tube for semiconductor wafers 6 A gate oxide layer 7 6 is formed on 1, and then a low-pressure chemical vapor deposition method is used to form a polycrystalline silicon layer 7 8 on the surface of the gate oxide layer 7 6, and then an ion implantation process is performed on the polycrystalline silicon layer 7 8 Internal doping. A low pressure chemical vapor deposition, the polysilicon layer 78 to the surface to

Page 15 492155 V. Description of the invention (12) liters (formed into a silicided metal layer 82), and then a yellow light and etching process are performed to form the gates 84 of each NMOS, each PMOS, and each photoelectric induction transistor. Then reused The deposition of the dielectric layer and the adjustment of the selection ratio in the dry etching process form sidewalls 8 5 on both sides of each gate. • As shown in Figure 12, then two different yellow light and ion implantation processes are used. In order to complete the production of the photoelectric sensor transistor 6 in the active pixel sensing area 69, first a third yellow light process is performed, and a sensor mask is used to define a photodiode area 89, Then, a third ion implantation process is performed. In the photodiode region 89, an N ion implantation process using phosphorous ions at a dose of 1012 / cm as a dopant is performed to form a photosensitive dopant (sens 〇r implant) area 90, and above the photodiode area 89 is the light sensing area 70. Then a fourth yellow light process and a fourth ion implantation process are performed for active pixel sensing Photoelectric transistor 8 6 in area 6 9 A n-implantation process using phosphorous ions at a concentration of 10 h / cm as a dopant to form a source / drain (S / Drain) 87 of a phototransistor transistor 86 88. In this two-ion implantation process, the implantation concentration of the N-ion implantation process is lower than that of the n-ion implantation process, but the implantation depth of the N-ion implantation process is deeper than that of the n-ion implantation process. The implantation order of the N ion implantation process and the N ion implantation process can be reversed. As shown in FIG. 13 ', a fifth yellow light and a fifth ion implantation process are performed, and the NMOS in the peripheral circuit area 65 Crystal 92 for N-ion implantation

Page 16 492155 V. Description of the invention (13) Enter the manufacturing process to form the source / drain 93 of the NMOS transistor 92 and complete the production of the NMOS transistor 92 in the peripheral circuit area 65. Before or after the fabrication of the source / electrode 9 3 of the NMOS transistor 92 is completed, an angled ion implantation process may be performed to form a lightly doped non-electrode 92 nm transistor. doped drain, LDD) (not shown). Among them, the lightly doped drain of the NMOS transistor 92 can also be formed before the fabrication process of the sidewall member 85. Next, as shown in FIG. 14, a sixth yellow light and sixth ion implantation process is performed, and a P0S transistor 94 in the peripheral circuit area 65 is subjected to a P implantation process to form the source / injection of the PM0S transistor 94. Pole 95, and complete the fabrication of the PMOS transistor 94 in the peripheral circuit area 65. Finally, the furnace tube is used to perform a drive-in process of about 8 5 0C, so that the source / drain 8 7 and 8 8 of the photoelectric induction transistor 86 are doped, and the source of the NMOS transistor 9 2 is doped. / Drain 9 3 dopant 'Source of the PM0S transistor 94 / drain 95 dopant, and photosensitive dopant 9 0 of the photodiode region 89, driven to a predetermined depth (as shown by the dotted line) In order to complete the production of the photoelectric induction transistor 86 and the peripheral circuit CMOS transistor. In the light sensing area 70 of the active pixel sensor 60 manufactured by the present invention, since there is no p-type well around the light sensing area 70, it can be avoided because of the secondary high-energy implantation. The wafer structure is destroyed, and the phenomenon of p-type well erosion and encroachment will not occur due to subsequent high-temperature drive-in seeding. Therefore, the actual area of the photodiode will not be reduced ’and the area of the light sensing area 70 of the different photodiodes 60,

Page 17 492155 V. Description of the invention (14) (sensor area), there will be no nonuniformity, which significantly improves the mismatch between the different photodiodes (ιη) ί3 · ϋ. At the same time 'Because there are fewer defects in the wafer structure, lower leakage current and less noise. In addition, since the source / drain electrodes 8 7, 8 8 and the photodiode region 8 9 are a common structure That is, the higher concentration of 'Wuji 8 8 is not bonded to the p-type substrate 6 2, but the photosensitive dopant g 0 with a lower concentration is directly bonded to the p-type substrate 6 2'. Therefore, the present invention is utilized The empty area of the photodiode 60 produced by the method has a wide width and a large light absorption range. ~ In short, the method of the present invention first forms a first active pixel sensing block mask (APSB mask) To cover the active pixel sensing area, and then form at least one first well on the surface of the semiconductor wafer that is not covered by the first APSB mask ^ / t. Then remove the first APSB mask and place it on the semiconductor wafer A second APSB mask and at least one first well are formed on the surface Screen to cover the active pixel sensing area and the area of the non-second-type well in the peripheral circuit area respectively. Then the surface of the semiconductor wafer not covered by the second APSB mask and the first-type well mask. At least one second well is formed. Finally, the second active pixel sensing block mask and the first well mask are removed, and at least one photodiode and a photodiode are formed on the surface of the active pixel sensing area. At least one complementary metal-oxide-semiconductor (CMOS) transistor. To sum up, the method of the present invention uses the first active pixel sensing block mask and the second active pixel sensing block mask to avoid this.

Page 18 492155 V. Description of the invention (15) Any of the first type well and the second type well are formed in the active pixel sensing area to improve the quantum efficiency (QE) of the photodiode. For example, when the wavelength of the incident light is 550 nm, the quantum efficiency of the photodiode of the present invention will be greatly improved by more than 60%.

Compared with the light-sensing area of the conventional active pixel sensor, there is no P-well around the light-sensing area of the photodiode produced by the present invention, so that there are fewer defects in the wafer structure and lower leakage current. , Less noise. In addition, the inconsistent area of the light-sensing area of the photodiode will also be significantly improved, thereby improving the quality of the day. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the patentable scope of the present invention shall fall within the scope of the patent of the present invention.

Page 19 492155 Simple explanation of the diagram Simple explanation of the diagram Zone noise? The sensor and sensor image of the sensor and image of the medium and the sensor combined with the structure and structure is a one-to-two picture of the implantation well type P and well gambling. The well-typed P-score β of the sensor image sensor structure shown in Figure 3 with the intention and structure is shown in the figure. The four-picture diagram shows the well-planted P section and the well _ marching in the plate crystal sensor image. The five-picture diagram shows the structured sensor sensor image. This picture is a schematic diagram of the sensor system of the sixth image. The main Mingfa is the forty to seven images. Symbol descriptions 10 Photodiodes 11 Semiconductor wafers 12 Broken substrate 14 P type Well 16 NMOS transistor 17 Drain 18 Field oxide layer 20 Light sensing region 22 N-type doped region 24 Empty region 30 Photodiode 31 Semiconductor wafer 32 $ 夕 基 33、34 P-type well

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492155 Schematic description 35 ^ 36 field oxide layer 38 NM0S transistor 39 drain 40 light sensing area 42 N-type doped area 44 image sensing chip 46 60 active pixel sensing area active pixel sensor 61 semiconductor wafer 62 Broken substrate 63 Silicon oxide layer 64 Silicon nitride layer 65 Peripheral circuit area 66 CMOS transistor 67 Active area 69 Active pixel sensing area 70 Light sensing area 72 N-type well area 73 Photoresistive layer 74 Field oxide layer 76 Gate Oxide layer 78 Polycrystalline silicon layer 82 Metallized metal layer 8 4 Gate 85 Side wall 86 Phototransistor 87 Source 88 89 Drain photodiode region 90 Photoreceptor 92 NM0S transistor 93 Source / Drain 94 PM0S transistor 95 source / impulse

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Claims (1)

492155 VI. Scope of patent application1. A method for making a plurality of active pixel sensors on the surface of a semiconductor wafer. The semiconductor wafer includes a P-type substrate and an active pixel. An active pixel sensor region and a peripheral circuits region. The method includes the following steps: a first yellow light process is performed to form an * active pixel sensor on the surface of the semiconductor wafer; Measure an active pixel sensor block mask (APSB mask) to cover the active pixel sensor area; Performing a first ion implantation process to form at least one first well (we 1 1) on the surface of the semiconductor wafer not covered by the first active pixel sensing block mask; removing the first active pixel Sensing block mask; performing a second yellow light process to form a first active pixel sensing & APSB mask and at least one first well mask on the surface of the semiconductor wafer, respectively Covering the active pixel sensing area and the area other than the second type well in the peripheral circuit area; performing a second ion implantation process so as not to be covered by the second active pixel sensing block and the first The surface of the semiconductor wafer covered by the well mask forms at least one second well; Removing the second active pixel sensing block mask and the first well mask; and forming at least one photodiode and at least one complementary metal-oxide semiconductor on the surface of the active pixel sensing area Page 22 492155 VI. Patent Application (complementary metal-oxide semiconductor, CMOS) transistor. 2. The method of claim 1 in the scope of patent application, wherein the first yellow light process is further formed with at least a second type well cover to cover the area other than the first type well in the peripheral circuit area. 3. The method according to item 1 of the patent application scope further includes a step of forming an insulating layer for forming a plurality of insulating layers to isolate each of the photodiodes and each of the C MOS transistors. 4. The method of claim 3 in the scope of patent application, wherein the plurality of insulating layers include a field oxide (FOX) or shallow trench isolation (STI) ° 5. In the case of claim 1 of the scope of patent application The method, wherein the first active pixel sensing block mask and the second active pixel sensing block mask are used to prevent any of the first wells and the · from forming in the active pixel sensing area. The second type of well is used to improve the quantum efficiency (QE) of the photodiode. 6. The method according to item 1 of the patent application, wherein the first type of well is an N type well, and the second type of well is The pattern well system is a P-type well. 492155 The type well system is 6. Application scope of patent 7: The method of item 1 of the application scope of patent, wherein the first P-type well 'and the second-type well system are an N-type well. ^ A method for making an active pixel sensor ac ^ ve Plxei on the surface of a + conductor The (substrate) includes an active pixel sensing area and a peripheral electrical area, and the peripheral circuit area is used to form a plurality of N-channel metal semiconductor (NMOS) and P-channel metal oxide semiconductor (pMOS). A complementary metal oxide semiconductor (CM0s) is formed. The active pixel sensing area is used to form a plurality of APS transistors and a plurality of photodiodes. The method includes the following steps: On the surface of the semiconductor wafer, a silicon dioxide (SiO 2) layer and a silicon nitride (S i 3N 4) layer are formed; that is, a first yellow light process is performed to define the CMOs in the peripheral circuit area. The active area of the crystal and the active area of the pixel unit in the active pixel sensing area; performing an etching process to remove the nitride that is not protected by the photoresist of the first yellow light process; the layer; An active pixel X e 1 sensor block mask (APSB mask) is formed to define an n-type well area in the peripheral circuit area for making a PM0S transistor, and shield the peripheral circuit area. Other areas and the entire active pixel sensing area; performing a first ion implantation process to form a plurality of N-well (nW e 1 1) areas on the surface of the semiconductor wafer; Page 24 ^ 2155 The scope of the patent application is to form a plurality of field oxide (FOX) layers on the semiconductor wafer to isolate the NMOS and the PMOS. Adjust the starting voltage in the active area; form each of the NMOS, each of the PM0S, and each of the photoelectric induction transistors and a spacer; and perform a third yellow light process to form a sensor mask (Sensor maA) 'to define the photodiode region, and the photodiode region is the same region as the photodiode's drain; ^ a third ion implantation process is performed to the photodiode N-photosensitive doping (sensoI. Impiantin) process is performed in the polar region; a fourth yellow light process is performed to expose the photoelectric induction transistor in the active pixel sensing region; a fourth ion implantation process is performed To form a source / drain (source / drain, S / D) of each of the photoelectric induction transistors in the active pixel sensing area; and perform a fifth yellow light process to expose the peripheral circuit area. nmos transistor A fifth ion implantation process is performed to form the source / drain (source / drain, S / D) of each NMOS transistor in the peripheral circuit area; a sixth yellow light process is performed to expose A PM0S transistor in the peripheral circuit area is shielded and the rest of the peripheral circuit area and the active pixel sensing area are shielded. A sixth ion implantation process is performed to form each of the peripheral circuit areas. Page 25 492155 VI. Scope of patent application: Sources and electrodes of the MEMS transistor are subjected to a high temperature activation process to drive (dri ν ingi η) each of the source / drain and each of The dopants in the photodiode region complete the fabrication of the photoelectric induction transistor and the CMOS. 9. If the method of the scope of patent application No. 8 further includes a channel blocking process, which is performed before the process of the field oxide layer, the channel blocking process includes the following steps: A yellow light process is performed to form a patterned A photoresist layer shields the P M 0 S transistor and the active pixel sensing region in the peripheral circuit area, and performs a P-type ion implantation process on the surface of the semiconductor wafer, so as to form a region of each NMOS transistor. Forming a channel stop around; and removing the patterned photoresist layer. 10. The method according to item 8 of the scope of patent application, wherein the method for producing the field oxide layer includes the following steps: A wet furnace is used to perform a wet oxidation process so that the silicon nitride is not on the semiconductor wafer. Forming a field oxide layer on the portion protected by the layer; and performing a wet etching process to strip the silicon nitride layer on the semiconductor wafer. 1 1. The method according to item 8 of the scope of patent application, wherein the method of making each of the NMOS and each of the PMOS on the semiconductor wafer includes the following steps: Page 26 492155 VI. Scope of patent application ^^ A dry oxidation process is performed using a hot furnace to crystallize a gate oxide layer on the semiconductor; the θ shape is formed by a low-pressure chemical vapor deposition method on the gate oxide layer. Surface formation-crystalline silicon layer; people usually perform an ion implantation process to dope the polycrystalline silicon layer; form a silicide metal layer on the surface of the polycrystalline silicon layer; perform a yellow light process to define each CMOS crystal And the gate pattern of each of the inductive transistors; an etching process is performed to remove the silicided metal layer, the doped polycrystalline silicon layer, and the gate oxide layer that are not used by the photoresist layer of the yellow light process; The photoresist layer. M and 1 2 · The method according to item 8 of the patent application scope, further comprising an ion implantation process with an angled angle to form a heterodyne / drain of each Mos transistor (1 ightly doped drain) , LDD). ^ 1 3-A method for fabricating an active pixel sensor on the surface of a semiconductor wafer. The substrate of the semiconductor wafer includes an active pixel sensing area and a periphery = £ 'this The peripheral circuit area is used to form a plurality of N-channel metal semiconductors (NM0S) and P-channel metal oxide semiconductors (pMOS). J = complementary metal oxide semiconductor (CMOS). The active pixel sensing The area system is used to form a plurality of APS transistors and a plurality of photodiodes. The method includes the following steps: 492155 6. Apply for a patent on the surface of the semiconductor wafer to form a silicon dioxide (SiO2) layer and a silicon nitride (Si 3N 4) layer; perform a first yellow light process to define peripheral circuits The active area of the CMOS transistor in the area, and the active area of the pixel in the active pixel sensing area; performing a surname engraving process to remove the gasification debris layer that is not protected by the photoresist of the first yellow light process; An active pixel sensing area mask (APSB mask) is formed to define an n-type well area in the peripheral circuit area that is used to excite the PM OS electrical body and shield it. The entire area of the peripheral circuit area f ^ the entire active pixel sensing area; ', f ^ is a first ion implantation process to form a plurality of N-Well (N Wen) areas; dry body day The surface shape of the film and the image + i are formed on the film to form a plurality of field oxide layers (FOX) that isolate the NM0S and the PM0S with = ϊ = '; the initial voltage is a second ion implantation process to adjust the active area The risers form each of the NMOS, each of the PM0S, and each of the light mines. The gates and side workers of Yong Lei Sun, and people are divided into two parts, and they are especially responsible for the application of the sun and the sun, "4 ^ spacer); in the process of 'to expose the active pixel sensing area ii: cloth The implantation process is used to form the active pixel sensing area. The source / drain (S / D) of the first inductive transistor is firstly a fourth yellow light process to form a sensor mask. ens〇r Page 28 492155 VI. Patent application mask) to define the photodiode area, and the photodiode area is the same area as the photodiode's drain electrode; perform a fourth ion implantation process To perform an N-sensor implantation process on the photodiode region; to perform a fifth yellow light process to expose the tritium crystals in the peripheral circuit area, and to perform a fifth ion implantation process To form the source / drain (S / D) of the NM0S transistor in the peripheral circuit; ° ^ perform a sixth yellow light process to expose the crystal in the peripheral circuit area and shield the rest of the peripheral circuit area And the main two test areas; study the pixel sense to form each of the peripheral circuit areas and perform a sixth ion implantation process on the source / drain of the PM0S transistor; perform a high temperature activation process, and the L7 choke gate · · · The manufacturing of drone v / dv (dr 1 v 1 ng 1 η) and the read source source transistor and the CMOS in the photodiode region. The photoinductor is doped into the photo-resistor. 14. If the method in the scope of patent application No. 13 is applied, there is another process to implement the photoresistance of the oxide layer in the field. ^ ^ K-channel barrier system has the following steps: Ｍ 私It is possible that the channel blocking process includes performing a yellow light process to form the PM0S transistor and the second photoresist layer in the circuit area to shield the periphery from the semiconductor wafer to the active pixel sensing area. To predetermine the area where each NMOS transistor is to be formed, add n 4 M 丨 丨 ~ rain s to order a P-type ion implantation process, and form a channel block around it. 492155 6. Scope of patent application Remove the patterned photoresist layer. 15. The method according to item 13 of the scope of patent application, wherein the method for producing the field oxide layer includes the following steps: A wet furnace is used to perform a wet oxidation process so that the semiconductor wafer is not nitrided. A portion of the silicon layer is protected to form a field oxide layer; and a wet etching process is performed to strip the silicon nitride layer on the semiconductor wafer. 16. The method according to item 13 of the scope of patent application, wherein the gate method for manufacturing each of the NMOS and each of the PMOS on the semiconductor wafer includes the following steps: A dry oxidation process is performed using a hot furnace tube to the A gate oxide layer is formed on the semiconductor wafer; a low-pressure chemical vapor deposition method is used to form a polycrystalline silicon layer on the surface of the gate oxide layer; an ion implantation process is performed to dope the polycrystalline silicon layer; on the polycrystalline silicon layer A petrified metal layer is formed on the surface; a yellow light process is performed to define a gate pattern of each of the CMOS transistors and each of the photoelectric induction transistors; an etching process is performed to remove a photoresist that is not in the yellow light process Layer, the silicided metal layer, the doped polycrystalline silicon layer, and the gate oxide layer; and removing the photoresist layer. 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