TW492139B - Device with excellent durability to electrostatic discharging - Google Patents

Abstract

The present invention provides a device with excellent durability to electrostatic discharging. The device according to the present invention is provided with two NMOSs with finger-type gates and a N-well. Each NMOS is configured on a P-well. The surface of the N-well is configured with a p-type heavily doped region. With the semiconductor controlled rectifier (SCR) composed of the p-type heavily doped region, N-well, P-well, and NMOS source, the device according to the present invention can provide a very excellent ESD protection; furthermore, it can be used as the driving device for the I/O port. Moreover, the present invention has the shallow trench isolation layer configured around the N-well for reducing the capacitance formed by the P-well and the N-well. Thus, the parasitic capacitance of the device according to the present invention is extremely small, which can be applied to the I/O port for high frequency integrated circuit.

Description

492139 V. Description of the invention (i) The present invention relates to a component with good resistance to electrostatic discharge (ESD), especially 'a kind of high frequency (radiofreauency (rF) integrated circuit) ESD components of input and output ports. As the process evolves, components in integrated circuits (ICs) become more and more vulnerable to ESD damage. Therefore, in the design of 丨 C circuits, it is often between the input and output ports to the power line, or two power supplies. Line-to-line | ESD protection circuit or ESD protection element. When an esd event occurs, the ESD current | can be released from the ESD protection components before the internal semiconductor components are damaged, thus protecting the normal operation of the entire IC. Figure 1 is a cross-sectional view of a conventional esd protection element. Figure 2 shows the layout of the ESD protection element in Figure 1. One kind of ESD protection component is to drive the shame 8 by the high current in the input and output ports, because it occupies a relatively large area of the chip and can provide better heat dissipation. However, in order to save area, in general, the layout of the ‘high current driving M0S’ is designed as a finger-like structure, as shown in FIG. 2. FIG. 1 is a sectional view taken along line AA in FIG. 2. The NMOS in Figures 1 and 2 has four finger-shaped polysilicon gates 20. NMOS is provided on the surface of a p-type well 12. The surface of the p-type well 12 between every two polysilicon gates 20 is a heavily doped region (16 or 18). The N heavily doped region 16 serves as the source of NMOS and is coupled to the power supply line VSS; the N heavily doped region 18 serves as the sink of NMOS and is coupled to the bonding pad pad. When an esd event is a positive pulse relative to the power line VSS When it occurs on the bonding pad pad, the ηρη double junction transistor composed of η heavily doped region 18, P well region 12 and η heavily doped region 16 of NMOS (bip〇iar juncti〇n '492139 V. Description of the invention (2) transistor, BJT) will be triggered to release ESD current. However, the BJT under the finger-shaped MOS cannot be triggered evenly during an ESD event, so the ESD tolerance does not increase with the increase of the channel width of the total NMOS. For example, the finger structure NM0S produced in the 0.3 CMOS process of TSMC, when his channel width is (K4um, the total channel length is I20um, the ESD withstand voltage in human discharge mode is only 0.5kV. , Which does not meet the industrial specifications of 2kV at all. One way to increase the tolerance of the input & input circuit is to connect a semiconductor stone rectifier controller (semiconductor controlling) in the NM0S source.

rectif ier, SCR). See Figures 3A and 3B. FIG. 3A is a cross-sectional view of a low-voltage triggered SCR chip of IEEE electron device letter P.21 in 1991. Fig. 3B is an equivalent circuit diagram of Fig. 3A. SCR has a very good ability to discharge electricity from static electricity. Since the pnp and npnl transistors generate an latch-up when the SCR is turned on, its operating voltage is about 1.2V, and NM〇s as shown in Figure 1 is used. The operating voltage of the parasitic npn transistor is above 4V. Static electricity can be considered as a current source. When the same current flows into different components ’, the lower the operating voltage, the more power and heat it generates,

The smaller. Therefore, the better the electrostatic discharge protection ability. Therefore, using SCR can use a small area to withstand a large electrostatic discharge current. Moreover, the junction of the SCR is NW / PW, and its junction capacitance is much smaller than the junction capacitance of N + / pw (NM0s). Therefore, SCR is the only choice for electrostatic discharge protection with low capacitance. Because: 1 · The area used is much smaller than the NM0S protection element. 2. NW / PW (SCR) junction capacitance < < N + / pw (NM0S) junction capacitance. As shown in the conventional SCR equivalent circuit diagram shown in Figure 3B,

Page 5 492139

The condition of turn-on is that lnw * Rnwl > = 0.7, Ipw * Rp > = 0.7, that is, the files that enable the pnp and npn double junction transistors to start. Only summer 1 疋 If you want to increase

Rnwl makes the SCR turn-on easier. As shown in Figure 3A, the distance between the η heavily doped region 17 and the p heavily doped region 19 must be increased. Therefore, the area of the n-type well 15 is increased, and the drain width of the NMOS is increased. In this way, the power valley of the NW / PW (SCR) junction and the area of the consumed chip will increase at the same time, becoming a protection circuit that is not suitable for high-frequency IC use. Say

In view of this, the main object of the present invention is to provide an NMOS with a finger structure of a parasitic SCR, which can have good ESD tolerance on the one hand, and can be applied to high-frequency 1C on the other hand.

According to the above object, the present invention proposes a component with good resistance to electrostatic discharge (ESD), which is connected between a bonding pad and a power line, and includes two first conductive M0S of the same size, one A second well region of the first conductivity type, a first heavily doped region of the second conductivity type, and an isolation layer. The MOSs are symmetrically disposed on the surfaces of the first well regions of the two second conductivity types, respectively. Each of the MOSs has a source region and a drain region of a first conductivity type, which are respectively coupled to the power line and the bonding pad. The first wells are also coupled to the power line. The second well area is floating between the first well areas. The first heavily doped region is disposed on a surface within the second well region and is coupled to the bonding pad. The insulation layer is closely attached to and surrounds the second well area, so as to prevent a part of the sidewall of the second well area from forming a PN interface with the first well area. The first heavily doped region, the second well region, the first well region, and the source regions form a parasitic iSCR. During an ESI event, the parasitic

Page 6 492139 V. Description of the invention

The SCR is triggered to release the ESD current. At the same time, the insulation layer can effectively reduce the area of the pN junction formed by the first well area and the second well area, so 'the effective capacitance between the first well area and the second well area can be reduced by Effective suppression. The features of the present invention are as follows: 1 "use a source of NMOS to make a set of SCRs, and use the low breakdown voltage of the source to trigger the Scr turn-on. 2 η-type wells are combined> and there are η-type miscellaneous regions 'So the area η-type well can be made very small. On the one hand, it reduces the cost of the wafer and the capacitance value of the η-type well / substrate. On the other hand, it makes the SCR easy to trigger. 3. There is an insulation layer around the η-type well to reduce the effectiveness. Capacitors. Therefore, the parasitic SCR can effectively release the ESD current. Therefore, the present invention can be applied to the input and output ports of high-frequency ICs. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, the following is a comparison. The preferred embodiment and the accompanying drawings are described in detail as follows: Implementation Example: Figure 4A is a schematic cross-sectional view of an esd element of the present invention, and Figure 4B is a top view of an ESD element of the present invention. Section 4A The figure is a cross-sectional view at the line B-B in FIG. 4B. The ESD element of the present invention is provided on a P-shaped substrate 30. The substrate 30 is provided with two ρ-type wells 32 and 〆 η-type well 34 between ρ-type well 32. The surfaces of two P-type wells 32 are respectively provided with a phase. Mutually symmetrical and parallel NMOSs are shown in Figs. 4A and 4B. Each NMOS has a finger gate 44 generally composed of polycrystalline silicon. The surface of the p-well 32 on both sides of the finger gate 44 is provided with η heavily doped regions 40 and 38. η heavily doped region 40 serves as the drain of NMOS, coupled to the junction, and pa (i.n heavily doped region 38 serves as 厶 1 of NMOS. 5. Description of the invention (5) Source ^ It is connected to the electric line ^^ the original line ^. ^ Well 32 is through? Re-dosing the impurity region 36 42 αρ heavy doping ", the surface of well 34 is provided with a heavy P doping region doping Miscellaneous region 40 ° Pal6f = to junction, Pad ° P heavily doped region 42 and two η isolation layers 60. Shallow;: \: 34: P-type well 32 has a shallow trench formed on the surface of the π-type well 34. Layer 60 is close to the side wall of n-type well 34 and surrounds the well. Figure 4B shows that 'P4 doped region 42, n-type well 34, p -scr ::! Η # Λ " 38 ^^ ρηρη ^? ^ ^ ^ SCR φ ^ ^ i Well 34 is in a state of ocean motion and does not have the same two-layer connection as the second layer. The 4CJi / A: n diode. Resistor RP ^ -type well 32 The equivalent circuit diagram of the ES Λ diagram of Zhanming. From the self-correction diagram, we can see that the present = Γί = symmetrical SCR parasitic Therefore, the structure of Figure 4A and Figure 4β of silver I t 2 'can be repeated and discharge two ΓΠ fingers; the interval 44 can be connected in parallel to one with a large current drive: On the one hand, the structure of the invention can be used as an input and output: to cause damage. In order to prevent ESD events, the internal circuit has three characteristics: 1 · Make a fine s Γ1? From the source of N M 0 S, ，, ϊ 朦 类 总 总 总 总 Ρ Ρ Ρ Ρ + + + + + + P + sub-utilization of the source's low breakdown voltage [finally, make SCR turn —〇η. Because the working voltage of the SCR is approximately DU, the element of the present invention can be used as a good ESD protection element 仵 0 492139

2. Small footprint. Among the produced SCRs, the drive MOS originally used as the wheel in / out port is compared with a large part of the SCR method (as shown in ^ and ⑽), and the special one is reduced. In addition, the n-type well 34 of the present invention exhibits thunderbola, which is as large as the n-type state of the n-type heavily doped region 17 in the n-type well 15 in Fig. 3A, and Rnwl in the present invention is europium. In addition to not requiring an n-type capacitor, the 3A plot and the miscellaneous region 17 that reduces the lightning capacity between the n-type well 34 / substrate 30 save the benefits of a low SCR start-up voltage. That is to say, the present invention has

The heavily doped region 42 is biased to 0.7 volts when the n-type well 34 is turned on, and the 彳 5 uses P SCR. Therefore, it meets the small area and small capacitance as well as the smoke starting. The capacitance between the mesh-type wells 34 and p-type wells that are dry-sucking burst voltage will be reduced due to the shallow existence. In other words, the equivalent capacitance of the bonding pad is reduced, so the element invented can be regarded as a high-frequency input / output element. " FIG. 5 is a voltage-current relationship measured by a driving nmos designed according to the present invention and a conventional driving N MOS 0 ′ through a conductive line pulse wave generator. 4um。 Here the structure of the conventional driving NMOS, as shown in Figure 1 and Figure 2, has 4 polysilicon gates, and each polysilicon gate channel width is 30um, channel length is 0.4um. That is, the total channel width of the conventionally driven nmos is 120um. The structure of the driving NMOS of the present invention, as shown in FIG. 4 / v and FIG. 4B, has two polysilicon gates, and each polysilicon channel has a channel width of 30um and a channel length of 0e4um. That is, the total channel width of the driving NMOS of the present invention is 60 μm. The conduction line pulse wave generator can generate a pulse with a pulse width of 100 ns and is input by the bonding pad pad. theory

492139 5. In the description of the invention (7), the product of the secondary breakdown current measured by the conductive line pulse generator and the effective resistance in the human body model (HBM) 1. 5k Ω is affected by The ESD withstand voltage of the device under test. As can be seen from FIG. 5, the second breakdown current of the conventional driving NM0S is about 1 A, and the second breakdown current of the driving NM0S according to the present invention is about 2.5 A, which is 2.5 times the conventional one. . In contrast, in the experiment, the total channel width (60um) of the driving NMOS of the present invention is only half of the total channel width (120um) of the conventional driving NMOS. From this, it can be proved that the drive NMOS designed according to the present invention has superior ESD tolerance. FIG. 6 is a diagram showing the relationship between the E S D withstand voltage for driving N M 0 S and the total channel width for driving NMOS according to the present invention. When the total channel width of the driving NMOS designed according to the present invention is 60um, under ΗBM, the voltage of ESD asset is about 3 ~ 3.5kv. When the total channel width of the driving nmos designed according to the present invention is 120um, under HBM, the ESD withstand voltage is about 5 ~ 5 · 5kv. Therefore, it can be known that the drive circuit designed according to the present invention can effectively protect the internal circuit from the ESD current. The driving NMOS designed according to the present invention can have a very small effective capacitance. For example, if the NMOS designed according to the present invention has two finger gates with a width of 30um and the width of the n + doped region 40 is 2.34um, then two n + doped regions 40 to p-type wells 32 The contact area is approximately 2.34 * 3 (T2 · 2 (~ 140.4um2). If the length and width of the η-type well 34 are 34 and 4.32um, respectively, the area of the η-type well 34 to the ρ-type substrate 30 is approximately It is 34M.32um2 = 1 46.26um2. Most of the sidewalls of the n-type well 34 and the sidewalls of the doped region 40 are replaced by the STI layer 60. Therefore, the sidewalls of the n-type well 34

Page 10 492139 V. Description of the invention ⑻-The parasitic snow capacity generated by the side wall of the n + doped region 40 on the P-type well 32 can be reduced by $. After calculation, when the power supply is 3.3 volts, the total effective capacitance is about 0.02pf, which can be doubled for an RF 1C input and output port. Although the present invention uses NMOS as an embodiment, the present invention can also use two PMOSs as an embodiment. However, the technology of p-type semiconductor and n-type semiconductor interchange is already very common in the industry, and it will not be described in detail here. Compared with the conventional ESD protection element, the ESE protection element of the present invention combines a driving MOS and a parasitic SCR, on the one hand, it can provide a driving current for input and output, and on the other hand, it can provide more conventional ESD protection. Components have good ESD tolerance. In addition, the parasitic capacitance of the ESI) protection element of the present invention is also relatively small, so it can be used in an RP integrated circuit. ^ Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention :: 1 shall be determined by the scope of the appended patent application. ’'492139

Brief description of the drawings: Figure 1 is a cross-sectional view of a conventional ESD protection element; Figure 2 is a schematic layout of the esd protection element of Figure 1; Figure 3A is a cross-sectional view of a low-voltage triggered SCR chip Figure 3B is an equivalent circuit diagram of Figure 3A; Figure 4A® is a schematic cross-sectional view of an ESD element of the present invention; Figure 4B is a top view of an esd element of the present invention; Figure 4C is a figure of Figure 4A and the like Fig. 5 is a voltage-current relationship diagram of a drive NMOS and a conventional drive NMOS designed according to the present invention and measured by a conductive line pulse generator; and Fig. 6 is a drive designed according to the present invention NMOS ESD withstand voltage vs. total channel width driving NMOS. Explanation of symbols: 10, 30 base materials 12, 32 p-type wells 14, 36, 42 P heavy doping 16, 18 ^ 38, 40 η heavy doping 1¾ 20, 44 finger gate 34 η-type well 60 shallow trench isolation

Page 12

Claims (1)

492139 VI. Scope of patent application 1. A component with good electrostatic di scharge (ESD) resistance, connected between a bonding pad and a power line, including: two first conductive M0S of the same size Are respectively arranged in parallel and symmetrically on the surfaces of the first well regions of the two second conductivity types, wherein each of the MOSs has a source region and a drain region of the first conductivity type, which are respectively coupled to the power line and The bonding pad, and the first well areas are also faced to the power line; a second well area of a first conductivity type is floatingly arranged between the first well areas and includes a side wall; a second The first heavily doped region of the conductive type is disposed on the surface of the second well region to the bonding pad; and an insulation layer is closely attached to the second well region to prevent a part of the second well region. The sidewall of the well area forms a PN interface with the first well areas. 2. The element according to item 1 of the scope of patent application, wherein the insulation layer surrounds the second well area on the side. 3. The element according to item 1 of the patent application scope, wherein the isolation layer is a shallow trench isolation layer. 4 · As for the element in the scope of the patent application, each of the MOSs has a finger gate, and the finger gates are coupled to each other. 5. The component according to item 1 of the patent application scope, wherein the first well regions are coupled to the power line through a second heavily doped region of a second conductivity type. 6 · The element according to item 1 of the patent application scope, wherein the element is provided on a substrate surface. 7 · The element according to item 6 of the patent application scope, wherein the substrate is Page 13 492139 VI. Scope of patent application The second conductivity type semiconductor. 8. The element according to item 1 of the patent application scope, wherein the first conductivity type is η-type and the second conductivity type is p-type. 9. The element according to item 1 of the patent application scope, wherein the first conductivity type is p-type and the second conductivity type is n-type.