TW475249B - Device having good electrostatic discharge endurance - Google Patents

Abstract

The present invention proposes a device having good electrostatic discharge endurance. The device of the present invention comprises two NMOS devices having finger-like gates and an n-well, each NMOS device is disposed on a p-well. A heavily doped p-type region is disposed on the surface of n-well. By using the semiconductor controlled rectifier (SCR) formed of p-type heavily doped region, n-well, p-well and the source of NMOS, the device of the present invention can provide an excellent ESD protection. On the other hand, it can be used as the driving device of the input/output port. Also, the parasitic capacitance of the device of the present invention is pretty small, so it can be applied in the input/output port of the high-frequency integrated hybrid circuit.

Description

475249

Ben Sheming refers to an element with good resistance to electrostatic discharge (ESD), especially ESD components that can be applied to the input and output ports of a two-frequency (racjiofrequenCy, rj?) Integrated circuit . Ik is the evolution of the process, integrated circuit,

The components in IC are more and more easily damaged by £ $ d. Therefore, in the IC circuit design, ESD protection circuit or ESD protection components are often set between the input and output ports to the power line, or between the two power lines. When an ESD event occurs, the ESD current can be released from the ESD protection element before the internal semiconductor element is damaged, thereby protecting the normal operation of the entire c. FIG. 1 is a cross-sectional view of a conventional ESD protection element. Figure 2 shows the layout of the ESD protection element in Figure 1. One type of ESD protection element is to drive Mos by the high current in the input and output ports. Because it occupies a large area of the chip, it can provide better heat dissipation. However, in order to save area, in general, the layout of the high-current driven M0S is designed as a finger-like structure, as shown in Figure 2. FIG. 1 is a sectional view taken along line AA in FIG. 2. The NMOS in Figures 1 and 2 has four finger-shaped polysilicon gates 20. NMOS is provided on the surface of a p-type well 12. The surface of the p-type well 12 between every two polysilicon gates 20 is an η heavily doped region (16 or 18). The heavily doped region 16 serves as a source of NMOS and is coupled to a power source.

Line VSS, N heavily doped region 18 as the drain of NM0s, coupled to the pad pad ° When an ESD event with a positive pulse relative to the power line VSS occurs on the access point d, the title is as follows The npn double junction transistor (bip〇Urjunction transistor 'BJT) composed of the heavily doped region 18, the region 12 and n retransmission = 16 will be triggered to release the ESD current.

0503-5501TWF1; TSMC2000-0206; Vincent.ptc Page 4 475249 correction

Case No. 89: 1 Milk U 5. Description of the invention (2) However, the BJT under the finger-shaped MOS is often not evenly triggered during an ESD event, so the ESD tolerance does not follow the channel width of the total NMOS (Channel width) increases. For example, when the finger structure NMOS is manufactured in TSMC's 0.3 CMOS process, when its channel width is 0.4um and the total channel length is i20um, the ESD withstand voltage in human discharge mode is only 〇 5kV, which does not meet the industrial specifications of 2kV at all.

One way to increase the endurance of the I / O ports is to connect a semiconductor ONR control rectifier (SCR) in the OFF source. See Figures 3A and 3B. Figure 3A, 1991 is a cross-sectional view of a low-voltage triggered SCR chip of IEEE electron device letter P.21. Fig. 3B is an equivalent circuit diagram of Fig. 3A. SCR has very good electrostatic electricity discharge ability. Because the pnp and npnl transistors generate latch-up (iatch-up) when the SCR is turned on, its operating voltage is about 2 billion volts. Use the parasitic nPn of NMOS as shown in Figure 1 The operating voltage of the transistor is above 4V. Static electricity can be considered as a current source. When the same current flows into different components', the lower the operating voltage, the less power and heat it generates. Therefore, the better the electrostatic discharge protection ability. Therefore, using SCR can use a small area to withstand a large electrostatic discharge current. Moreover, the junction of the SCR is NW / PW, and its junction capacitance is much smaller than the junction capacitance of N + / pw (NM0s). Therefore, SCR is the only choice for low-capacitance electrostatic discharge protection components. Because: 1 · The area used is much smaller than the NMOS protection element. 2. NW / PW (SCR) junction capacitance < < N + / pw (NM〇s) junction capacitance. As shown in the conventional equivalent circuit diagram of SCR as shown in FIG. 3B, the conditions for SCR to turn nw * Rnwl > u, that is, the conditions for starting the pnp j ^ npn double junction transistor respectively. But if you want to increase

Page 5 0503-5501TW1; TSMC2000-0206; vincent.ptc 475249 correction

_ Case No. 891182U 5. The description of the invention (3) must be added, and NW / PW (is added to make-801 ^ turn-on easier. As shown in Figure 3A, the large η heavily doped region 丨 7 to 1) The distance between the heavily doped regions 9 and 9. The area of the n-type well 15 and the yield of the following drains are wide. (Note Note SCR) The junction capacitance and the chip area consumed will both increase the protection circuit used for the non-aligned frequency I c. In view of this, the main purpose of the present invention is to give birth to the SC's ㈣S of the structure, one side: it can be used in the presence of one's strength, the other can be applied to high-frequency ICs .... have good ESD Resistant to tolerance, the present invention proposes a good electrostatic discharge package with right and taxi pieces' connected between a joint and a power line. The element: has-the same size of the-conductive type _,-the first-conductive And third heavily doped regions of the second conductivity type of the second type. The two identically-sized electric types M0S are respectively disposed on the surface of the second j 2 -well region in parallel and symmetrically. Each-the, Mos has the first- One of the conductive types = ί: ϊίHeavy doped regions are respectively connected between the power line and the first-well regions of the c. The third heavy replacement; the surface of the first well region, Is coupled to the bonding pad. M: the third heavily doped region, the second well region, the first well region, and the SCR region form a parasitic SCR. In the event of an ESD event, the SCR will be It is triggered to release the ESD current. The characteristics of the present invention are: 1. Use the source of the NMOS to make-group ^ ^ and use the low breakdown voltage of the source to The SCR turn_〇n. Is merged, and there are n-type heavily doped regions, so the area of the n-type well can be used to make eggs ^-This reduces the cost of the wafer and reduces the electric conductivity of the n-type well / substrate. Amendment V. Explanation of the invention (4) On the one hand, the SCR is easy to trigger. Therefore, the parasitic SCR can effectively release the ESD current. Therefore, the present invention can be applied to the high-frequency 丨 c input and output 为. The features and advantages are more obvious and easier to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings. The brief description of the drawings is as follows: Figure 1 is a cross-sectional view of a conventional ESD protection element. Figure 2 is a schematic layout of the ESD protection element in Figure 1; Figure 3 A is a cross-sectional view of a low voltage triggered scR chip;% Figure 3B is an equivalent circuit diagram of Figure 3A; Figure 4A is a A schematic cross-sectional view of an ESD element of the present invention; FIG. 4B is a top view of an esD element of the present invention; FIG. 4C is an equivalent circuit diagram of FIG. 4A; and FIG. 5 is a drive NMOs and Known Driving NMOS 'Pulse Waves Through Conduction Line Figure 6 shows the relationship between the voltage and current measured by the generator; and Figure 6 shows the relationship between the withstand voltage and the total channel width of the driving NMOS. Materials; 32 ~ p-type wells; 36, 42 ~ p heavily doped regions; 18, 38, 40 ~ n heavily doped 44 ~ finger gates; hetero region 10 > 30 12 14 16 20 34 ~ η type wells

475249 _Case No. 891182U ^ ----------- Year, Month, Day and Five, Description of Invention (5) '" Example: Figure 4A is a schematic cross-sectional view of a private ESD component, Figure a Is a top view of the ESD device of the present invention. Figure 48 is a cross-sectional view taken along the line 4β. The ESD element of the present invention is disposed on a p-type substrate. The substrate 30 is provided with two p-type wells 32 and an n-type well 34 disposed in two p-type wells 32. Two P-type wells 32 Each surface is provided with a parallel surface, as shown in Figure 4A and Figure 4β. Each face center is a finger-shaped gate 44, which is generally composed of polycrystalline fragments. Finger-shaped double-sided wells The surface of 32 is provided with 0 heavily doped regions 40 and 38 heavily doped regions 40 as NMOS drains, which are connected to the bonding 塾 _βη heavily doped regions as the source of the gate, and connected to the power line The vss 1-type well 32 is a heavily doped region that is connected to the power line VSS. Inside the surface of the n-type well 34 is provided a heavy-duty pushing area 42. The p heavily doped region 42 is coupled to a bonding pad pad. As can be seen from Figs. 4A and 4B, the p-doped region 42, the n-type well 34, the well 32, and the n-doped region 38 happen to have a structure of pnpn, so they can be used as an SCR. Moreover, the n-type well 34 is in a floating state, and each layer is not directly coupled to a potential as in a general SCR. The junction between the ρ heavily doped region and the ^ -type well forms a diode. The resistance of the R0p-type well ^. Figure 4C is an equivalent circuit diagram of Figure 4A. As can be seen from Figure 4C, the present invention The ESD element has two symmetrical SCR parasites inside, so it can effectively release the esd current during the event. Of course, the structure of Figure 4A and Figure 4B can be repeated side by side, and all the finger gates 44 It can be connected in parallel to an NM with high current driving force. In this way, the structure of the present invention can be used as an input and output port to drive fOS on the one hand, and on the other hand, it can prevent ESD events from creating internal circuits 475249

Into damage. The characteristics of the present invention are twofold: 1. A set of SCRs are made from the source of NMOS, and the voltage of the brake field and the store is used to trigger the SCR turn-on. Because ⑽'s and / ^^ 's low crash. Therefore, the element of the present invention can be used as a good one: 2. The occupied area is small. Among the produced SCRs, there are —, —, and M0S that were originally used as input and output ports. Compared with the known method (as shown in Figures 3A and 3B), the area of the present invention has been greatly reduced. . Moreover, the 0-type well 34 of the present invention exhibits an electrically floating state, and is not as good as the n-type heavily doped region 17 in the n-type well 15 in FIG. 3A. In contrast, I in the present invention is 〇〇. In addition to the advantages of not requiring 0-type heavy "zone 17 to save the surface θ product and reduce the capacitance between the η-type well 34 / base material 30, there is also the benefit of reducing the SCR start-up voltage. That is, the elements of the present invention utilize The 0. 7 volt bias when the heavily doped region 42 to the n-type well 34 is turned on is used to start the SCR. Therefore, it meets the objectives of small area and small capacitance and reducing the trigger voltage.

Fig. 5 is a voltage-current relationship diagram measured by the driving NMOS designed according to the present invention and the conventional driving NMOS and the second transmission line pulse wave generator. Here, the conventional structure for driving NMOS, as shown in Fig. I and Fig. 2, has four polysilicon gates, and each polysilicon gate has a channel width of 30 'and a channel length of 0.4um. That is to say, the total channel width of the conventional driving Li OS is 120um. The driving structure of the present invention, as shown in Figs. 4A and 4B, has two polysilicon gates, and each polysilicon gate has a channel width of 30um and a channel length of 0.4um. That is, the driving dragon of the present invention.

475249 Case No. 89118214 _a. Name V. Description of the invention (7) A pulse with a wave width of 100ns is input by a bonding pad. Theoretically, the product of the secondary breakdown current measured by the conductive line pulse wave generator and the effective resistance in the human body model (HBM) 1.5 · 1 Ω is the ESD withstand voltage of the device under test. It can be known from FIG. 5 that the conventional primary current of driving N M 0 S is about 1 A, and the secondary crash current of driving NMOS according to the present invention is about 2.5 A, which is well known. 2. 5 times. In contrast, in the experiment, the total channel width (60 μm) of the driving NMOS of the present invention is only half of the total channel width (120 μm) of the conventional driving NMOS. Therefore, it can be proved that the drive NMOs designed according to the present invention has superior ESD tolerance. Fig. 6 is a diagram showing the relationship between the ESD withstand voltage of the drive .OS designed according to the present invention and the total channel width of the drive NMOS. When the total channel width of the driving NMOS designed according to the present invention is 60um, under HBM, the ESD withstand voltage is about 3 ~ 3.5kv. When the total channel width of the drive NMOs designed according to the present invention is 120 μm, under HBM, the ESD withstand voltage is about 5 ~ 5 · 5kv. Therefore, it can be known that the driving circuit designed according to the present invention can effectively protect the internal circuit from the ESD current. The driving NMOS designed according to the present invention can have a very small effective capacitance. For example, 'there are two finger gates with a width of 30um and the width of the n + doped region 40 is 2.34um, the contact area of the two n + doped regions 40 to the p-type well 32 is about 2.34 * 30 * 2um2 (~ 140.4um2), because the n + doped region 40 is a shallow implant region, the lateral area is negligible. Assuming that the length and width of the η-type well 34 are 34 and 4.32um ', respectively, the area of the η-type well 34 to the ρ-type well 34 is about 34 * 4 · 32um2. The total effective capacitance is about 0.27pf, which is the input and output of an rf ic

0503-5501TWF1, TSMC2000-0206; vincent.ptc

Page 10 475249 V. Description of the invention (8) The port is acceptable. P_ = Γ_〇δ is taken as an example, but the dry rod which can also be used in the present invention is too fr 2: t The technology of P-type semiconductors and n-type semiconductors is not common in the industry, so I wo n’t repeat them here. . Compared with the conventional ESD protection element, ^ combined-drive MOS and a parasitic '★ Mingzhi ESD protection of the drive current into the port, on the other hand can provide good ESD resistance of the output part Force. T ^ ESD protection for car owners. The present invention uses a preferred embodiment to reveal that Ru is not invented by a ruler: He is familiar with this skill, and does not leave: The invention is equal to the target range / when Some modifications and retouching can be done, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. μ

Claims (1)

475249 6. Scope of patent application 1. A component with good resistance to electrostatic discharge (ESD), connected between a bonding pad and a power line, including: "two first conductive devices of the same size Type M0S is disposed on the surface of the first well region of the second conductivity type in parallel and symmetrically, respectively, wherein each of these m0s has a first heavily doped region and a second heavily doped region of the first conductivity type. Miscellaneous regions are respectively coupled to the power line and the bonding pad, and the first well regions are also coupled between a second well region of a first conductivity type; and a third heavily doped surface of a second conductivity type. To the joint pad. The floating ground is located in the miscellaneous area of the first well area, and the second well area is located in the second well area. State =, eight, each of these 3. If you apply for one of the items in the scope of the patent application! One of them, where the first well area is through the second weight of a second conductivity type. The miscellaneous area of the scope of the patent application is consumed by the power cord and the substrate te) the surface. The element is composed of a semiconductor of the second conductivity type, such as in the scope of patent application No. 4; 'wherein' the base material is 6; such as the Yuandu type in the scope of patent application, No. 1. The first conductive type is the p-type, and the second conductive type is the n-type s. The first conductive type is the p-type, and the second conductive type is the n-type s. 'Wherein the first conductive «12 pages