TW488016B - Method for suppressing the defect occurrence in dielectric layer - Google Patents

Abstract

The present invention provides a suppressing method for defect generation in the dielectric layer on the semiconductor substrate. The method is first to conduct a microwave processing to the dielectric layer on the surface of the semiconductor substrate; and, conducting a reflow processing on the dielectric layer to planarize the dielectric surface; wherein, the microwave processing step is conducted with different powers for polar molecules in different depths to process the excitation operation for evaporating the polar molecules, and further to prevent the solid or liquid defects caused by the absorption of polar molecules in boronphosphate during reflow.

Description

488016 V. Description of the invention (1) Field of the invention The present invention provides a method for suppressing the generation of defects in a dielectric layer and a dielectric layer formed on a semiconductor. Background: Borophosphosilicate glass (BPSGS) and borophospho-tetra-ehtyl-ortho silicate (BPTEOS) containing shed fillings are a type of boron-phosphorus-containing dioxide. It is widely used in the inter-layer dielectric layer (IDL) of VLS I. This type of BPSG / BPT0ES can be formed by adding a small amount of phosphorus and boron compounds in the atmospheric pressure chemical vapor deposition (A PC VD) reaction of silicon dioxide, and its characteristics are better than the appearance of ordinary dioxide It is smoother, and the glass transition temperature is lower, about 850 ~ 950 ° C. Therefore, we can improve the flatness of the surface of the BPSG / BPTE0S by applying high-temperature thermal flow to the surface of the BPSG / BPTEOS, thereby reducing the BPSG / BPTEOS deposited layer from the undulation of the wafer surface. In addition, after the contact (c ntact) lithography and other steps, the second heat flow step of BPSG / BPTE 0 S is usually performed, that is, the reflux (ref 1 〇w) process to make the BPSG / BPTE0S sink. The layered engraved wheel is relatively smooth, which is conducive to the subsequent performance of the metal layer splash key in the last name hole (spu 11 ering)

Page 4 488016 5. Description of the invention (2) Process. As the integration of VLSI increases, the yellow light technology has progressed to below 0 · 15 // m, so the topography of the component surface must be smoother, so it is usually used to increase the use of boron and phosphorus. Concentration to increase the melting of BPSG / BPTEOS to obtain a more flat effect. However, increasing the dopant concentration of boron and phosphorus will cause the BPSG / BPTE0S deposition layer to be unstable, and a large amount of crystalline particles will be formed on the surface of the deposition layer, resulting in solid and liquid defects on the BPSG / BPTE0S, which will seriously affect the efficiency of the wafer. Please refer to Figures 1-3. Figures 1-3 are simple schematic diagrams of defect formation patterns on the BPSG / BPTE0S dielectric layer. As shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12 and a BPSG / BPTEOS dielectric layer 14 formed on the surface of the silicon substrate 12. Usually after the BPSG / BPTEOS dielectric layer 14 is formed, the surface of the dielectric layer 14 will absorb water vapor 16 in the air, so that dopants (boron, phosphorus) in the dielectric layer 14 interact with water. Action to form a dopant solution 18. Then as shown in FIG. 2 ', the wafer is placed in a hot furnace tube, and nitrogen, oxygen, or a mixed gas of the two is passed as a carrier gas 20 to perform a high-temperature reflux process. During the early stage of the high temperature reflow step (e a r 1 i e r s t age), the dopant solution 18 will diffuse to the surface of the dielectric layer i 4, so that water vapor and some of the dopants will evaporate on the surface of the dielectric layer 14 to leave crystal nuclei.

488016 V. Description of the invention (3) (nucleus) 22, and some dopants are retained in the gaseous form in the surface environment of the semiconductor wafer 10. Then, the crystal nuclei 2 2 remaining on the surface of the dielectric layer 14 will interact with water and gas to grow and form surface defects. After two hours, as shown in Figure 2, in the reflow step, in the late sfage, surface defects will continuously interact with water vapor 16 in the air and undergo defect merging, and then form through the water vapor evaporation process. Crystal 24, which remains on the gaseous side of the semiconductor wafer 10 environment, and the dopant also interacts with water and gas to perform gas phase deposition 26, and crystal 24 is formed on the surface of the dielectric layer 14, thereby causing Crystal 24 growth (crystal growth), affecting the yield. ❶ Based on research by M.yoshimaru and H.wakamatsu (J.

Electrochem. Soc., 1996) showed that the formation and side filling concentration of defects, the reflow temperature, the thickness of the borophosphosilicate glass film, the cooling rate after reflow, the carrier gas flow rate in the reflow furnace tube, and the Kind-related. Therefore, the current methods for suppressing the formation of BPSG / BPT0ES defects generally include the following two methods: 1. Inhibition of water vapor adsorption: Because water vapor adsorption on the BPSG sedimentary layer is the main cause of defects on the sedimentary layer, pre-tempering can be used. (Pre-anneal) Remove most of the surface water before reflow or add a waterproof layer to prevent water vapor adsorption, or limit it to 12 to 24 hours to return to the tube to reduce water absorption. In addition, in BPTE0S, because BPTE0S has a by-product water during the deposition reaction, it is allowed to stand for several hours before reflow to make water in the sedimentary layer.

Page 6 488016 V. Description of the invention (4) Evaporation of gas to prevent water gas adsorption. 2. Prevent the formation and growth of crystalline nuclei: Because the wafer arrangement in the reflow furnace tube is perpendicular to the flow direction of the carrying gas, the surface of the BPSG deposition layer volatilizes, and the boron and phosphorus gas is easily stagnated between the wafers, causing the gas phase in the later stage of reflow Deposition on the BPSG film makes the crystal grow, so it can be used to increase the spacing between wafers in the reflow furnace tube, or increase the flow rate of the gas carried in the reflow furnace tube to prevent crystal growth.

However, these conventional solutions each have their own disadvantages, whether it is the consumption of cycle time (cyc 1 etime) caused by standing for several hours or increasing the wafer pitch, or the cost of expensive equipment (pre-tempering requires additional furnace tubes) Or U RTA), or it will reduce the concentration of boron and phosphorus and affect the flattening effect (such as pre-heat treatment or adding a waterproof layer), which will cause a time and cost burden, and the water removal efficiency of these methods or the effect of suppressing the formation of defects limited. SUMMARY OF THE INVENTION The main object of the present invention is to provide a manufacturing method for suppressing defects in a dielectric layer formed on a semiconductor substrate to solve the above problems. An embodiment of the present invention first provides a semiconductor substrate, and deposits a dielectric layer on the surface of the substrate by a chemical vapor deposition method, and then performs a microwave treatment on the dielectric layer on the surface of the semiconductor substrate to remove the dielectric layer. Polar molecules, and finally a reflow treatment of the dielectric layer on the surface of the semiconductor substrate

Page 7 488016 5. Description of the invention (5) To planarize the surface of the dielectric layer. The invention uses a microwave processing step, which can use different powers to excite polar molecules at different depths to evaporate the polar molecules, thus preventing solid molecules or liquid defects due to the absorption of polar molecules by side scales during reflow. Detailed description of the invention Please refer to FIGS. 4 to 7. FIGS. 4 to 7 are schematic diagrams of a process for fabricating a dielectric layer capable of suppressing defect formation according to the present invention. As shown in FIG. 4, the semiconductor wafer 30 includes a silicon substrate 32 and a plurality of active areas 34 and 36 provided on the surface of the silicon substrate 3 2 and a plurality of shallow trenches 38 provided on the two phases. Adjacent active areas 34, 36 are used as electrical isolation. Two gates 40 and 42 are respectively provided in the active regions 34 and 36, and source 44 and 46 and drains 48 and 50 are respectively provided on both sides of the gates 40 and 42. Then, as shown in Figure 5, using SiH4 (silane) / PH3 (phosphine) / B2H6 (diborane) and TE0S (tetraethy 1 orthosi1icate) / 03 / TMP (tri-Methyl-phosphate) / TEB (tri-ethyl-borate) A low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or plasma chemical vapor deposition (PECVD) reaction forms a dielectric layer 52 made of BPSG or BPTEOS on the semiconductor wafer 30 to cover the gate. Pole 40, 42 and silicon

Page 8 488016 V. Description of the invention (6) Substrate 3 2. Subsequently, the semiconductor wafer 30 is sent into a hot furnace tube, and the appearance of BPSG / BPTE0S is flattened with the undulation of the wafer surface at a high temperature of 850 ~ 950 ° C, so as to facilitate the subsequent metallization process. Then, as shown in FIG. 6, a lithography and etching process is performed to form a plurality of contact holes (c ο ntacth ο 1 e) 5 4 and 5 6 in the dielectric layer 5 2 to connect different transistors respectively. Gate 4 and drain 50. Then, before reflowing (re f 1 0w) the BPSG / BPTEOS on the surface of the semiconductor wafer 30, a microwave treatment on the surface of the semiconductor wafer 30 with a frequency of 2450 MHz and a power of 100 to 20000W is performed. Among them, the microwave treatment can be used to excite specific polar molecules, so different powers can be used to evaporate water molecules at different depths in the dielectric layer without affecting other elements', and pass in nitrogen, oxygen, or nitrogen and oxygen at the same time. The mixed gas is used to assist the volatility of water vapor and avoid re-adsorption of water vapor on the surface. In addition, the microwave treatment may be performed before the lithography and surname engraving process, that is, the microwave treatment is performed first, and then a plurality of contact holes 5 4 and 5 6 are formed in the dielectric ^ 52. 9 The reflow step of the BPSG / BPTEOS dielectric layer 52 is then performed. Due to the poor step coverage of the metal layer deposited by the sputtering method, the wafer was sent to a hot furnace tube to be heated to 80 to 1000. 〇 Nitrogen gas, gas ^ 1 ^ is a mixed gas of nitrogen and oxygen in the hot furnace tube for reflow to make the yarn engraved; the outline of the dielectric layer is inclined to facilitate the subsequent metal sputtering, as shown in Figure 7 As shown. Finally, processes such as metal sputtering are continued to complete the subsequent Mos metallization process. '

$ 9 pages 488016 5. Description of the invention (7) Since the present invention uses the microwave step to reduce the moisture absorbed by the surface layer of the film according to the formation mechanism of the defects, it can suppress the progress of the rolling mill and reduce the number of defects. Please refer to FIG. 8 to FIG. 10, which are schematic diagrams of a method for suppressing defect formation by using the present invention. As shown in FIG. 8, the BPSG / BPTE0S dielectric layer 52 is located on the silicon substrate 32 of the semiconductor wafer 30, and the dielectric layer 52 absorbs water vapor 60 from the air so that the butterfly, phosphorus dopants, and water in the dielectric layer Gas 60 acts to form a dopant solution 62. Next, as shown in FIG. 9, before reflowing, a micro n-wave treatment 5 8 is performed on the surface of the dielectric layer 5 2 to evaporate the water in the dopant solution 62 of different depths, and simultaneously pass in nitrogen, oxygen, or nitrogen. Oxygen mixed gas 64 is used to volatilize and take away water vapor. Therefore, during the reflow step, as shown in FIG. 10, the dielectric layer 5 2 has an insufficient amount of water, which results in the number of crystals 6 6 precipitated on the surface of the wafer 30. It is greatly reduced, and the crystal 66 particles are smaller than the crystal 24 particles in the conventional technology, thereby suppressing the formation of defects on the dielectric layer and avoiding the effect of the wafer due to the precipitation of crystal particles of boron and phosphorus. It uses microwave treatment to remove the moisture in the BPSG / BPTE 0 S dielectric layer and suppress the formation of defects. Therefore, the thermal energy generated is small and will not affect other elements in the deposited layer (such as boron, phosphorus, silicon, etc.) Therefore, not only the thermal budget is low, which can avoid affecting the operation of the components. In addition, microwave processing has the advantages of very simple mechanical structure, cheap price, strong water removal efficiency, and operation at room temperature. It can even be directly attached to the reflow furnace. In-tube, greatly simplified

Page 10 488016 V. Description of the invention (8) Process flow. Compared with other conventional methods, this method does not need to purchase expensive equipment or consume cycle time. It can perform instant deep evaporation of water molecules at room temperature, which is less time and cost than the pre-tempering method. It is also more efficient in removing water vapor than increasing nitrogen flow or tempering. Moreover, this method can also save processing time by multiple batches of processing methods, and it is economical to increase the pitch and double the cycle time. In addition, if the microwave step is stopped for a long time, the microwave step can be performed again or the microwave can be performed before the reflow to eliminate the problem of time-injection. Therefore, the production line can be more efficient and all the conventional technical problems can be solved. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 11 488016 Brief description of the diagrams Brief description of the diagrams Figures 1 to 3 are simple schematic diagrams of the defect formation modes on the BPSG / BPTEO S dielectric layer. Figures 4 to 7 are made by the present invention to suppress the formation of defects. Schematic diagram of the electrical layer process. Figures 8 to 10 are simple schematic diagrams of suppressing the formation of defects according to the present invention. Symbols shown in the figure 10 '3.0 Semiconductor wafer 12, 32 Silicon substrate 14, 32' 52 Dielectric layer 16 ^ 60 Water vapor 18, 62 Dopant solution 20 ^ 64 Carrying gas 22 Crystal core 2 Core 66 Junction / 26 Gas Facies deposition, 34 second motion domain 38 shallow trench isolation 40, 42 gate 44 ^ 46 source 48, 50 drain 54 '56 plug hole 58 microwave processing #

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Claims (1)

488016 VI. Application Patent Scope 1. A method for preventing H generated by a dielectric layer, the dielectric-dielectric layer being a surface of a ferroconductor substrate, the method comprising the following steps: performing a microwave on the dielectric layer on the surface of the semiconductor substrate A microwave process; and performing a reflow process on the dielectric layer on the surface of the semiconductor substrate to planarize the surface of the dielectric layer. 2. The method according to item 1 of the patent application, wherein the dielectric layer is borophosphosilicate glass (BPSG) or borophospho-tetra-ethyl-ortho-si containing boron and phosphorus 1icate, BPTE0S) 〇3. For the method in the second item of the patent application, the dielectric layer uses a low pressure chemical vapor deposition (LPCVD), atmospheric pressure vapor deposition (atmospheric) pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD) is formed on the semiconductor substrate. 4. The method according to item 2 of the patent application, wherein the microwave processing step is used to remove most of the polar molecules in the dielectric layer. 5. The method of claim 4 in the scope of patent application, wherein the polar molecule is a water molecule, and the buccal rate of the microwave treatment is 2450 ΜΗζ. Page 13 488016 6. Scope of patent application 6. For the method of scope 5 of the patent application, the power of the microwave treatment is 100 ~ 2000W to remove water molecules of different depths in the dielectric layer, thereby preventing During the reflow process, boron and phosphorus in the dielectric layer absorb solid defects or liquid defects caused by the water molecules. 7. The method according to item 1 of the scope of patent application, wherein the temperature of the reflow treatment is 800 ~ 100 ° C. 8. The method of claim 1, wherein the reflow treatment is performed in an atmosphere containing nitrogen, oxygen, or a mixed gas of nitrogen and oxygen. 9. A method of forming a dielectric layer, the method comprising There are the following steps: providing a semiconductor substrate; depositing the dielectric layer on the surface of the semiconductor substrate by a chemical vapor deposition method (chemica 1 vapor deposition, CVD); and performing a microwave on the dielectric layer on the surface of the semiconductor substrate A microwave process; and performing a reflow process on the dielectric layer on the surface of the semiconductor substrate to planarize the surface of the dielectric layer. 10. The method according to item 9 of the scope of patent application, wherein the dielectric layer is borophosphosilicate glass (BPSG) or tetraethoxysilane containing boron and phosphorus atoms. Page 14 488016 VI. Patent application scope (BPTE0S) ° 1 1. The method according to item 9 of the patent application scope, wherein the chemical vapor deposition method is a low pressure chemical vapor deposition method (LPCVD), atmospheric pressure chemical gas Phase deposition (APCVD) or plasma chemical vapor deposition (PECVD). 1 2. The method according to item 9 of the scope of patent application, wherein the temperature of the reflow treatment is 80 ° to 100 ° C. 1 3. The method according to item 9 of the patent application, wherein the reflow treatment is performed in an atmosphere containing nitrogen, oxygen, or a mixed gas of nitrogen and oxygen. 1 4. The method according to item 9 of the patent application, wherein the The frequency of microwave processing is 2450MHz. 15. The method of claim 9 in the scope of patent application, wherein the microwave processing step is used to remove most of the polar molecules in the dielectric layer. # 1 6. The method according to item 15 of the scope of patent application, wherein the polar molecule is a water molecule. 1 7. The method according to item 16 of the scope of patent application, wherein the power of the microwave treatment is 100 ~ 2000W to remove water molecules of different depths in the dielectric layer, thereby preventing the medium from being subjected to the reflow treatment. Boron and phosphorus absorption in the electrical layer Page 15 488016 VI. Scope of patent application Solid or liquid defects caused by these water molecules Φ Page 16