TW480833B - Integrated receiver with digital signal processing - Google Patents

Abstract

A receiver (10), such as a television receiver, includes a tuner (20) and a receiver integrated circuit (100). The receiver integrated circuit (100) includes a high-image rejection mixer (110) and an analog-to-digital converter (ADC) (130) to provide a digital representation of signals received by the tuner (20), which may be in one of several formats, such as an NTSC format or a PAL format. Digital signals from the ADC (130) are digitally down converted (140, 150) and filtered (144, 154, 192) and may be formatted as an intermediate frequency (IF) signal or be decoded into digital video signals for a display device (60) and digital audio signals for an audio reproduction device (70). As a result of the digital frequency conversion, efficient digital filtering is employed in place of conventional bulky and costly SAW filters, and digital words having a greater number of bits than the digital data produced by the ADC (130) are available for digital signal processing.

Description

480833 V. Description of the Invention (1) This case requests US Provisional Patent Application No. 60/1 54 0 2 9 for the rights and interests of September 16, 1999. The present invention relates to a receiver, and more particularly to a receiver including a digital signal processing configuration. As TV receiver technology matures and additional functional features are added to products, the problem of how to fill additional electronic circuits into physical products at a cost that consumers can afford has been solved by using integrated circuit technology. Special circuits are not implemented on a single integrated circuit, but are implemented in a set of multiple integrated circuits. Restrictions on combining certain functions in an integrated circuit include the compatibility of the special circuits used to perform these functions, and the compatibility of the integrated circuit processing technology required by these circuits. For example, combining digital circuits and analog circuits on the same integrated circuit causes a set of problems to be solved. Combining high-frequency analog signal processing and wide-band digital signal processing causes another set of problems. Another issue arises as the number of circuits to be formed on a single integrated circuit increases, the cost also increases and the yield of satisfactory devices decreases. In addition, the conventional receiver has performed channel selection as part of the analog intermediate frequency (IF) process, selecting a predetermined channel IF signal by using a surface acoustic wave (SAW) or a ceramic band-pass filter, and excluding unwanted adjacent channel signals. However, the physical size of SAW filters and ceramic filters is large, so they are not suitable for integration into integrated circuits with electronic circuits. In addition, these filters are expensive and undesirable. Thus, what is needed is a receiver configuration suitable for implementation as an integrated circuit.

480833

In order to achieve this project, this place receives the information carrying signal and the information carrying signal in the frequency combiner to provide the frequency migration source at a predetermined frequency coupling to the analog to digital rate migration digital word sequence. The output signal is filtered and displayed. According to another aspect of the present invention, a mixer includes a first and a frequency of the mixer for responding to a shifted information-bearing signal and a frequency of a second mixing circuit and a real number of the combiner. At least one analog to digital is used to couple the frequency-shifted digital multiplier to a fixed frequency-like sinusoidal shifted digital word sequence, and digitally filters the frequency shifted digital word in a receiver invented by an output port. A mixer is coupled to, and an analog to digital information-bearing signal is converted into a sinusoidal digital rendering converter, and a digital filter is coupled to the shifted digital word sequence. A receiver integrated second hybrid circuit, the rate of the information of the first predetermined frequency signal, and a combiner utilization rate are excluded from the information carrier after the migration. The frequency-bit converter coupled to the mixed information carrier signal is converted to a ratio to digital. The converter and the digital presentation source are coupled to the shifted digital word sequence by a digital filter, with one less input, and are used at the input port to transfer the converter to the mixed sequence digital word. Now, a digital multiplication source generates a generation circuit with a predetermined frequency digital multiplier and an output circuit word sequence. At least one carrier signal is coupled to individual orthogonal components to combine the signals from the first signal component. A sequence of digital words, which is a combination of a serializer and a combiner. A coupled to the second pre-predetermined frequency shift_ digital multiplier and to provide a simple description of the filtered pattern

Page 480833 V. Description of the invention (3) The detailed description of the preferred embodiment of the present invention will be easier to understand when read together with the schematic composition. The drawings include: Figure 1 is a schematic view of a receiver according to the present invention. Schematic block diagram of a specific embodiment; Figure 2 is the amplitude versus frequency characteristics associated with the specific embodiment of Figure 1; Figures 3 A to 3 E are schematic block diagrams of example mixers that can be used with the receiver of Figure 1; Figure 4A is Schematic diagram of an example phase shift and amplitude adjustment network of an oscillator that can be used in the specific embodiments of Figures i &3b-3E; Figure 4B is a schematic diagram of the example adjustment network of Figure 4A and Figure 3 (: example mixer) Figure 5 is a schematic diagram of a ring oscillator that can be used in the specific embodiment of Figure 1; Figure 6 is a schematic diagram of a specific embodiment that can be used to understand the automatic gain control features of the receiver of Figure 1; Figure 7 is a part of the receiver of Figure 1 Figure 8 is a schematic block diagram of another specific embodiment; Figure 8 is a schematic diagram showing the digital signal spectrum at each position of the specific embodiment of Figure 7; = 9 is a schematic diagram of a second specific implementation of the receiver according to the present invention; and Figure 10 For the example NTSC / PAL decoder which can be used in Figure q-Y-Y receiving 1 § the description of the preferred embodiment exemplified, the receiver includes a-tuner section, where received information containing predetermined information

V. Description of the invention (4) The ja number and a round of step-out strikes / such resources as the video-stomach and / or audio source 'segment and output configuration; Located in the tuner area, as a signal received from (rf), it contains predetermined information and is modulated on the dish receiver. Once there is a signal,-cable TV system, system,-satellite or "digital receiver", Quantong or Wei | Converter for disc receiver Computer or other source: r machine, -video disc or laser disc drive'-device, flat panel display, electric; H set includes the polaritron tube 'projection display information and any Simplicity 2: Set up a monitor and other devices to display video and reproduce audio information. Every 15 to multi-channel digital audio system configuration in the example receiver in Figure 1, the receiver receives three bands of information. TV receiver 10, its tuner 20 and receiver integrated circuit 100; ^^^ at input 12, Via the regulator No. 20 at its output terminal 14. Select these signals, and provide an output mode and features, one of the audio I receive the message, and the video display button or rotary controller, keyboard = letter, the processing is received by the user by pressing whether to receive On the controller or on the remote control: Enter the poor information selection, regardless of the button source. This selection information is received from a computer or other control signal to be sent to the receiver 10, including the user controller 50, and is distributed to the receiver integrated circuit. Two standard signaling control buses. Tuner 20 includes three frequency band sections for parallel signal engines. Each signal path is used to roughly connect the received RF signal to the signal input terminal 1 2

480833 V. Description of the invention (5) Schematic display shows that the RF switch SW1A selects the slave under the control of the receiving self-selection band selection signal, * receives the frequency of the integrated circuit 1 0 0, such as FET or PIN diode n / link. Although SW1A can be used as a true switch for μ switch, for example, "three selectors," a harmonic circuit ‘: using other appropriately configured tuning circuits, each frequency is exhausted.-The signal is broken into three frequency bands.

In the electricity, broadcast signal path-processing. For example, use low VHF frequency bands (such as TV and radio to broadcast in two discrete frequency bands, in other words, frequency bands (such as television, μ; 5 4-8 8 MHz) to broadcast, high VHF AV, Lerutun video force 7-13 to 2 7 _: broadcast ί = Ι; then through a wide frequency band, such as 5'-Broadcast, it can be divided into adjacent bands for processing within the receiving region.

Is the RF signal in the Ushi band (including the broadcast UHF TV band) on loan? Low miscellaneous flood amplifier = amplifier 24, the amplifier responds to automatic gain control (AGC) signal = provides gain that can be controlled in the range of about 20 dB, and is added to υΗρ variable resistance tuning 1§ 22, which is tuned to select the upper frequency band And UHF band signals, as well as channel selection signals from the receiving integrated circuit 丨 〇〇 down-convert the frequency of these signals, such as about 334-9 10 million MHz (MHZ) with about 20-30 Megahertz bandwidth. The down-converted up-band signal from the spectrum tuner 22 is applied to the upper-band input terminal 102 of the receiver integrated circuit 100. In the same way, the RF signal in the middle frequency band (including the VHF television band on the broadcast) is amplified by the vHF low noise amplifier 34, which provides a gain that can be controlled in the range of about 20 dB in response to the AGC signal, and added to the VHF rheostat tuner 32. , Which is tuned to select a mid-band signal, and down-converts the frequency of these signals in response to a channel selection signal from the receiver integrated circuit 100, such as about

Page 10 480833 V. Description of the invention (6)

\ 38 —33 4 Megahertz (MHZ) with about 20-30 Megahertz bandwidth. The down-converted IF signal (including the broadcast high VHF signal) from the tuner 32 is applied to the mid-band input of the receiver integrated circuit 100. In the same way, radio frequency signals in the low frequency band (including signals in the broadcast low VHF TV frequency band) are amplified by the vhf and the noise amplifier 44, which provides a gain that can be controlled in the range of about 20 dB in response to the AGC signal, and is added to the v HF Rheostat tuner 4 2. The tuner selects a low-band signal in response to the channel selection signal from the receiver integrated circuit 100 being tuned, and down-converts the frequency of this signal, for example, about 57-138 (MHZ) million. The frequency band is about 20-30 million Hz. From the tuner

The down-converted low-band signal of 4 2 is additionally applied to the low-band input terminal 106 of the receiver integrated circuit.

The receiver integrated circuit 100 includes an input circuit, which is schematically shown as a ⑽ switch S W1 B ′, which is selectively connected to the selected one of the RF wheel input terminals 1 0 z, 1 0 4, 1 〇6 under the control of a band selection signal to Mixer 1 1 〇, the frequency band selection signal is the same as the RF switch SW 丨 A used to select the tuner 20, so the tuner / amplifier 22-24, 32-34 or 42-44 receives the signal from The RF signal from the input terminal 12 is provided in response to this, and a signal is provided to the mixer of the receiver integrated circuit 100 via the RF switch SW 1 B. The mixer 1 jade 〇 converts the frequency of the signal received from the switch SW 1 B to a predetermined frequency, for example, about 20 MHz, and has high image rejection. In other words, the mixer preferably provides image exclusion of a predetermined signal of at least 30 decibels, such as various sums and differences that occur in the frequency of the mixed signal. Low-pass filter 丨 2 〇 Passes a signal within a predetermined signal bandwidth from the mixer 丨 丨 0, such as a signal at about 20-30 MHz bandwidth (including receiver intermediate frequency (IF)), and Attenuation ratio of about 20_3 () MHz &

Page 11 480833 V. Description of the invention (7) Frequency higher than the above. Although SW1 B can be a true switch, such as a FET or PIN diode switch configuration, other suitable configurations are also available. For example, a balanced converter tuning circuit includes combining input signals from multiple sources into one signal and adding it to the image. Exclude the tuning circuit of the mixer. In addition, instead of the switch S W1 B ', three image exclusion mixers are provided, each receiving an input signal from an individual tuner / amplifier 22/24, 32/34 or 42/44, and providing an output signal to a low-pass Filter 1 2 0. As only one of the three mixers 1 1 0 is used at any time 'the other two mixers are switched off, for example by removing the bias potential to switch off' or by driving the mixer to the point where little or no input signal is passed through it The output is switched off under conditions. The IF signal from the low-pass filter 1 2 0 is an analog L number containing predetermined information. It is oversampled and converted from a wide-band analog to digital converter (ADC) to a digital format signal. The ADC is preferably 1 0. Bit ADCs operate at a sampling rate of about 80-100 MHz, that is, about 80-100 million sample conversions per second, such as a sequential continuous approximation (SSA) ADC. Because the ADC 130 has a low-pass filter 120 in front, the low-pass filter strongly attenuates signals whose frequency is more than half of the sampling rate, so that the digital data words generated by the ADC 130 can be avoided. In this way, the digital output from ADC 130 is a ten-bit data word stream at a data word rate of 80 to 100 million per second, which represents the information contained in the received RF signal. The digital data words from ADC 1 30 accept digital multiplication, digital filtering, and demodulation ^ to recover the information contained therein. In particular, each digital multiplier 14 (), 150 receives a ten-bit digital data word at its first input, and

Page 12 480833

Frequency receiving single-frequency sine and cosine sine song 绫 ^ ^ Bing Meng green raised digits are shown in their individual inputs 亦, that is, the phase one from the numerically controlled oscillators 142, 152: f sine curve < "compliance Phase "m" orthogonal "notation. : Missing f digital vibrator 丨 42, 152 can be provided in several other forms, but the regularized digital representation of the better frequency sine curve is stored in the addressable two-body (ROM), which is the same data rate from the ROM at the same data rate Periodically read items ^ j The data rate is the same as the digital data word by ADC 13〇, which is the rate of "lookup table" ~ lean device 140, 150. Corresponding to the complete sine curve of 36. ^ Multiply by a while

The rate at which the sine curve value is generated by the ROM determines the "frequency, and positive rate" of the sine curve, and is different from the data rate at which a particular value is generated. For example, if every microsecond, a set of 360 corresponding to a sine curve is generated. The sinusoidal value of = the frequency of the sine wave is 10 megahertz, but produces a certain value of data, and a nanosecond produces a new value for a data rate of 20 megahertz. ,… mother

In order to reduce the size of the ROM memory required, only 1/4 of the sine curve needs to be stored in the ROM because of the sine-curvature property, that is, sigma /, has 4 times the 1/4 value (one quadrant), with an appropriate angle Definition and #sine curve to define a complete sine curve (four quadrants). In addition, a ROM with a 1/4 value that is changed by 1 can be used to read the sine curves 142 and 152 alternately, one for the sine value and the other for the oscillator The values are latched in two individual latches, one latches the value of the oscillator 42, its output, and one latches the cosine of the oscillator 152. ° Sine value 'The individual output of each digital multiplier 1 4 0, 15 0 is a predetermined intermediate frequency. The intermediate frequency signal is frequency-shifted to a digital signal processing frequency = 仏, such as 20 MHz to Frequency in the 200 MHz range. Tianlai I is convenient

480833 V. Description of the invention (9) The digital data after the individual frequencies of the multipliers 1 40 and 1 50 are transferred to the digital filters 1 4 4 and 1 5 4 for digital filtering respectively. The filters can be any convenient digital filters Configurations, such as FIR, i iR or canonic digital canonical digital wave torch 'and added to a digital-to-analog converter (DAC) and a restructuring filter device 160. Figure 2 shows the characteristics of the amplitude versus frequency of a typical digital wave filter suitable for digital filters 1 4 4 and 1 5 4. The digital filter's cross-passing has extremely flat and uniform characteristics. It is centered at 20 MHz IF 'and attenuates substantially outside the traffic, that is, in the stop band. The ripple of the channel is less than 1 dB, and the stop band is at least 30 dB lower.

Note that the flat passband has extremely sharp cut-off characteristics and a high and uniform attenuation of the frequency band, such as about -4.5 decibels. The flat passband is comparable to the passband obtained from conventional surface acoustic wave (SAW) filters and ceramic filters. The latter two are extremely large and C & B also lacks the tuning capability peculiar to digital filters. This tuning capability can be achieved by changing the various weighting factors and tap coefficients. As mentioned, when down-converted and filtered, the oversampled digital data generated by the ADC 130 provides at least one additional bit resolution, and in some cases more than one additional bit is used to supply the device 160 digital digits. signal.

Note that the advantage of the present invention is that the unique multiplication and filtering processes generate the tenths of the signal, thus providing additional resolution bits. It is further noted that the additional resolution is before the signal is demodulated and the information contained in it is recovered. Another advantage is that it is known from the digital field to use the multiplication mixers 1 40 and 150 for signal interpretation. The reason is that the frequency of the numerically controlled oscillators 142 and 152 is selected, so the digital filter can operate at an appropriate consistent rate and the circuit The complexity and cost are reduced, and the predetermined filtering performance is obtained at the same time.

Page 14 480833 V. Description of the invention (10); Set up 16 complex sets of digital signals from the digital 遽 ancient wave device 144, 154 and the ΪΓ signal, and Ϊ need to obtain a special output frequency, the frequency must be converted into The analog output signal at the intermediate frequency is bad. Its DAC is re-imaged (examples and components of 9 and 9), and it is installed: the binary bisector opens the color TV analog form to generate an analog intermediate frequency signal.::cheng; ^ Group: The signal is converted into a class filter which can be used to improve the analog intermediate frequency 俨. The 2 i filter example (Sln x) / x is converted into an analog signal with the sign of 遽: the received frequency: ί, ί: quasi-IF For example, 43 mHz carries or encodes the data m. ° = integrated circuit 100 uses a built-in circuit to generate the digital circuit functions described herein as two-way work! The complementary metal-oxide semiconductor (CM⑻ method consists of Multi 4: The fan t can be convenient and beneficial at the same time and can meet this demand. Better width = body method function example ^ microprocessor, memory (ROM and RAM), multiplier type a, combiner , Filters, oscillators, etc. are provided by many semiconductor manufacturers that provide integrated power & Set the cast soul. 丨 The circuit configuration provides high image rejection and highly stable and controllable wave characteristics, which eliminates the need for a conventional surface acoustic wave (SAW) filter or other ceramic or filter = It is known that the K 2 t 'SAW filters used in televisions and other receivers are large and expensive, and cannot be manufactured on integrated circuits with digital A slave electronic devices. By the way, there is an example mixer with high image signal exclusion.丨 丨 〇 The configuration is shown in solid

480833

V. Description of the invention (11) 3 A to 3 E. The example mixer 1 10 of FIG. 3A includes a down-conversion mixing circuit 122, which is responsive to receiving information from the tuner 20 via the switch SW1B, and a local oscillation received from the frequency synthesizer 170. ° Generate two t-frequency signals (up and down arrows) and their phases; vertical rotation: that is, orthogonal. One of the intermediate frequency signals is phase-shifted by a phase shifter 24/90. In addition, the combiner 126 combines other intermediate frequency signals to generate an intermediate frequency signal with a substantially attenuated signal frequency at the video signal frequency. The combination of two rotations of 90 ° phase produces a total phase shift of 180 °, and the cancellation of the image signal is generated at the combiner 126, thereby reducing the amplitude of the image signal therein, thereby providing an image with high image signal exclusion such as about 30 decibels or more Excluded mixers 丨 丨 〇. "

Note that a combiner, such as a combiner, can combine signals by adding (adder or adder circuit) or subtracting (differentiating) its value, and select the combined signal according to the specific configuration of the phase shift obtained in the circuit. According to this combiner The associated circuit obtains a specific configuration or a special configuration of the mixed signal to select the plus or minus value, for example, as known in the industry, 'the oscillator frequency is higher or lower than the mixed signal. Figure 3B is a heuristic representative diagram of the mixer 110 with high image signal rejection. In the figure, the input signal from the switch sw 丨 B is added to the multiplication hybrid circuit 114a 11 & b and the cosine phase and the sine phase local oscillator signal c 〇 $

And the individual input terminals of Sln to the other input terminals of the multiplication mixing circuits 1 14a, 1 14b, whose individual outputs are cosine and sine phase signals having a predetermined bandwidth at a second predetermined frequency, for example, about 20 MHz. The phase of one of the quadrature sine and cosine-phase output signals is shifted by a phase shifter 1 2 4 by 90. This produces a net 1 8 0. The phase difference cancels the image signal. Sine- and cosine-phase

480833 V. Description of the invention (12) The phase shift of one of the signals is added to the phase shifter of the combiner 1 2 6 to generate an output signal, wherein the image signal has been substantially attenuated. In addition, as shown in FIG. 3C, the currently preferred mixer 1 10 includes four hybrid circuits 1 1 2 a, 1 1 2 b, 1 1 4 a, and 1 1 4 b which are connected in series / parallel configuration. Two sets of parallel hybrid circuits 1 12a, 1 12b and 1 1 4a, 114b combine their associated local vibration gains is 1 1 1 a, 1 1 1 b and 1 1 5 a, 1 1 5 b, and their associated filter circuits 113a, 113b and 116a, 116b have what is sometimes referred to as Weaver's mixed 1§ form. The information-bearing signal from the tuner 20 is received via the switch sw 丨 β and is applied in parallel to the input terminals of the multiplication hybrid circuit 丨 丨 2a, 丨 丨 2b. The cosine phase and sine phase local oscillator signals cos and sin Wlt from the analog local oscillators 1 1 1 a, 1 丨 1 b are added to the multiplication mixing circuit U2a, 1 12b ^ the other input terminal 'its individual wheel out The end uses the filters 丨 丨 仏 and 丨 i3b to perform band-pass filtering 'to generate individual cosine and sine phase signals having a first predetermined frequency, for example, about 200 megahertz, and a predetermined frequency bandwidth. The band-pass filters 1 1 3a and 1 1 3b can advantageously exclude image signals that are necessarily generated as a result of the non-linear mixing effect of the hybrid circuits 丨 丨 2a, 丨 丨 2b. The two signals are connected in parallel to the multiplication hybrid circuits 丨 丨 4a, 丨 丨 4b and the respective input terminals. The individual cosine phase and sinusoidal phase local killer signals cos ωιΐ and sin ωt from the analog local oscillators ll5a, n5b are respectively applied to the other input terminals of the multiplication and mixing circuit 1 1 4a, 1 1 4b, and their individual output terminals Low-pass filtering is performed by the filters 116a and 116b to generate cosine and sine phase signals with a second predetermined frequency, for example, about 20 megahertz and a predetermined frequency bandwidth. The band-pass filters Is 1 1 6a, 1 1 6b can advantageously exclude image signals that are necessarily generated as a result of the non-linear mixing effect of the hybrid circuits 丨 14a, 丨, and the like. The two signals are, for example, borrowed

$ 17 pages 480833 V. Description of the invention (13) ^ ------ The combiner 1 2 6 combines to generate the intermediate frequency-ADC 130. I type mixer is added to the low-pass filter. 12/30 decibels or more image exclusion / high image signal exclusion, such as the total scheduled image exclusion of about decibels; two devices 1 and 10: so already accounted for about 60 devices 20 rheostat tuner 22 , 32, knife ,, and other images are excluded by tuning. The bandpass and low-pass filters of 4 and 2 are exemplified by a Weaver mixer configuration. The first-local wavelet signal cos' has an input signal at 800 MHz, _Mhz, and is generated in the bandpass. The frequency of the frequency ^ is the signal of the center frequency of 10,000 Hz; and ^ Example 2 of the leather device 1138, U3b

And sin ω2ΐ the frequency fL0: 2 7Γ ω2 is] two local oscillator signals C0S are generated from the example 20 megahertz intermediate frequency signal megahertz (or 220 megahertz) and the low pass filter 1 1 6a, 1 16b bis. Note that the signal amplitude adjustment may include one or two inputs of the combiner 输入 2δ, or both, and / or include failure. Gilbert's mixing element with a wide dynamic frequency and adjustment of the mixer Π 0 and (Gilbert) unit cell analog mixing and frequency translation properties, and adopted here as a mixer 1 1 0 'Figure 3D, Mixers / dividers are analogous to mixers. The combiner / divider 119 stops at its special features; the private path = 'includes a mixture of x ^ x & Rc to split the input signal into a positive phase relationship such as 0. And 90. The two half-power signals of the phase. The two half power signals are mixed with the orthogonal cos and sin ωα signals in the multiplier mixers 11 4a and 11 4b to generate a total of 180. The phase shift is similar to the aforementioned image exclusion mixer, and is used to cancel the image signal when the two signals from the mixer Π 4a, 丨 丨 4b are combined in the combiner 1 2 6.

Page 18 480833 V. Description of the invention (14) Figure 3E shows the digital image signal cancellation mixer circuit, which can also be used in the receiver of Figure 1. Similar to the heuristic embodiment of Figure 3B, from the switch SW1 The input signal of B is added to the multiplier mixers 114a and 114b together with the quadrature local oscillator signal. Instead of the output shown in FIG. 3B, they are combined and then passed through the low-pass filter 120 and ADC 130 of the receiver integrated circuit 100 and multiplied. The outputs of the mixers 1 1 4 a, 1 1 4 b (phase interval g 0) are applied to the individual analog to digital converters 1 3 0 a, 1 3 0 b, and the digital signals are in the digital adder 1 2 6 , Combination. Since A DC 130a and 130b are each sampled at twice the Nyquist frequency of the input signal, the phase interval between consecutive samples is 90 °. The addition delays the digital word stream from one of the ADCs 130a and 130b. One clock cycle 'provides an additional 90. Phase shift, so a total of 180. Phase shift is used to cancel the image signal. The digital signal of the adder 1 26' is equal to the output of the ADC 1 30 'in Figure 1 and is coupled to the subsequent Multipliers 1 4 0, 1 50. Low-pass filtering The devices 1 1 6 a and 1 16 b can be used for each path s in front of the ADC 130 a and 1 30 b to attenuate higher frequency signals from the hybrid circuit 1 1 4a and 1 1 4b. Note that the cosine phase and sine phase of each group are locally vibrated The device signals c 0s ω! 7 and sin t and (303021: and 3: 111021; a set of two analog local oscillators 111a, 111b, and 115a, 115b are shown in Figs. 3B, 3C, 3D, and 3E, For example, 'each group of local oscillators can be implemented as a single oscillator circuit whose output is phase shifted to produce two signals with a relative phase relationship of 90. In addition, multiple sources of local oscillatory signals can be turned to Corresponds to the adjustable analog attenuator and / or the adjustable analog phase-shift network to adjust the amplitude and phase of the local oscillator signal cosi ^ t and sinWit and cosw2t & sin6j2t, and tune or adjust the mixer 1 1 0, 1 1 0，1 1 〇 ，， improve the image if necessary

Page 19 480833

V. Description of Invention (15) Excluded. A convenient circuit for providing quadrature local oscillators cos 00t and singt by shifting the phase of a signal provided by a single oscillator signal is shown schematically in FIG. 4A. ^ The oscillator 11 1 provides a sinusoidal signal, which is phase shifted by the R-C-R-C phase shift network ^ -45. A COSwt signal is generated, and a sin ω t signal is generated by a phase shift of the OR-C-R phase shift network of about +. The superior advantage of this configuration is that by using a testable resistor in one of the two-phase-shift networks and / or the use of a tunable capacitor in another phase-shift network, the c ω s t and si η ω t signals The phase can be adjusted. The external ’debuggable gain circuit A can provide gain or attenuation or both, and can be placed on the path of one or both of the cos ωϋ and sin signals to adjust its 浐 pair amplitude and relative amplitude. This type of adjustment can be used to adjust the mixer ^ = γ0, to increase the amplitude of the predetermined output signal, and to reduce unwanted images. This configuration can be used for all mixers and other 3 ^ positive coS (i) t: & sin6l) t circuits described herein. FIG. 4B is a schematic diagram showing an example adjustment network and a graph of the "J t device 110 'combined with the image failure and adjustment circuit 138 and & 139 as an example. The mixer 110 includes a variable resistor Represents the signal 'integer 118a, or may additionally adjust the signal amplitude 1181) (also

Resistance is shown but shown in dashed lines) and is also controlled by circuit 138. Image failure = The entire circuit 1 38 also controls the phase shift 疋 provided by the variable capacitor C and variable resistor R, and the amplitude adjustment provided by the variable gain block A. For typical adjustment operations, the circuit 138 controls the signal generator 13Θ to be provided at a predetermined input frequency, and then adjusts the phase shift adjustment provided by the variable capacitor C and the variable resistor R, and the variable resistor 118a and the variable gain block. Eight provided amplitude modulation

480833

The predetermined output signal supplied to the ADC 130 is rounded and maximized. Secondly, the circuit controls the signal generator 1 39 to provide a signal at the input terminal, which generates an image "signal frequency output" number, and then adjusts the phase shift adjustment provided by the variable capacitor C and the variable resistor r. 11 8a and the amplitude adjustment provided by the variable gain block A to minimize the output signal of the undesired image signal frequency provided to the ADC 13〇. Thus, the mixer 丨 丨 〇 is adjusted to provide a pre-round signal, Highly excluded with undesired video frequency signals. In addition, although there is only one mixer 1 i ', three mixers and three frequency bands are preferably used. In this case, the switch may be turned on or eliminated.

0 is shown in the receiver integrated circuit for each of the signals from the tuner 2 0. SW 1 B can be a three-monopole single-throw reference picture as described above. The digital frequency synthesizer 170 provides a predetermined local oscillation = frequency f LQ. The signal to the mixer 1 1 0 is used to convert the presentation signal from the tuner 2 0 into an intermediate frequency signal, and is applied to the 0 bit ^ DC 130 through a low-pass filter 20. The digital frequency synthesizer 170 is located in the receiver integrated circuit. The best one includes the digital ring vibrator or the 11 digital type shown in Figure 5. A device that can provide a tweeter of a predetermined frequency over a wide frequency range. In addition, or for the local oscillator inside the mixer 110, it can be sigma 1 type. The control oscillator includes a connection set of voltage controlled oscillators, and y = control signal control. The control signal is the same as the receiver integrated circuit. The "00" series circuit generates a control signal for setting the frequency of the digital frequency synthesizer 70. This type of local oscillator can use voltage-variable capacitance element 2 2 = such as a varistor diode or a switching frequency determining capacitor set as a frequency determining element, or it can be controlled by a control signal. The control signal is the same as the receiving signal. Device

480833 V. Description of the invention (17) The logic circuit of the integrated circuit 100 generates a control signal for setting the frequency of the digital frequency synthesizer 170. Due to the need to down-convert a wide range of input signal frequencies, the local oscillator frequency range is very wide, such as the 5 2-8 8 MHz '174-216 MHz and 470-890 MHz bands of 8 2 channel broadcast television signals Or channel 99 has

The 5 4-6 4 8 MHz range of a wire system makes it impractical to obtain a frequency range from a single oscillator. The digital frequency synthesizer 17o includes a ring oscillator and a phase locked loop (PLL) 172, which includes a complex voltage controlled oscillator (vc0) VC01-VC04, each of which covers a partial range of the local oscillator frequency. The h number responds to the channel selection information contained in the I2 C user control signal, and establishes the divider ratio of the PLL · Equalizer Network 1 74, and selects one of the oscillators VC01-VC04 to operate at any special time. The PLL is completed by loop filtering 176 to precisely control the operation of VC01-VC04. The oscillator is generated ^ The frequency of the oscillator signal is a multiple of the test frequency determined by the divider ratio of the divider network 1 74, so it receives the user-selected Channel signal. The fixed frequency reference oscillator including the integrated circuit of the receiver 100 provides the reference frequency% ^, which is connected to the accurate frequency determined by the crystal 18. < Conversion of I2C data into analog signals may be divided into y and frequency channels and added to the rheostat to a specific rate

Further, the digital-to-analog converter 180 in FIG. 1 converts the decoded user-selected digital information received through the data stream into a band selection signal, which can be divided into discrete types: bits; success; heart signals, each of which controls a Activation of circuits related to a specific frequency band; and ~, the selection signal may be a controlled analog level, such as externally applied to a pole body or other variable resistance element to tune the tuning circuit to the special two to be supplied to the tuner 20. day

Page 22

480833 V. Description of the invention (18) The receiver integrated circuit 1 00 digital to analog converter 1 8 2 responds to the digital AGC control word and provides the analog AGC control signal of the tuner 20, which shares the system gain in the tuner 20 The amplifiers 24, 34, and 44 are in use, and the amplification and / or attenuation is included in the gain control of the receiver integrated circuit 100, as shown in FIG. The preferred gain control is performed in a total range of about 60 decibels, of which the gain control of about 20 decibels is performed by the radio frequency amplifier 2 of the tuner 20,

34, 44, the tuner 20 is usually tied to high gain operation. In addition, the remaining approximately 40 dB increase control range is allocated to approximately 20 dB gain control system just in the input port of the circuit 100 in use! 〇2, 104, and 106, as shown by AGC box 128; and about 20 dB gain control is performed just before ADC 130, as shown by AGC amplifier 132. Note that the AGC amplifier 132 and the amplifier 134 coupled in series with the amplifier 132 just before the input of the ADC 130 each provide a substantial gain, such as about 40 decibels each. Therefore, providing the signal amplitude to a D ^ 1 3 0 can effectively improve its input range. Generally, the gain control first reduces the gain just in front of the ADC 130, then decreases the gain of the input ports 102, 104, 106, and finally reduces the gain of the tuner 20. Such a base AGC function can advantageously use an analog gain control combined with the tuner 20 amplifier and a digital gain control combined with the receiver integrated circuit 丨 〇〇, that is, dual-mode AGC, allowing comparison of single-mode AGC. Quickly adjust system gain with higher accuracy. Figure 7 shows the modified configuration of the digital signal processing in the receiver product of Figure 1. The processed information-bearing signal is used by a class of digits for subsequent use in the digital collar.

The ADC 130 of the body circuit 100 is performed later. As mentioned above, the tuner 20 receiving processing is converted to digital (ADC) 130 into a series of processing, which is marked as a digital section here.

Page 23 480833

1 90. In this example, the ADC 1 30 samples the analog signal at its input. For example, the analog intermediate frequency k has a center frequency of 20 MHz, the sample rate is 75 MHz, the bit segment 190 includes a multiplier mixer 1 40, and has a sine. The digits of the signal are $ as one of its inputs. A sine signal, for example, generates a series of 12-bit coefficients represented by a look-up table stored in memory such as ROM (as described above) is a sine wave. I. Bai Wanhe The digital section 1 90 includes another configuration of the digital filter from FIG. 1, which is illustrated in conjunction with the digital spectrum diagram of FIG. 8. The digital spectrum diagrams A, β, c, ′ D, and E in FIG. 8 correspond to positions a, β, and

C, D, E digital signal spectrum. The digital signal generated by the ADC 130 is presented in the digital spectrum diagram A ', which includes predetermined information carrying the digital signal in a channel, the core frequency of which is 20 MHz, and an undesired channel in its vicinity. In addition, the undesired image of the predetermined signal is centered at 55 MHz with an undesired channel in its vicinity. The digital band-pass filter 9 2 is in front of the multiplier 1 40, and the frequency spectrum of the digital signal imposed on the filter by the band limit carries the digital signal in the predetermined information (centered at 20 MHz).

A preferred embodiment of the digital band-pass filter 192 uses a Gannon Signed Digital (CSD) digital band-pass filter, and more preferably a (2N + 1) tapped symmetrical CSD binomial coefficient filter. The performance of the CS D digital filter (defined by the characteristic ripple of the filter inside the passband of the filter and defined by the filter attenuation of the stopband, that is, outside the passband) is improved with the increase in the number of taps, reaching infinity 'Accuracy' At this time, the terms of the filter equation are implemented. If fewer terms in the filter network are implemented, the accuracy is lower. The following table presents a comparison of the performance of the C S D bandpass filter with the number of taps and the limitation of the number of terms.

Page 24 ^ «0833

Five 'invention description (20)

—— Number of taps Passband Ripple Stopband attenuation Unlimited accuracy CSD 3 items CSD 2 items Unlimited accuracy CSD 2 items N = 70.61 dB 0.64 dB 0.92 dB 31.5 dB 29.5 dB N = 80 0.43 dB 0.45 dB 0.72 dB 36 dB 35 dB N = 9〇0.30 dB 0.32 dB 0.33 dB 40 dB 39 dB N = l〇〇 ----- 0.21 dB 0.24 dB 0.27 Db 42 dB 41 dB The adequate attenuation and ripple of the converter 丨 92 provide the filtering characteristics shown in Figure 2 above, which can be reused more closely = more expensive and larger analog filters that can be achieved by analogous SAW and ceramic filters :: number: spectrogram As shown in Figure B, the predetermined spectrum at 20 MHz is equal to Γ 皮 器 i92 and the channel adjacent to the channel of $$ is excluded. The spectrum diagram is “spectrum multiplied by digits”, 75 hundred

He's predetermined frequency spectrum is 2. Megahertz and 13.: = 2〇: J frequency repeats, that is, 6.25 Megahertz qi 0 Megahertz and frequency and difference

The low-pass transit wave 144 has a cutoff frequency of 1 (million) megahertz repeats. The digital can be connected to the CSD binomial digital filter at 12 points. 3 Hz per Hz = no need to be accurate, and the frequency of the digital signal, so only left and then, only attenuated in a more diffuse quality, as shown in Figure 8 d As shown. The bit k number spectrum is 6 · 2 5 hundred. Finally, the pre-pure bit signal is sampled down by 3 factors. For 胤 m

Page 25 480833 V. Description of the invention (21) 7 The 5 Mhz sampling rate simply discards the intermediate samples by only taking the second sample of every other sample. This down-sampling Yu Sheng takes a frequency of 6.25 Mhz. The spectrum repeats three times that frequency, which is 1 8. 7 5 Mhz, which can be used as the intermediate frequency digital output signal to the receiver of Figure 1. Square Rose 1 6 0. The receiver 10 in FIG. 9 is similar to the receiver 10 in FIG. 1 described above, and each element in FIG. 9 has the same number or text number as the similar element in FIG. Alternative examples are not described here. Components with the same designation but with an apostrophe, such as readers 20 and 20 ', and integrated circuits 100 and 100' are similar, with the following exceptions. The tuner 2 〇 includes the same components of the tuner 20 and performs the same function, but the varistor adjustment | the tuners 2 2, 3 2, 4 2 and the amplifier 2 4, 3, 4, 4 4 are in the order of the tuner of FIG. 9 The 2 0 'three parallel signal paths are reversed, which is a better configuration. Thus, for example, the received UHF band signal is amplified by the low-noise amplifier 24, and then the frequency is changed by the rheostat tuner 22. Similarly, the receiver integrated circuit 100 ′ includes the same components of the receiver integrated circuit 100 and performs the same functions, but the receiver integrated circuit 100 ′ also includes the NTS C / PAL decoder 200, which will be described later. Described. A better ADC 130 has a sampling rate of about 80 megahertz and the signal is oversampled by the filter 120. The output circuit of the receiver integrated circuit 100 'includes a device 160 and an NTSC / PAL decoder 200. In addition, the aforementioned video display device or system 60 and audio reproduction device or system 70 are shown in FIG. The digital-to-analog converter (DAC) and recombination filter device of the receiver integrated circuit 100 ′ processes the composite compliant phase and quadrature digital signals from the digital filters 144, 154, thus generating binary data The word streams, each preferably having 10 to 12 bits, represent the information-bearing signal of the intermediate frequency. Two digits

Page 26 480833 V. Description of the invention (22) The data word stream is added to the NTSC / PAL decoder 2 0 0 to determine the encoding format of the information, that is, the universal NTSC television signal format or the European common PAL (Phase Alternating Line) ) TV signal format. Depending on the situation, after decoding the ^ 3 (: signal or PAL signal, the digital image information is formatted into a digital luminance (luma or "Y") and digital chrominance (chroma or "C") signal, each of which is better It is an 8-bit signal, which is also added to the video display device 60 to display a poor video signal; and a digital audio signal is preferably an 8-bit signal, which is added to the audio device 70 to reproduce sound or audio program information. One of the great advantages is that the information-bearing bandwidth-limiting signal that exists in the IF processing section has been converted to a digital data format by ADC 1 3 0, which has oversampled data and has down-converted the frequency and the digital multiplier. , 150, and digital filters 1 44 and 1 54 for digital signal filtering. ADc 1 = 0 Gastric < Oversampled digital data should be down-converted and filtered as shown ^ 'determined by one extra bit Meta digital signal resolution supply device 丨 60 and NTSC / PAL decoder 2 0. Second, the digital format signal is further processed digitally for signal separation, chroma and brightness filtering, synchronization and sound extraction, and It was then further processed digitally and formatted to display the video Yuxun 2 TV monitor called Guren computer monitor or other display media and technology. All of the foregoing was transmitted in g ^ .. σ ^ The body circuit 100 is performed, and the receiver integrated circuit 100 ′ may be included in + ^ ^ ^ ^ ^ 3. It is used in a television receiver, a computer, a receiver, a modem, or a digital receiver for ππΓΜΓΜ Λ I s Beta or cable TV system, DVD player or PCMCIA card and its μ price award _ Secret 4 Receive plug-in mode of σσ, turtle brain, TV or other devices. Figure 10 is the connection included in Figure 9. You cry and receive the Ιδ integrated circuit 100, the NTSC / pAL solution

480833 V. Description of the invention (23) Schematic block diagram of encoder 2 0 0. The two 10-bit digital data streams representing the composite video baseband signal (CVBS) are applied to the synchronous timing recovery circuit 21 and to the Y / C separation circuit 220. The synchronization and timing recovery circuit 21 decides which signal encoding format, ie, ^% or pAL is used for the received signal, from the received digital data, and extracts the correct timing signal and the correct synchronization signal from the digital data, for example, using digital This encoding format for phase-locked loop (pLL) circuits. These signals include, for example, filtered clock and timing signals for the Y / c separation circuit 22 o and the chroma demodulator 240, and blank, color bursts for the video and audio formatting and conditioning circuit 230. , Vertical synchronization, horizontal synchronization and clock signals. Digital pLL circuit of special circuit 21 provides frame and line synchronization. Circuit 21 can detect various major coding architectures, such as NTSC-N, NTSC-M, PAL ~ B, PAL-D, PAL-G, PAL -H and PAL-I. In this way, the Y / C separation circuit 220 preferably uses a multi-dimensional digital comb filter to directly or through the circuit 160 to separate the luminance digital data (γ) and chrominance digital data from the digital data stream received from the digital filters 144 and ι54. (C). The chrominance digital signal is further decoded by the chrominance demodulator 240 into a color signal component in the —-Q or u-V standard format. The preferred demodulator 24o uses a ten-decimal digital filter. Circuits 21 0, 220, and 24 0 use known standard circuits and techniques to detect, demodulate, and decode NTSC / PAL signals. NTSC / PAL decoder 2 0 0 Formatting and conditioning circuit 23 0 Selects Y and I-Q digital signals or γ and Uv digital signals according to the user instruction selection received through the I2 C user selection signal bus. With digital video data formatted into an appropriate format for video display device 60; and

Page 28 480833 V. Description of the invention (24) The I2C user selects the user select command received by the signal bus to condition these digital signals. Such user choices include image brightness, contrast, color saturation, sharpness, hue and hue (for example), and gamma correction. Preferably, the 8-bit luminance and chrominance digital output from the decoder 2000 is generated by 4 over-sampled luminance signals and 2 over-sampled 2 chrominance signals, occasionally abbreviated as "8-bit 4: 2 · 2 Υ Γ r Γ h I. 8 Fuyuan imu Turen — _ ^ KrLD ”When the digital data is output from the flood wheel, it can generate data at high data rates, such as about 20 to 25 million bytes per second. Rate for example 25 megahertz for the integrated circuit of the timing receiver-^ 11 20 ° ^ ^ ^ ^ t „2 30 ^ ^ " The appropriate format of the digital audio data contained in the digital audio signal of A type A 70 % Qiu Douyi / ^ Sai Songbei is expected to become audio 糸 adjust the tone of these signals. Such user choices include balance and so on ... Emphasis and non-emphasis, loudness between speakers In addition, the format circuit 2 30 also provides some control functions The digital output is _ used in mouth temples, which is not a format, or a television signal coding standard = such as a giant video signal, which is known to suppress a certain value in the turn-in video signal when it exists (VCR). Λ Recorded in the video recorder., Kind; "Integrated Circuit". ". ◦ ’Includes digital PLL and line lock function. 5 / digitize and line up the digital circuit and cry 1 4 η 1/1 further, due to the digital multiplier and pi 4. , 144, 150, 154 digital frequency migration and wave operation results

480833 V. Description of the invention (25) As a result, digital signal processing can be performed on the digital data word, which has more data bits than the input digital data word, and the undesired signal (such as confusion) is removed from the digital data spectrum signal). For example, 8-bit digital data input produces 9-bit or 10-bit digital data words, which are processed by 9-bit or 10-bit digital signal processing circuits to improve resolution and accuracy. Although the present invention has been described with reference to the foregoing specific embodiments, the essence of the present invention and the changes within the scope as defined by the scope of the following patent applications will be apparent to those skilled in the art. For example, although the television receiver is described here, the present invention can also be applied to radios, wireless and cableless communication devices such as portable phones and cellular phones, and other receivers. The special circuit can be implemented in various ways. For example, the switches SW 1 A and SW 1 B can be electromechanical or electronic switches or can be a balance converter or other coupling network. ADC 130 may be embodied as a flash converter, or-delta or (5-sigma converter, continuous approximation converter, or other similar analog-to-digital converter configuration. Further, it is expected to include other characteristic changes. For example, as described herein The digital filter described above is an example, and any digital filter form that provides appropriate performance can be used. In addition, the digital sine wave can be generated by a device other than the memory containing the look-up table, such as a microprocessor, such as a microprocessor. Calculate the sine wave coefficient from the equation, and the memory 1 4 2, 1 5 2 does not need to be a single memory, but can be a combination of coarse and fine memory each containing a portion of each 12-bit or other bit-length coefficient Look up the table.

Page 30

Claims (1)

480833 6. Scope of patent application 1. A receiver 10, comprising: at least one input 槔 (1 2, 1 0 2, 1 0 4, 1 06), where the information bearing signal is received; a mixer (1 1 0 ), Which is coupled to the input port (12, 102, 104, 106) to migrate the frequency of the information-bearing signal; an analog-to-digital converter (1 3 0) is coupled to the mixer (1 1 0 ) For converting the frequency-shifted information-bearing signal into a digital word sequence; a source (142, 152) for digital representation of a sinusoid of a predetermined frequency; a digital multiplier (1 40, 15 0), Light-to-analog-to-digital converter (130) and coupled to source (142, 152) to shift the digital word sequence at a predetermined frequency; a digital filter (144, 154, 192), coupled To the digital multiplier 0 4 0, 15 0), and digitally filter the frequency-shifted digital word sequence; and an output circuit (16 0, 2 0 0), which is coupled to the digital filter to shift the digital The word sequence produces an output signal representing the information. 2 · The receiver according to item 1 of the patent application scope, wherein the mixer (丨 10) includes first and second mixing circuits (112a, U2b, 114a, 114b), each having first and second input terminals and An output terminal, wherein the first input terminals of the first and second hybrid circuits (112a'112b, 114a, 114b) receive the information-bearing signal, and the first and second hybrid circuits (1, 2a, 1 1 2b, 114a, 114b) The second round of the end is assembled to receive the sine and cosine signals at the specified frequency, and the first and second hybrid circuits (n2a, 480833 VI. The patent application scope 112b, 114a, 114b) is coupled to a combiner (126). 3. The receiver according to item 1 of the patent application scope, wherein the output circuit includes a decoder 'for decoding-information bearing signals encoded in at least two different encoding formats. 4 · The receiver (10) as claimed in the first patent application range, wherein the digital filter (144, 154, 192) is a digital band-pass filter (144, 154, 192) with a stop band attenuation of at least 30 dB , And passband ripple of less than 1 dB to provide channel selectivity. 5 · If the receiver (10) of item 1 of the patent application scope further includes a tuner (20) for receiving the information-bearing signal and the additional information-bearing signal to at least one input port (102, 1 〇) 4,101), and at least one of a display device (60) and a sound reproduction device (70). 6. —A receiver integrated circuit (100, 100,), including: at least one mixer (1 1 0), including first and second hybrid circuits (112a, 112b, 1 14a, 11 4b) ), The information-bearing signal is coupled to the hybrid circuits to shift the frequency of the information-bearing signal in response to individual orthogonal components of a first predetermined frequency signal; a combiner (1 2 6) for combining the signals obtained from the first And the frequency-shifting component of the information-bearing signal of the information-bearing signal of the second mixing circuit (112a'112b'114a, 114b), wherein the mixer (1 1 0) and the combiner (1 2 6) can substantially exclude the image of the frequency_ after the frequency shift Frequency signal; 'At least one analog-to-digital converter (130), light-to-mixer (1 1Q) and combiner (1 2 6), used to convert the frequency-shifted information-bearing signal into a sequence Digits; · Page 32 480833 VI. Patent application scope A digital multiplier (1 40, 15 0), which is combined with an analog-to-digital converter (130) and a sinusoidal digital presentation source coupled to the second predetermined frequency (1 4 2,1 5 2) for frequency-shifting the digital word sequence by a second predetermined frequency; and a digital filter and waver (1 4 4, 1 5 4, 1 9 2), which are combined to a digital multiplier, and Digitally filter the frequency-shifted digital word sequence, and provide the filtered digital word to the output 槔 (14, 60, 70). 7 · The receiver integrated circuit (100, 100,) according to item 6 of the patent application, wherein the combiner (126) has individual input terminals coupled to the first and second hybrid circuits (112a '112b 114a, 114b) output terminals, and an input terminal having an output coupled to the analog-to-digital converter (130). 8. The receiver integrated circuit (100, 100,) according to item 6 of the patent application 'wherein the at least one analog-to-digital converter (1 30) includes first and second analog-to-digital conversions Device (1 3 0 a, 1 3 0 b), with its individual input terminals coupled to the output terminals of the first and second hybrid circuits (112a, 112b, 114a, 114b) and its individual wheel output terminals coupled to Individual input terminals of the combiner (丨 2 6). 9 · The receiver integrated circuit (丨 00, 10 G) according to item 6 of the patent application scope, further comprising a decoder (200) for decoding the tribute encoded in at least two different encoding formats Bearer signal. 10. If the receiver integrated circuit (100, 100 ') of item 9 of the patent application scope further includes a digital band-pass filter (192), which is inserted in the analog-to-digital converter (130) and digital multiplication (14, 15), the digital bandpass filter (192) has a stopband attenuation of at least 30 decibels, and less than} decibels. Page 480 833 Page 34