WO2001020792A9

WO2001020792A9 - Integrated receiver with digital signal processing

Info

Publication number: WO2001020792A9
Application number: PCT/US2000/025165
Authority: WO
Inventors: Robert Malkemes
Original assignee: Sarnoff Corp; Robert Malkemes
Priority date: 1999-09-16
Filing date: 2000-09-14
Publication date: 2002-11-21
Also published as: WO2001020792A1; TW480833B

Abstract

A receiver (10), such as a television receiver, includes a tuner (20) and a receiver integrated circuit (100). The receiver integrated circuit (100) includes a high-image rejection mixer (110) and an analog-to-digital converter (ADC) (130) to provide a digital representation of signals received by the tuner (20), which may be in one of several formats, such as an NTSC format or a PAL format. Digital signals from the ADC (130) are digitally down converted (140, 150) and filtered (144, 154, 192) and may be formatted as an intermediate frequency (IF) signal or be decoded into digital video signals for a display device (60) and digital audio signals for an audio reproduction device (70). As a result of the digital frequency conversion, efficient digital filtering is employed in place of conventional bulky and costly SAW filters, and digital words having a greater number of bits than the digital data produced by the ADC (130) are available for digital signal processing.

Description

INTEGRATED RECEIVER WITH DIGITAL SIGNAL PROCESSING

This Application claims the benefit of U.S. Provisional Application Serial Number 60/154,029 filed September 16, 1999.

The present invention relates to a receiver and, in particular, to a receiver including a digital signal processing arrangement.

As television receiver technology has matured and additional features have been added to the product, the problem of how to cram the additional electronic circuitry into the physical product at a cost consumers can afford has been addressed by employing integrated circuit technology. In particular, the circuitry is not on one integrated circuit, but is embodied in a set of a plurality of integrated circuits.

Among the limitations on combining certain functions on an integrated circuit is the compatibility of the particular circuitry utilized in performing such functions and of the integrated circuit process technology required for such circuitry. For example, combining digital circuitry and analog circuitry on the^' same integrated circuit poses one set of problems to be addressed. Combining'high-frequency analog signal processing and wideband digital signal processing presents a different set of problems. Another issue that arises is that the cost increases and the yield of satisfactory devices decreases as the amount of circuitry to be formed on a single integrated circuit increases.

In addition, in conventional receivers, channel selectivity has been done as part of the analog intermediate frequency (IF) processing by utilizing a surface acoustic wave (SAW) or ceramic bandpass filter to select the desired channel IF signal and to reject unwanted adjacent channel signals. But SAW filters and ceramic filters are physically large and are not suitable to be incorporated into an integrated circuit with electronic circuits. In addition, such filters are undesirably expensive.

Accordingly, there is a need for an arrangement for a receiver that is suitable for implementation as an integrated circuit. To this end, the receiver of the present invention comprises at least one input port at which an information-bearing signal is received, a mixer coupled to the input port for shifting the information-bearing signal in frequency, and an analog-to-digital converter coupled to the mixer for converting the frequency-shifted information- bearing signal to a sequence of digital words. A source provides a digital representation of a sinusoid at a predetermined frequency, a digital multiplier is coupled to the analog-to-digital converter and to the source to shift the sequence of digital words by the predetermined frequency, a digital filter is coupled to the digital multiplier to digitally filter the frequency-shifted sequence of digital words, and an output circuit is coupled to the digital filter to produce from the frequency-shifted sequence of digital words an output signal representative of the information. According to another aspect of the present invention, a receiver integrated circuit comprises at least one mixer including first and second mixing circuits to which an information-bearing signal is coupled to for shifting the information-bearing signal in frequency responsive to respective quadrature components of a first predetermined frequency signal, and a combiner for combining frequency shifted components of the information-bearing signals from the first and second mixing circuits, wherein the mixer and the combiner substantially reject signals at image frequencies of the shifted frequency. At least one analog-to-digital converter is coupled to one of the mixer and the combiner for converting the frequency-shifted information-bearing signal to a sequence of digital words. A digital multiplier is coupled to the analog-to-digital converter and to a source of a digital representation of a sinusoid at a second predetermined frequency to shift the sequence of digital words by the second predetermined frequency, and a digital filter coupled to the digital multiplier to digitally filter the frequency-shifted sequence of digital words and to provide filtered digital words at an output port.

BRIEF DESCRIPTION OF THE DRAWING The detailed description of the preferred embodiments of the present invention will be more easily and better understood when read in conjunction with the FIGURES of the Drawing which include: FIGURE 1 is a schematic block diagram of an exemplary embodiment of a receiver including the present invention; FIGURE 2 is an amplitude vs. frequency characteristic associated with the embodiment of FIGURE 1 ;

FIGURES 3A through 3E are schematic block diagrams of exemplary mixers useful in the receiver of FIGURE 1; FIGURE 4A is a schematic diagram of an exemplary phase shifting and amplitude adjusting network for an oscillator useful in the embodiments of FIGURES 1 and 3B-3E;

FIGURE 4B is a schematic diagram of the exemplary adjustment network of FIGURE 4A and the exemplary mixer of FIGURE 3C; FIGURE 5 is a schematic diagram of a ring oscillator useful in the embodiment of FIGURE 1 ;

FIGURE 6 is a schematic diagram of an exemplary embodiment useful in understanding the automatic gain control feature of the receiver of FIGURE 1 ;

FIGURE 7 is a schematic block diagram of an alternative embodiment of a portion of the receiver of FIGURE 1 ;

FIGURE 8 is a diagram representing the frequency spectra of the digital signals at various locations in the embodiment of FIGURE 7;

FIGURE 9 is a schematic block diagram of a second exemplary embodiment of a receiver including the present invention; and FIGURE 10 is a schematic block diagram of an exemplary NTSC/PAL decoder useful in the receiver of FIGURE 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A typical receiver includes a tuner section at which signals containing desired information are received and an output arrangement such as a visual display and/or an audio source at which such information can be perceived or otherwise utilized. Between the tuner section and the output arrangement resides various signal processing apparatus that transforms the received signals into a form or forms that are suitable for use by the output arrangement. In a television receiver, for example, received signals may include radio frequency (RF) signals having the desired information modulated thereon as received from an antenna, a cable television system, a satellite dish receiver, a converter or "set-top box" for a cable television system or a satellite dish receiver, a video recorder, a video disc or laser disk player, a computer, or other source. Output arrangements therefor can include cathode ray tubes, projection displays, flat panel displays, plasma or field effect device displays, and the like for displaying visual information and anything from a simple loudspeaker to a multi-channel digital audio system for reproducing audio information.

In the exemplary receiver of FIGURE 1, for example, television receiver 10, tuner 20 thereof receives information-bearing RF signals in three frequency bands at input 12, processes such signals through tuner 20 and receiver integrated circuit 100, and provides an output signal at its output 14. Selection of the one of the many signals received, as well as the mode and characteristics of the visual display, the audio reproduction, and the signal processing, are selected by a user inputting information via buttons or rotary controls, keypads, and the like, whether on the receiver or on a remote control device therefor, or from a computer or other source of control signals. Such selection information is received by a conventional user control 50 and is distributed within receiver 10, including to receiver integrated circuit 100, via a standard I²C signaling control bus.

Tuner 20 includes three parallel signal paths for generally segmenting the frequency bands in which RF signals are received. Each signal path is selectively connected to the signal input 12 schematically by RF switch SW1A under control of the band select signal received from receiver integrated circuit 100. While SW1A may be an actual switch, such as a FET o r PIN diode switching arrangement, other suitable arrangements may be utilized, for example, a "tri-selector" tuned circuit which includes tuned circuits that segment the input signals into three frequency bands, each of which is processed by one of the three parallel signal paths. For television signals, for example, broadcast television signals are broadcast in three distinct frequency bands, i.e. the low VHF band (e.g., TV channels 2-6 broadcast at 54-88 MHZ), the high VHF band (e.g., TV channels 7-13 broadcast at 174-216 MHZ) and the UHF band (e.g., TV channels 14 - 83 broadcast at 470-890 MHZ). For cable television signals, on the other hand, are broadcast over a broad band of frequencies, such as 54 - 810 MHZ, and may be segmented into adjacent bands in a receiver for purposes of processing.

RF signals in the upper band which includes the broadcast UHF television band are amplified by UHF low-noise amplifier 24, which provides a gain controllable over about a 20 dB range responsive to an automatic gain control (AGC) signal, and applied to UHF varactor tuner 22 which is tuned to select upper band and UHF-band signals and to down-convert such signals in frequency, for example, from about 334-910 megahertz (MHZ) with about 20-30 MHZ bandwidth, responsive to the channel select signal from receiver integrated circuit 100. The down-converted upper-band signals from tuner 22 are applied to upper band input 102 of receiver integrated circuit 100. Similarly, RF signals in the middle band which includes the broadcast upper VHF television band are amplified by VHF low-noise amplifier 34, which provides a gain controllable over about a 20 dB range responsive to an AGC signal, and applied to VHF varactor tuner 32 which is tuned to select middle-band signals and to down-convert such signals in frequency, for example, from about 138-

334 megahertz (MHZ) with about 20-30 MHZ bandwidth, responsive to the channel select signal from receiver integrated circuit 100. The down-converted middle band signals including broadcast high-VHF signals from tuner 32 are applied to middle band input 104 of receiver integrated circuit 100. Similarly again, RF signals in the lower band which includes signals in the broadcast low-VHF television band are amplified by VHF low-noise amplifier 44, which provides a gain controllable over about a 20 dB range responsive to an AGC signal, and applied to VHF varactor tuner 42 which is tuned to select lower-band signals and to down-convert such signals in frequency, for example, from about 57-138 megahertz (MHZ) with about 20-30 MHZ bandwidth, responsive to the channel select signal from receiver integrated circuit

100. The down-converted lower band signals from tuner 42 are applied to lower band input 106 of receiver integrated circuit 100.

Receiver integrated circuit 100 includes an input circuit shown schematically as RF switch SW1B that selectively connects a selected one of the RF inputs 102, 104, 106 to mixer 110 under control of the band select signal as is also utilized to select the corresponding position of RF switch SW1 A of tuner 20 so that a selected one of the tuner/amplifiers 22-24, 32-34, or 42-44, receives RF signals from input 12 and provides a signal responsive thereto through RF switch SW1B to mixer 110 of receiver integrated circuit 100. Mixer 110 converts the frequency of the signal received from switch SW1B to a predetermined frequency, for example, about 20 MHZ, and has high image rejection. I.e., mixer 110 preferably provides at least 30 dB rejection of images of the desired signals, such as occur at the various sums and differences of the frequencies of the signals being mixed. Low pass filter 120 passes signals with in the bandwidth of the desired signals from mixer 110, e.g., signals within a bandwidth of about 20-30 MHZ including the intermediate frequency (IF) of the receiver, and attenuates frequencies higher than the upper frequency of the about

20-30 MHZ bandwidth.

While SW1B may be an actual switch, such as a FET o r PIN diode switching arrangement, other suitable arrangements may be utilized, for example, a balun tuned circuit which includes tuned circuits that combine input signals from plural sources into a signal that is applied to image-rejecting mixer 110. Alternatively, in lieu of switch SW1B, three image-rejecting mixers 110 are provided, each one of which receives an input signal from a respective one of tuner/amplifiers 22/24, 32/34, 42/44 and provides an output signal to low-pass filter 120. Since only one of the three mixers 110 is utilized at any time, the other two mixers 110 are turned off, such as by removing bias potential therefrom or by driving the mixer to a condition where little or none of the input signal thereto passes through to its output.

The IF signal from low pass filter 120, which is an analog signal containing the desired information, is oversampled and converted into a digital format signal by wideband analog-to-digital converter (ADC) 140 which is preferably a ten-bit ADC that operates at a sampling rate of about 80-100 MHZ, i.e. about 80-100 million sampling conversions per second, such as a sequential successive approximation (SSA) ADC. Because ADC 130 is preceded by low-pass filter 120 that strongly attenuates signals at frequencies of one-half the sampling rate and higher, aliasing of the digital data words produced by ADC 130 is avoided. Thus, the digital output from ADC 130 is a stream of ten-bit data words at a rate of 80-100 million data words per second that are representative of the information contained in the received RF signals. Digital data words from ADC 130 are digitally multiplied, digitally filtered and demodulated to recover the information therein. In particular, each of digital multipliers 140, 150 receive the ten-bit digital data words at a first input thereof and receive digital representations of single frequency sine and cosine sinusoidal signals at the same frequency, i.e. "in-phase" and "quadrature" representations of the same single frequency sinusoid, from numerically-controlled oscillators 142, 152, respectively, at their respective other inputs. While each of digital oscillators 142, 152 may be provided in several alternative forms, it is preferred that a normalized digitized representation of a single-frequency sinusoid be stored in an addressable read-only memory (ROM) and that values thereof be read cyclically from the ROM at the same data rate at which the digital data words arrive at multipliers 140, 150 from ADC 130, i.e. as from a "look-up table." The rate at which a set of sinusoid values corresponding to an entire 360° of the sinusoid is produced from the ROM determines the "frequency" of the sinusoid, and is different from the data rate at which particular values are produced. For example, if a set of sinusoid values corresponding to an entire 360° of the sinusoid are produced every 100 nanoseconds, then the frequency of the sine wave is 10 MHZ, although the data rate at which particular values are produced could be to produce a new value every 50 nanoseconds for a data rate of 20 MHZ. In order to reduce the size of the ROM memory required, only one-quarter of the sinusoid need be stored in the ROM due to the four-fold symmetry of the sinusoid, i.e. the values of one quarter of the sinusoid (one quadrant) define, with appropriate angle definition and sign change, the entire sinusoid (four quadrants). Further, one ROM containing the values of one-quarter of a sinusoid could be employed to serve as both controlled oscillators 142 and 152 by being alternately read, once for the sine value and then for the cosine value, and the output thereof latched in two respective latches, one for sine values for oscillator 142 and one for cosine values for oscillator 152.

The respective output of each of digital multipliers 140, 150 is a representation of the desired IF signal that is frequency shifted to a frequency that is appropriate and convenient for digital signal processing, for example, a frequency in the range between 20 MHZ and 200 MHZ. The respective frequency-shifted digital data streams from digital multipliers 140, 150 are digitally filtered in digital filters 144, 154, respectively, which may be any convenient digital filter arrangement, such as a FIR, IIR or canonic signed digit type of digital filter, and are applied to digital-to- analog converter (DAC) and reconstruction filter apparatus 160. FIGURE 2 is an amplitude vs. frequency characteristic for a typical digital filter suitable for digital filters 144, 154. The digital filter has a very flat, uniform characteristic across the passband, which is centered on the IF frequency of 20 MHZ, and substantial attenuation outside of the passband, i.e. in the stopband. Preferably, passband ripple is less than 1 dB and stopband attenuation is at least 30 dB.

It is noted that the flat passband, the very sharp cutoff characteristics and high, uniform attenuation out of band, e.g., about -45 dB, is comparable to that obtainable from conventional surface acoustic wave (SAW) filters and ceramic filters which are bulky and very expensive, and also lack the ability to be tuned inherent in a digital filter that can be achieved by changing the various weighting factors and tap coefficients. The oversampled digital data produced by ADC 130 when down converted and filtered as described provides at least one additional bit of resolution, and in certain cases, more than one additional bit, for the digital signals provided to apparatus 160. It is noted that an advantage of the present invention is that the multiplication and filtering processes inherently produce decimation of the signal, thereby providing additional bits of resolution. It is further noted that the additional resolution obtains prior to the demodulation of the signal to recover the information contained therein. A further advantage obtains from the frequency translation in the digital domain by multiplying mixers^" 140, 150 because the frequency of the numerically-controlled oscillators 142, 152 is selected so that the digital filters can operate at an appropriate rate consistent with reducing circuit complexity and cost and with obtaining the desired filter performance.

Output circuit 160, in particular digital-to analog converter (DAC) and reconstruction filter apparatus 160, recombines the complex in-phase and quadrature digital signals from digital filters 144, 154 and, if necessary to obtain a particular output frequency, frequency shifts such signals to such output frequency before the digital signals are reconverted in to an analog output signal at the IF frequency by the DAC thereof. Apparatus 160 can separate the I and Q components of a color television image signal, for example, and combine the two components and convert the combined signal to analog form to produce the analog IF signal. In addition, filtering, such as a (sin x) / x filter may be employed to improve the fidelity of the information contained in the analog IF signal. Preferably, the output signal is a filtered analog signal containing the information borne by or encoded in the received RF signal converted to a standard IF frequency, e.g., 43 MHZ. Preferably, integrated circuit 100 is fabricated utilizing a fabrication process that can produce both the digital circuit functions described herein and the analog circuit functions described herein in a single monolithic integrated circuit. Complementary metal-oxide semiconductor (CMOS) processes are readily available from many semiconductor manufacturers and satisfy this requirement. Advantageously, a wide variety of circuit functions such as microprocessors, memories (ROM and RAM), multipliers, summers, combiners, filters, oscillators and the like, are available as standard pre-designed circuit blocks from many semiconductor manufacturers that provide integrated circuit foundry fabrication services. The foregoing arrangement provides high image rejection and highly stable and controllable filter characteristics, thereby eliminating the need for a conventional surface-acoustic-wave (SAW) filter or other ceramic filter, as is conventionally utilized in the IF sections of television and other receivers, which SAW filter is large and costly, and is not capable of fabrication on an integrated circuit with digital and analog electronic devices.

Arrangements of exemplary mixers 110 having high image signal rejection are shown in FIGURES 3A through 3E. The exemplary mixer 110 of FIGURE 3A includes a down-converting mixing circuit 122 that receives and is responsive to information bearing signals received from tuner 20 via switch SW1B and the local oscillator signal f_L0 received from frequency synthesizer 170 to produce two intermediate frequency signals (upper and lower arrows) that are rotated from each other by 90° in phase, i.e. are in quadrature. One of the intermediate frequency signals is shifted in phase by 90° by phase shifter 124 and is combined with the other intermediate frequency signal in combiner 126 to produce an intermediate frequency signal having substantially attenuated signals at image signal frequencies. It is the combination of the two phase rotations of 90° each to produce a total phase shift of

180° that produces cancellation of the image signals in combiner 126, thereby to reduce the magnitude of the image signals therein, thereby to provide a mixer 110 having high image signal rejection, for example, image rejection of about 30 dB or more. It is noted that a combiner, such as combiner 126, may combine signals by either adding (a summer or summing circuit) or subtracting (taking the difference of) the values thereof, and is selected to do so in accordance with the particular arrangements for obtaining phase shift in the circuit with which such combiner is associated or the particular arrangements for mixing signals, e.g., whether the local oscillator frequency is at a higher or lower frequency than is the signal being mixed, as is known to one of ordinary skill in the art.

FIGURE 3B is a heuristic representation of a mixer 110 having high image signal rejection. Therein, the application of input signals from switch SW1B to respective inputs of multiplying mixing circuits 114a, 114b and of cosine-phased and sine-phased local oscillator signals cos ω₂t and sin ω₂t to respective other inputs of multiplying mixing circuits 114a, 114b, the respective outputs of which are cosine and sine phased signals at a second predetermined frequency, e.g., about 20 MHZ, having a predetermined bandwidth. One of the quadrature sine- and cosine-phased output signals is shifted in phase by 90° phase shifter 124 to produce a net 180° phase difference for cancellation of image signals. The phase shifted one of the sine- and cosine-phased signals is added to the other one thereof in combiner 126 to produce output signals in which the image signals are substantially attenuated.

Alternatively, a presently preferred mixer 110' shown in FIGURE 3C includes four mixing circuits 112a, 112b, 114a, 114b connected in series/parallel arrangement. The two sets of parallel mixing circuits 112a, 112b and 114a, 114b, in combination with their associated local oscillators Ilia, 111b and 115a, 115b, respectively, and their associated filter circuits 113a, 113b and 116a, 116b, respectively, is of a form sometimes referred to as a Weaver mixer. Information bearing signals from tuner 20 are received via switch SW1B and are applied in parallel to respective inputs of multiplying mixing circuits 112a, 112b. Respective cosine-phased and sine-phased local oscillator signals cos ω_{t and sin ω,t from analog local oscillators I lia, 111b, respectively, are applied to respective other inputs of multiplying mixing circuits 112a, 112b, the respective outputs of which are bandpass filtered by filters 113a and 113b, respectively, to produce respective cosine and sine phased signals at a first predetermined frequency, e.g., about 200 MHZ, having a predetermined bandwidth. Bandpass filters 113a, 113b beneficially reject image signals produced as a necessary result of the non-linear mixing action of mixing circuits 112a, 112b, respectively.

These two signals are in turn applied in parallel to respective inputs of multiplying mixing circuits 114a, 114b. Respective cosine-phased and sine-phased local oscillator signals cos ω,t and sin ω^ from analog local oscillators 115a, 115b, respectively, are applied to respective other inputs of multiplying mixing circuits

114a, 114b, the respective outputs of which are lowpass filtered by filters 116a and 116b, respectively, to produce respective cosine and sine phased signals at a second predetermined frequency, e.g., about 20 MHZ, having a predetermined bandwidth. Bandpass filters 116a, 116b beneficially reject image signals produced as a necessary result of the non-linear mixing action of mixing circuits 114a, 114b, respectively.

These two signals are combined, for example, by combiner 126, to provide an intermediate frequency signal that is applied to lowpass filter 120 and ADC 130. The Weaver-type mixer provides a mixer 110' having high image signal rejection, for example, image rejection of about 30 dB or more, which is a substantial part of the total desired image rejection of about 60 dB, the remainder of which is provided by bandpass and low pass filters in varactor tuners 22, 32, 42 of tuner 20.

In the Weaver mixer arrangement, for example, with an incoming signal at 800 MHZ, the frequency f_LO = 2πω_l of the first local oscillator signals cos ω^ and sin Q[t is 600 MHZ to produce signals at the exemplary 200 MHZ center frequency of bandpass filters 113a, 113b and the frequency f_L0 = 2πω₂ of the second local oscillator signals cos ω₂t and sin ω₂t is 180 MHZ (or 220 MHZ) to produce signals at the exemplary 20 MHZ IF frequency. It is noted that a signal amplitude adjustment may be included in any one or both of lowpass filters 116a, 116b and/or in one or both inputs to combiner 126 to provide for adjustment and nulling of mixer 110'. A Gilbert-cell analog mixer, which has wide dynamic range and symmetrical frequency translation properties, may be employed as the mixing element in mixer 110' as well as in the other analog mixers described herein.

In FIGURE 3D, a hybrid combiner/splitter mixing circuit 110" includes a hybrid combiner/splitter 119 terminated in its characteristic impedance Re to split the input signal into two half-power signals in quadrature phase relationship, e.g., at 0° and 90° phase. These two half-power signals are mixed with quadrature cos ω₂t and sin ω₂t signals in multiplying mixers 114a and 114b, respectively, to produce a total 180° phase shift for cancellation of image signals when the two signals from mixers 114a, 114b are combined in combiner 126, similarly to the previously described image rejecting mixers. FIGURE 3E shows a digital image signal canceling mixer circuit 110'" that may also be employed in the receiver of FIGURE 1. Similarly to the heuristic embodiment of FIGURE 3B, input signals from switch SWIB are applied multiplying mixers 114a, 114b along with quadrature local oscillator signals. Rather than the outputs thereof being combined as in FIGURE 3B and then passed through lowpass filter 120 and ADC 130 of receiver integrated circuit 100, the outputs of multiplying mixers 114a, 114b, which are 90° apart in phase, are applied to respective analog-to- digital converters 130a, 130b and the digital signals therefrom are combined in digital adder 126'. Because ADCs 130a, 130b each sample at twice the Nyquist frequency of their input signals, successive samples are 90° apart in phase and the adding is delayed one clock cycle for the stream of digital words from one of the ADCs 130a,

130b to provide an additional 90° phase shift, thereby to total 180° phase shift for canceling the image signals. The digital signal output of adder 126' is equivalent to the output of ADC 130 of FIGURE 1 and is coupled to subsequent multipliers 140, 150. A lowpass filter 116a, 116b may be utilized in each path prior to ADCs 130a, 130b to attenuate higher frequency signals from mixing circuits 114a, 114b, respectively. It is noted that whereas each set of cosine-phased and sine-phased local oscillator signals cos ω,t and sin ω,t and cos ω₂t and sin ω₂t are illustrated in FIGURES 3B, 3C, 3D and 3E by a set of two analog local oscillators 11 la, 11 lb and 115a, 115b, respectively, each set of local oscillators may be realized by a single oscillator circuit the output of which is phase shifted to produce two signals in 90° relative phase relationship, as described above. In addition, one or more of the local oscillator signal sources may be coupled to a corresponding adjustable analog attenuator and/or adjustable analog phase shifting network for the purpose of adjusting the amplitude and phase of each of the local oscillator signals cos ω,t and sin ω,t and cos ω₂t and sin ω₂t to tune or adjust mixer 110, 110', 110" for improved image rejection, if desired.

One convenient circuit providing quadrature local oscillator signals cos ωt and sin ωt by shifting the phase of the signal provided by a single oscillator circuit is illustrated in the schematic of FIGURE 4A. Oscillator 111 provides a sinusoidal signal that is phase shifted about -45° by the R-C-R-C phase shifting network to produce the cos ωt signal and is phase shifted about +45 ° by the C-R-C-R phase shifting network to produce the sin ωt signal. A further advantage of this arrangement is that by utilizing an adjustable resistor in one of the two phase shifting networks and/or an adjustable capacitor in the other of the phase shifting networks, the phases of both the cos ωt and the sin ωt signals may be adjusted. In addition, an adjustable gain circuit A, which may provide either gain or attenuation or both, may be placed in the path of one or both of the cos ωt and the sin ωt signals to adjust both the absolute and the relative amplitudes thereof. Such adjustment is particularly useful in adjusting the mixer circuit 110 to increase the magnitude of the desired output signal and to reduce the magnitude of the undesired image signals. Such arrangements are useful in all of the mixers and other circuits herein that receive quadrature cos ωt and sin ωt signals.

FIGURE 4B is a schematic diagram showing the exemplary adjustment network of FIGURE 4A and exemplary mixer 110' of FIGURE 3C in conjunction with an image nulling and adjustment circuit 138 and signal generator 139 controlled thereby. Mixer 110' includes a signal amplitude adjustment 118a represented by a variable resistance and may also or alternatively a signal amplitude adjustment 118b also represented by a variable resistance, but shown in phantom, also controlled by circuit 138. Image nulling and adjustment circuit 138 also controls the phase shift adjustments provided by variable capacitance C and variable resistance R, and the amplitude adjustment provided by variable gain block A. In a typical adjustment operation, circuit 138 controls signal generator 139 to provide a signal at the desired input frequency and then adjusts the phase shift adjustments provided by variable capacitance C and variable resistance R, and the amplitude adjustments provided by variable resistance 118a and variable gain block A to maximize the desired output signal provided to ADC 130. Next, circuit 138 controls signal generator 139 to provide a signal at the input that produces an output signal at an image signal frequency and then adjusts the phase shift adjustments provided by variable capacitance C and variable resistance R, and the amplitude adjustments provided by variable resistance 118a and variable gain block A to minimize the undesired output signal at the image signal frequency that would be provided to ADC 130. Thus, mixer 110' is adjusted to provide the desired output signals with high rejection of the undesired image frequency signals.

In addition, although only one mixer 110 is shown in receiver integrated circuit 100, it may be advantageous to employ three such mixers, one for each of the three bands of signals provided from tuner 20, in which case switch SWIB could be three single-pole, single throw switches, or could be eliminated, as described above.

Returning to FIGURE 1, digital frequency synthesizer 170 provides a signal at a predetermined local oscillator frequency f_L0 to mixer 110 for converting the information representative signal from tuner 20 to the intermediate frequency signal applied to 10-bit ADC 130 via low-pass filter 120. Digital frequency synthesizer 170 is located on receiver integrated circuit 100 and preferably includes a digital ring-type oscillator of the sort shown in FIGURE 5 or a type II digital synthesizer which can provide signals at predetermined frequencies over a wide range of frequencies. Alternatively, or for the local oscillators internal to mixer 110, other forms of voltage- controlled oscillators, including tandem sets of voltage -controlled oscillators, may be employed and may be controlled by the same control signals that are produced by logic circuitry on receiver integrated circuit 100 to set the frequency of digital frequency synthesizer 170. Such local oscillators may employ sets or chains of voltage- variable capacitance elements such as varactor diodes or sets of switched frequency determining capacitors as the frequency determining elements which also may be controlled by the same control signals that are produced by logic circuitry on receiver integrated circuit 100 to set the frequency of digital frequency synthesizer 170.

Because the range of local oscillator frequencies necessary to down-convert signals over a wide range of input signal frequencies, e.g., the 54-88 MHZ, 174-216 MHZ and 470-890 MHZ ranges of bands of frequencies of 82-channels of broadcast television signals or the 54-648 MHZ range of a 99-channel cable television system, is very wide, it is impractical to obtain same from a single oscillator. Digital frequency synthesizer 170 includes a ring oscillator and phase-lock loop (PLL) 172 that includes a plurality of voltage-controlled oscillators (VCO) VCO1 - VCO4, each covering a portion of the range of local oscillator frequencies. Control signals responsive to the channel selection information contained in the I²C user control signal establish the divider ratio of PLL divider network 174 and selects the one of oscillators VCO! - VCO4 operates at any particular time. The PLL is completed by loop filter 176 for precisely controlling the frequency of the local oscillator signal produced by the operating one of VCO1 - VCO4 at a multiple of the reference frequency determined by the divider ratio of divider network 174 so that the signal in the channel selected by a user is received. A fixed frequency reference oscillator included in receiver integrated circuit 100 provides the reference frequency signal at a precise frequency determined by crystal 18. Further, digital-to analog converter 180 of FIGURE 1 converts decoded user selection digital information received via the I²C data bus to analog signals that contain band selection signals, which may be distinct analog levels or may be distinct signals that each control activation of circuitry pertaining to a particular band, and channel selection signals, which may be a controlled analog level that is applied, for example, to a varactor diode or other variable reactance element, for tuning a tuned circuit to a particular frequency, provided to tuner 20. Digital-to-analog converter 182 of receiver integrated circuit 100 provides analog AGC control signals for tuner 20 in response to digital AGC control words that apportion system gain between the in-use one of amplifiers 24, 34, 44 of tuner 20 and amplifying and/or attenuating gain controls included in receiver integrated circuit 100, for example, as illustrated in FIGURE 6. It is preferred that gain control be performed over a total range of about 60 dB of gain control of which about 20 dB is performed in RF amplifiers 24, 34, 44 of tuner 20, with tuner 20 generally being operated at high gain. In addition, the remaining about 40 dB of gain control range is apportioned with about 20 dB of gain control being performed immediately following the in-use input port 102, 104, 106 to circuit 100, as represented by AGC block 128, and about 20 dB of gain control being preformed immediately before ADC 130, as represented by AGC amplifier 132. It is noted that AGC amplifier 132 and amplifier 134 coupled in series therewith immediately prior to the input of ADC 130 each provide substantial gain, e.g., about 40 dB each, to provide signal amplitude to ADC 130 that effectively utilizes the input range thereof. In general, the gain control first reduces the gain immediately before ADC 130, then reduces the gain at input ports 102, 104, 106, and lastly reduces the gain of tuner 20. This integrated AGC function advantageously employs a combination of analog gain control in the amplifiers of tuner 20 and of digital gain control in the circuits of receiver integrated circuit 100, i.e. a dual-mode AGC, which permits faster adjustment of the system gain and greater accuracy than could be provided by a single-mode AGC function.

In FIGURE 7 is shown a modified arrangement of the digital signal processing performed subsequent to ADC 130 of receiver integrated circuit 100 of FIGURE 1. As above, tuner 20 receives information-bearing signals that are processed and are converted to a sequence of digital words by analog-to-digital (ADC) 130 for subsequent processing in the digital domain, but here identified as digital section 190. In this example, ADC 130 samples the analog signal at its input, for example, an analog IF signal having a 20 MHZ center frequency, at an exemplary rate of 75 MHZ. Digital section 190 includes multiplying mixer 140 that has as one of its inputs a digital representation of a sine signal produced, for example, a sequence of 12-bit coefficients representing a 13.75 MHZ sine wave from a look up table stored in a memory such as a ROM, as described above.

Digital section 190 includes an alternative arrangement of digital filters from that of FIGURE 1 and is described in conjunction with the digital spectra diagram of FIGURE 8. The digital spectra diagrams A, B, C, D, E of FIGURE 8 correspond to the spectra of the digital signals present at locations A, B, C, D, E, respectively, of digital section 190 of FIGURE 7. Digital signals produced by ADC 130 are represented on digital spectrum diagram A which includes the desired information- bearing digital signal in a channel centered at a frequency of 20 MHZ with undesired channels adjacent thereto. In addition, an undesired image of the desired signal is centered at 55 MHZ with undesired channels adjacent thereto. Digital bandpass filter 192 precedes multiplying mixer 140 to band limit the spectrum of the digital signals applied thereto to that of the desired information-bearing digital signal that is centered at 20 MHZ.

A preferred embodiment of digital bandpass filter 192 employs a canonic signed digit (CSD) digital "bandpass filter, and more preferably a (2N+l)-tap symmetric CSD two-term coefficient filter. The performance of a CSD digital filter, which is defined in terms of the ripple of the filter characteristic within the filter passband and by the filter attenuation in the stopband, i.e. outside the passband, improves as the number of taps is increased, reaching infinite precision where all the terms of the filter equation are implemented and lesser precision where fewer terms are implemented in the filter circuit. The following table presents a comparison of CSD bandpass filter performance as the number of taps is changes and as the number of terms is limited.

A 90-tap two term CSD filter provides sufficient attenuation and ripple as to be satisfactory for bandpass filter 192, providing a filter characteristic as shown in FIGURE 2 above that closely replicated that achievable with the more expensive and bulkier analog SAW and ceramic filters. As shown in the digital spectrum diagram B, the desired spectrum centered at 20 MHZ remains after filtering through bandpass filter 192 which rejects the channels adjacent the desired channel.

Multiplying mixer 140 multiplies the spectrum of spectrum diagram B of FIGURE 8 by a digital 13.75 MHZ sine wave representation to produce the spectra of spectrum diagram C, in which the desired spectrum centered on 20 MHZ is replicated at the sum and difference frequencies of 20 MHZ and 13.75 MHZ, i.e. at 6.25 MHZ and at 31.25 MHZ. Digital lowpass filter 144 has a cutoff frequency of 10 MHZ, which need not be precise and which can be obtained in a 12-tap CSD two term digital filter, to substantially attenuate digital signals at higher frequencies, thereby to leave only the desired digital signal spectrum at 6.25 MHZ as shown in spectrum diagram D of FIGURE 8.

Finally, the desired digital signal is down sampled by a factor of three, which for a 75 MHZ sampling rate of the ADC 130, entails simply passing only every third sample and discarding the intervening samples. This down sampling produces a replica of the spectrum centered at 6.25 MHZ at three times that frequency, i.e. at 18.75 MHZ, which may be utilized as the IF digital output signal to processing block

160 in the receiver of FIGURE 1

Receiver 10' of FIGURE 9 is similar to receiver 10 of FIGURE 1 described above and each element of FIGURE 9 having the same numerical or alphanumerical designation as a like element of FIGURE 1 is identical thereto and is as described above in relation to FIGURE 1, including alternatives thereof, and so will not be again described. Elements having the same designation but with a prime, e.g., tuners 20 and 20' and integrated circuits 100 and 100', are likewise similar except as set forth below. Tuner 20' includes the same elements and performs the same functions as does tuner 20, except that the order of varactor tuners 22, 32, 42 and amplifiers 24, 34, 44, are reversed in each of the three parallel signal paths of tuner 20' of FIGURE 9, which is the preferred arrangement. Thus, for example, a received UHF-band signal is amplified by low noise amplifier 24 and is then translated in frequency by varactor tuner 22. Similarly, receiver integrated circuit 100' includes the same elements and performs the same functions as does receiver integrated circuit 100, except that receiver integrated circuit 100' also includes NTSC/PAL decoder 200 which is described below. It is preferred that the sampling rate of ADC 130 be about 80 MHZ to oversample the signal from filter 120. The output circuit of receiver circuit 100' includes apparatus 160 and NTSC/PAL decoder 200. In addition, a visual display device or system 60 and an audio reproduction device or system 70 as referred to above are shown in FIGURE 9. Digital-to analog converter (DAC) and reconstruction filter apparatus 160 of receiver integrated circuit 100' processes the complex in-phase and quadrature digital signals from digital filters 144, 154 to produce two streams of digital data words, each preferably of 10-12 bits, that represent the information-bearing signals at an intermediate frequency. These two streams of digital data words are applied to an NTSC/PAL decoder 200 which determines the encoding format of the information, i.e whether in the NTSC television signal format common in the United States and Japan or the PAL (phase alternating line) television signal format common in Europe. Following decoding of the NTSC signal or the PAL signal, as the case may be, the digital picture information is formatted into digital luminance (luma or "Y") and digital chrominance (chroma or "C") signals, each preferably an eight-bit signal, that are applied to visual display device 60 to display the visual information, and into digital audio signals, preferably an eight-bit signal, that is applied to audio device 70 to reproduce the sound or audio program information.

A significant advantage of this approach is that the information-bearing, bandwidth-limited signal present in the EF processing section has already been converted into a digital data format by ADC 130, which oversamples the data, and has been down -con verted in frequency and filtered in the digital signal processing performed by digital multipliers 140, 150 and digital filters 144, 154. The oversampled digital data produced by ADC 130 when down converted and filtered as described provides at least one additional bit of resolution for the digital signals provided to apparatus 160 and NTSC/PAL decoder 200. That digital format signal is next further processed digitally for signal separation, chrominance and luminance filtering, synchronization and sound extraction, and thereafter is further digitally processed to be formatted for display of visual information on a television display, personal computer monitor, or other display media and technologies. All of the foregoing is performed on a single receiver integrated circuit 100' that may be included in a television receiver, a computer, a receiver, modem or set-top box as for a satellite or cable television system, a video-disk player, or in a PCMCIA card or other plug-in module for a receiver, a computer, a television or other apparatus.

FIGURE 10 is a schematic block diagram of the NTSC/PAL decoder 200 included in receiver integrated circuit 100' of FIGURE 9. Two streams of ten-bit digital data words representing the composite video baseband signals (CVBS) are applied to synchronization and timing recovery circuit 210 and to Y/C separation circuit 220. Synchronization and timing recovery circuit 210 determines from the received digital data which signal encoding format, NTSC or PAL, is utilized in the received signals and extracts from the digital data the correct system timing signals and correct synchronization signals for such encoding format, for example, by employing digital phase-lock loop (PLL) circuits. These signals include, for example, filter clocking and timing signals for Y/C separation circuit 220 and for chrominance demodulator 240, and blanking, color burst, vertical synchronization, horizontal synchronization and clock signals for video and audio formatting and conditioning circuit 230. In particular, digital PLL circuits of circuit 210 provide frame and line synchronization and circuit 210 can detect various forms of the principal encoding schemes, such as NTSC-N, NTSC-M, PAL-B, PAL-D, PAL-G, PAL-H and PAL-I, for example. Thus, Y/C separation circuit 220 preferably employs a multi-dimensional adaptive digital comb filter to separate the luminance digital data (Y) and chrominance digital data (C) from the two streams of digital data received from digital filters 144, 154, either directly or via circuit 160. The chrominance digital signal is further decoded into color signal components in either the I-Q or the U-V standard format, by chrominance demodulator 240. Preferably, demodulator 240 employs a decimating digital filter. Circuits 210, 220, and 240 may employ known standard circuits and techniques to detect, demodulate and decode the NTSC/PAL signals.

Formatting and conditioning circuit 230 of NTSC/PAL decoder 200 formats the digital video data contained in the Y and I-Q or Y and U-V digital signals into the proper format for video display device 60 as selected by the user commands received via the I²C user selection signal bus and conditions those digital signals in accordance with user selection commands received via the I²C user selection signal bus. Such user selections may include picture brightness, contrast, color saturation, sharpness, hue and tint, for example, as well as gamma correction. Preferably, the eight-bit luminance and chrominance digital outputs from decoder 200 are produced with four times oversampling of the luminance signal and two times oversampling of each of the two chrominance signals, sometimes abbreviated as "8-bit 4:2:2 YCrCb." The eight-bit video output digital data words may be provided at a high data rate, for example, about 20-25 megabytes per second, and a clock signal is provided at a convenient frequency, e.g., 25 MHZ, for clocking other circuits of receiver integrated circuit 100'.

Finally, formatting and conditioning circuit 230 of NTSC/PAL decoder 200 formats the digital audio data contained in the digital audio signals into the proper format for audio system 70 and conditions those digital signals in accordance with user selection commands received via the I²C user selection signal bus. Such user selections may include adjustments of volume, bass and treble emphasis and de- emphasis, loudness balance among various loudspeakers and the like.

In addition, formatting circuit 230 may also provide digital output signals suitable for specialized display formats or for certain control functions, such as for a Macrovision signal, which is a conventional television signal encoding standard for encoding a data value in an incoming video signal that, if present, inhibits certain functions, such as the recording of the video signal on a video cassette recorder (VCR).

It is noted that the apparatus of the present invention provides a receiver integrated circuit 100, 100' that includes digital circuits for all video processing, synchronization and alignment and includes digital PLL and line locking functions.

Further, as a result of the digital frequency shifting and filtering operation of digital multipliers and filters 140, 144, 150, 154, the digital signal processing may operate on digital data words that have a greater number of bits of data than do the input digital data words, while eliminating undesired signals (such as aliasing signals) from the spectra of digital data. For example, eight-bit digital data inputs produce nine-bit or ten-bit digital data words that are processed in nine-bit or ten-bit digital signal processing circuits for increased resolution and accuracy.

While the present invention has been described in terms of the foregoing exemplary embodiments, variations within the scope and spirit of the present invention as defined by the claims following will be apparent to those skilled in the art. For example, while the description herein is in the context of a television receiver, the present invention may be employed in radio receivers, wireless and cordless communication devices such as portable and cellular telephones, and in other receivers. Particular circuits may be implemented in a variety of ways, for example, switches SWl A and SWIB may be electromechanical switches or electronic switches, or may be baluns or other coupling networks. ADC 130 may be implemented as a flash converter, a sigma-delta or delta-sigma converter, a successive approximation converter, or other suitable analog-to-digital converter arrangement.

Further, variations to other features are contemplated. For example, The digital filters described herein are exemplary and any form of digital filter providing suitable performance may be utilized. In addition, the digital sine wave may be produced by other means than the memory 142, 152 containing a look up table as described, such as by a microprocessor calculating sine wave coefficients from an equation, and the memory 142, 152, need not be a single memory, but may be a combination of coarse and fine memories each containing a look up table of a portion of each 12-bit or other bit-length coefficient.

Claims

WHAT IS CLAIMED IS:

1. A receiver (10) comprising: at least one input port (12, 102, 104, 106) at which an information- bearing signal is received; a mixer (110) coupled to said input port (12, 102, 104, 106) for shifting the information-bearing signal in frequency; an analog-to-digital converter (130) coupled to said mixer (110) for converting the frequency-shifted information-bearing signal to a sequence of digital words; a source (142, 152) of a digital representation of a sinusoid at a predetermined frequency; a digital multiplier (140, 150) coupled to said analog-to-digital converter (130) and to said source (142, 152) to shift the sequence of digital words by the predetermined frequency; a digital filter (144, 154, 192) coupled to said digital multiplier (140, 150) to digitally filter the frequency-shifted sequence of digital words; and an output circuit (160, 200) coupled to said digital filter to produce from the frequency-shifted sequence of digital words an output signal representative of the information.

2. The receiver of claim 1 wherein said mixer (110) comprises first and second mixing circuits(l 12a, 112b, 114a, 114b) each having first and second inputs and an output, wherein the first inputs of said first and second mixing circuits (112a, 112b, 114a, 114b) receive the information-bearing signal and the respective second inputs of said first and second mixing circuits (112a, 112b, 114a, 114b) are coupled to receive sine and cosine signals, respectively, at a given frequency, and wherein the outputs of said first and second mixing circuits (112a, 112b, 114a, 114b) are coupled to a combiner (126).

3. The receiver of claim 1 wherein said output circuit includes a decoder for decoding information-bearing signals encoded in at least two different encoding formats.

4. The receiver (10) of claim 1 wherein said digital filter (144, 154, 192) is a digital bandpass filter (144, 154, 192) having a stopband attenuation of at least 30 dB and a passband ripple of less than 1 dB, for providing channel selectivity.

5. The receiver (10) of claim 1 further comprising a tuner (20) for receiving the information-bearing signal and applying the information-bearing signal to said at least one input port (102, 104, 106), and at least one of a display device (60) and sound reproduction device (70).

6. A receiver integrated circuit (100, 100') comprising: at least one mixer (110) including first and second mixing circuits (112a, 112b, 114a, 114b) to which an information-bearing signal is coupled to for shifting the information-bearing signal in frequency responsive to respective quadrature components of a first predetermined frequency signal; a combiner (126) for combining frequency shifted components of the information-bearing signals from the first and second mixing circuits (112a, 112b, 114a, 114b) , wherein said mixer (110) and said combiner (126) substantially reject signals at image frequencies of the shifted frequency; at least one analog-to-digital converter (130) coupled to one of said mixer (110) and said combiner (126) for converting the frequency-shifted information-bearing signal to a sequence of digital words; a digital multiplier (140, 150) coupled to said analog-to-digital converter (130) and to a source (142, 152) of a digital representation of a sinusoid at a second predetermined frequency to shift the sequence of digital words by the second predetermined frequency; a digital filter (144, 154, 192) coupled to said digital multiplier to digitally filter the frequency-shifted sequence of digital words and to provide filtered digital words at an output port (14, 60, 70).

7. The receiver integrated circuit (100, 100') of claim 6 wherein said combiner (126) has respective inputs coupled to outputs of said first and second mixing circuits (112a, 112b, 114a, 114b) and has an output coupled to an input of said analog-to-digital converter (130).

8. The receiver integrated circuit (100, 100') of claim 6 wherein said at least one analog-to-digital converter (130) includes first and second analog to digital converters (130a, 130b) having respective inputs coupled to outputs of said first and second mixing circuits (112a, 112b, 114a, 114b) and having respective outputs coupled to respective inputs of said combiner (126).

9. The receiver integrated circuit (100, 100') of claim 6 further comprising a decoder (200) for decoding information-bearing signals encoded in at least two different encoding formats.

10. The receiver integrated circuit (100, 100') of claim 19 further comprising a digital bandpass filter (192) interposed between said analog-to-digital converter (130) and said digital multiplier (140, 150), said digital bandpass filter (192) having a stopband attenuation of at least 30 dB and a passband ripple of less than 1 dB, for providing channel selectivity.