TW480820B - Charge/discharge circuit enabling fast reaction for energy storage device - Google Patents
Charge/discharge circuit enabling fast reaction for energy storage device Download PDFInfo
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480820480820
本發明係有關於一種充放電電路,尤指可加速儲能元 件反應速率之充放電電路,可藉由一設於放電電路上之電 容於充電過▲程中形成負電位,並於放電過程中以導引放電 電流通過放電電路,而達到迅速完成放電效果者。 、 按’習用利用半導體開關元件所形成之充放電路,如 美國專利第4,754,175號,由](〇5&7&31116七&1.所揭露者The invention relates to a charge and discharge circuit, especially a charge and discharge circuit that can accelerate the reaction rate of an energy storage element. A capacitor provided on the discharge circuit can form a negative potential during the charging process, and during the discharge process Those who guide the discharge current through the discharge circuit to quickly complete the discharge effect. , According to the conventional use of a semiconductor switching element formed charging and discharging circuit, such as U.S. Patent No. 4,754,175, by] (〇5 & 7 & 31116 七 & 1.
「 SOLID STATE RELAY HAVING A THYRISTOR SIDCHARGE CIRCUIT」’其充放電路主要係由複數個二極體及電阻元 件所構成’於其充電過程中,為使充電電流快速導引而減 低漏電狀況,故其電阻必須選用較大數值者;而當於放電: 過程時’卻因為較大之電阻無法讓放電電流快速導流,以 致於無法達到迅速放電之效果。反之,若選用數值較小之 電阻’雖可達到迅速放電之功效,但在充電過程中,卻容 易發生所謂之漏電現象而降低充電速度,故電阻材質之選 用往往困擾電路設計者。 另外,習用充放電路使用過多之元件組成,徒增製程 之困難度。再者,由於其充放電路係設計以接地電位來作 為放電時之最低電位,因此其放電速率有一定之限制,難 以提升其放電效果。 為此’有另一種習用充放電路被予以應用,如第1圖 所示,係為美國專利第4, 931,656號,由EhaIt et al.所 揭露者「MEANS TO DYNAMICALLY DISCHARGE A CAPACTITI VELY CHARGED ELECTRICAL DEVICE」,其充放電電路主要 係由一電阻40、NPN電晶體44及一感光二極體42所組成,"SOLID STATE RELAY HAVING A THYRISTOR SIDCHARGE CIRCUIT" "The charging and discharging circuit is mainly composed of a plurality of diodes and resistance elements." During its charging process, in order to quickly charge the charging current and reduce the leakage condition, its resistance A larger value must be selected; when discharging: the discharge current cannot be conducted quickly because of the large resistance, so that the effect of rapid discharge cannot be achieved. Conversely, if a resistor with a smaller value is selected, the effect of rapid discharge can be achieved, but during the charging process, the so-called leakage phenomenon is likely to occur and the charging speed is reduced. Therefore, the choice of the resistance material often troubles the circuit designer. In addition, the conventional charging and discharging circuit is composed of too many components, which increases the difficulty of the process. Furthermore, since the charging and discharging circuit is designed to use the ground potential as the minimum potential during discharge, its discharge rate has a certain limit, and it is difficult to improve its discharge effect. For this purpose, another conventional charging and discharging circuit is applied. As shown in FIG. 1, it is US Patent No. 4,931,656, which is disclosed by EhaIt et al. "MEANS TO DYNAMICALLY DISCHARGE A CAPACTITI VELY CHARGED" ELECTRICAL DEVICE ", its charge and discharge circuit is mainly composed of a resistor 40, NPN transistor 44 and a photodiode 42,
第4頁 480820Page 4 480820
利用感光二極體42來作為電晶體44之開關控制,並藉此以 達到充放電電路規劃之目的。 當發光二極體陣列2 0受到足夠電源驅動而產生光源時 ’將耦合感應另一邊之感光二極體陣列3 〇以產生充電電流 ’此充電電流將依線路^向儲能元件5〇方向流動(如頂^ 之虛線箭頭所示),由於電阻40之阻隔作用而致使大部分 充電電流將依線路C2繼續往儲能元件50 (如本圖所示之^ 效電晶體)方向流動。在此同時,由於感光二極體42亦受 到光耦合感應而產生之電流,並將依線路C3而流向至電晶 體44之射極端E,並致使電晶體44形成斷路關閉狀態,因 此充電電流亦無法經由電晶體44路徑而造成漏電現象,因 此可達到快速充電之目的。 而於放電過程中,感光二極體42因為無光源照射及停 止產生電μ,因此自場效電晶體5 〇所產生之放電電流部分 將依循通過電路D3及電阻46以到達電晶體44之基極端B : 並致使電晶體44之基極B及射極E間導通而形成電晶體44之 集極C及射極E間成為開啟線路,因此大部分放電電流將可 依循線路D1、電晶體44及線路D2而接地達成放電目的。 雖然,上述第二種習用充放電電路具有快速充放電之 功效,但是由於該習用充放電電路4〇還是存在有一電阻46 ,電阻46所產生之缺憾還是無法根本上之有效解決。另外 ,该充放電電路還是以接地零電位為放電電路之最低電位 ’在放電過程中還是有其一定之速率限制。麦是 本發明之主要目的在於提供一種可加逮儲能元件反應The photodiode 42 is used as the switching control of the transistor 44 to achieve the purpose of the charge and discharge circuit planning. When the light-emitting diode array 20 is driven by sufficient power to generate a light source, 'the photodiode array 3 on the other side will be coupled and induced to generate a charging current.' This charging current will flow in the direction of the energy storage element 50 according to the line ^. (As shown by the dotted arrow on top), due to the blocking effect of the resistor 40, most of the charging current will continue to flow in the direction of the energy storage element 50 (such as the effective transistor shown in this figure) according to the line C2. At the same time, since the photodiode 42 is also subjected to the light-induced coupling current, it will flow to the emitter terminal E of the transistor 44 in accordance with the line C3, and cause the transistor 44 to form an open and closed state, so the charging current is also The leakage phenomenon cannot be caused by the transistor 44 path, so the purpose of fast charging can be achieved. During the discharge process, because the photodiode 42 does not irradiate and stops generating electricity μ, the discharge current generated from the field effect transistor 50 will follow through the circuit D3 and the resistor 46 to reach the base of the transistor 44. Extreme B: The base B and the emitter E of the transistor 44 are turned on to form an open circuit between the collector C and the emitter E of the transistor 44. Therefore, most of the discharge current can follow the line D1 and the transistor 44. And the line D2 is grounded to achieve the purpose of discharge. Although the second conventional charging and discharging circuit has the effect of fast charging and discharging, since the conventional charging and discharging circuit 40 still has a resistor 46, the defects generated by the resistor 46 cannot be effectively solved fundamentally. In addition, the charge-discharge circuit still uses the ground zero potential as the minimum potential of the discharge circuit, and it still has a certain rate limit during the discharge process. The main purpose of the present invention is to provide an energy storage element reaction
480820480820
20 發光二極體陣列 40 充放電電路 44電晶體 50 儲能元件 72 外部感光二極體 80 充放電電路 83内部感光二極體 85内部儲能元件 88第二電晶體 感光二極體 電阻 42 46 70 74 82 84 C1 發光二極體 外部儲能元件 ^ —二極體 第—電晶體 8 6 皆一 第一二極體 Q、Dl〜d5線路 % #閱第2圖 係為本發明一 車父佳實施例之充放電電20 Light-emitting diode array 40 Charge and discharge circuit 44 Transistor 50 Energy storage element 72 External photodiode 80 Charge and discharge circuit 83 Internal photodiode 85 Internal energy storage element 88 Second phototransistor photodiode resistance 42 46 70 74 82 84 C1 Light-emitting diode external energy storage element ^ —diode first —transistor 8 6 are all first diode Q, D1 ~ d5 line% #See Figure 2 for a driver of the invention Charge and discharge
第6頁 480820Page 6 480820
五、發明說明(4) 路構造圖;如圖所示,本發明之充放電電路8 〇主要係包括 有一可連接於至少一外部感光二極體72之第一二極體82、 一連接於第一二極體82輸出端之第一電晶體84 (如本實施 例之PNP電晶體)、一連接於至少一内部感光二極體μ之内 部儲能元件8 5 (如本實施例之電容)、一連接於内部儲能 元件85之第二電晶體88 (如本實施例之ΝΡΝ電晶體)及第一 二極體86。其中,ρνρ電晶體84之射極端Ε係連接於第_二 極體82之輸出端,其基極端Β可連接於外部感光二極體 及ΝΡΝ電晶體88之集極端C’ ,而集極端C則連接於νρν電晶 體88之基極端Β,,電容85之一端除了可連接於ΝΡν電晶^ 88之射極端Ε’外,亦可連接於第二二極體86之輸入端,而 第二二極體86之輸出端則連接於ΝΡΝ電晶體88之基極端Β, 於充電過程中,至少一發光二極體7〇受到足夠電源之 供應而產生照射光源,並耦合外部感光二極體7 2形成一充 電電流’充電電流將循線路C1往第一二極體82及線路C3流 動,此時由於第一二極體82所造成之壓降效應,致使ρΝρ 電晶體84之射極端Ε電位低於基極端B.電位,因此形成ρΝρ 電晶體84為斷路關閉狀態。於此同時,由於内部感光二極 體83亦受到發光二極體70之光源照射形成一電流\並依循 線路C4而流向可為電容、M0S場效電晶體、或絕緣閘雙極 一極體(IGBT)所構成之内部儲能元件85,並致使電容85於 連接ΝΡΝ電晶體88之一端形成比接地零電位還低之負電位 。而ΝΡΝ電晶體88之基極端Β’電位受到第二二極體86之壓V. Description of the invention (4) Circuit structure diagram; as shown in the figure, the charge-discharge circuit 8 of the present invention mainly includes a first diode 82 which can be connected to at least one external photodiode 72, and one connected to The first transistor 84 (such as the PNP transistor of this embodiment) at the output end of the first diode 82, and an internal energy storage element 8 5 (such as the capacitor of this embodiment) connected to at least one internal photodiode μ ), A second transistor 88 (such as the NPN transistor of this embodiment) and a first diode 86 connected to the internal energy storage element 85. Among them, the emitter terminal E of the ρνρ transistor 84 is connected to the output terminal of the _diode 82, and its base terminal B can be connected to the external pole C 'of the external photodiode and the NP transistor 88, and the extreme terminal C Then it is connected to the base terminal B of the νρν transistor 88. In addition to one terminal of the capacitor 85, it can be connected to the input terminal E ′ of the NPν transistor ^ 88, and it can also be connected to the input terminal of the second diode 86. The output terminal of the diode 86 is connected to the base terminal B of the NPN transistor 88. During the charging process, at least one light-emitting diode 70 is supplied with sufficient power to generate an illumination light source, and is coupled to an external photodiode 7 2 to form a charging current. The charging current will flow through the line C1 to the first diode 82 and the line C3. At this time, due to the voltage drop effect caused by the first diode 82, the radiated extreme E potential of the ρΝρ transistor 84 is caused. The B. potential is lower than the base terminal, so that the ρNρ transistor 84 is formed in an open state. At the same time, since the internal photodiode 83 is also illuminated by the light source of the light-emitting diode 70 to form a current \ and follow the line C4, the current can be a capacitor, a MOS field-effect transistor, or an insulated gate bipolar monopole ( The internal energy storage element 85 composed of IGBT) causes the capacitor 85 to form a negative potential lower than the ground zero potential at one end connected to the NPN transistor 88. And the base terminal B ′ potential of the PN transistor 88 is pressed by the second diode 86
1 _1 _
480820480820
降影響勢將形成比其射極端E’電 NPN電晶體88為斷路關閉狀態。在潰電晶體8此也= =同,關閉之其情況下,充電電流將繼續依循;路 C2而迅速抵達外部儲能元件74 ’以完成未增加漏電路徑之 情況下快速充電目的。 ^ ^ ’於放電過程中,外部儲能元件74所釋放出之放 電電流受到第一二極體82之阻隔將依循線路D1流向PNP電 晶體84之射極端e,由於PNp電晶體84之射極端E電位高於 其基極端B電位,因此也將導通其射極£與基極B間之線路 、集極C與基極b間之線路而致使pNp電晶體84成為通路 開啟狀癌’並讓部分放電電流經由線路D3流向NpN電晶體 88之基極端B’ 。NPN電晶體88受到放電電流之影響,基極 端B’電位將高於射極端E,電位,因此將依序導通射極£,與 基極B ’間之線路、集極C,與基極B,間之線路而致使NPN 電晶體8 8亦成為通路開啟狀態。受到比接地零電位還低之 電容85負電位影響,放電電流將可快速被導引通過pNp電 晶體84、線路D4、NPN電晶體88及線路D5而至電容85,藉 此完成快速放電之目的。 由於,本發明於放電電路中所固設之内部儲能元件85 負電位影響,其可讓放電電流流過之速率相較於習用以接 地電位為放電電路最低電位之設計明顯有較佳之導引效果 ’因此其放電電流之放電功效可優於習用電路構造。 再者,本發明由於係利用電晶體及二極體之搭配設計 ’完全捨棄習用電阻元件之應用,因此亦可避免電阻元件The NPN transistor 88 will be in an off-closed state than its emitter E 'transistor. When the transistor 8 is broken, the charging current will continue to follow when it is turned off; the circuit C2 will quickly reach the external energy storage element 74 'to complete the fast charging purpose without increasing the leakage path. ^ ^ 'During the discharge process, the discharge current released by the external energy storage element 74 is blocked by the first diode 82 and will follow the line D1 to the emitter terminal e of the PNP transistor 84, because the emitter terminal of the PNp transistor 84 The E potential is higher than the base potential B, so it will also turn on the line between the emitter and the base B, and the line between the collector C and the base b, causing the pNp transistor 84 to become a path-opening cancer. Partial discharge current flows to the base terminal B ′ of the NpN transistor 88 through the line D3. The NPN transistor 88 is affected by the discharge current. The potential at the base terminal B 'will be higher than the potential at the emitter terminal E, so the emitter will be turned on in sequence, the line between the base terminal B', the collector C, and the base B. The intermediate circuit causes the NPN transistor 88 to also become a path open state. Affected by the negative potential of the capacitor 85 which is lower than the ground zero potential, the discharge current can be quickly guided through the pNp transistor 84, line D4, NPN transistor 88 and line D5 to the capacitor 85, thereby achieving the purpose of fast discharge. . Due to the negative potential effect of the internal energy storage element 85 which is fixed in the discharge circuit of the present invention, the rate at which the discharge current can flow is obviously better than that of the conventional design in which the ground potential is the lowest potential of the discharge circuit. Effect 'Therefore, the discharge efficiency of the discharge current can be better than the conventional circuit structure. Furthermore, the present invention uses a combination design of a transistor and a diode to completely abandon the application of a conventional resistance element, so the resistance element can also be avoided.
480820480820
7帶來之設計缺憾。當然,本發明之内部儲能元件只 加f放電功效,而在另一實施例中亦可捨棄内部儲能元 元全以二極體及電晶體之搭配,同樣亦可達到改Μ φ 阻元件使用之缺憾。 又。電 另外,外部感光二極體72及内部感光二極體83亦可 ”、、同一感光二極體陣列,只是該感光二極體陣列係分為上 下二個不同驅動之方向陣列,上端之感光二極體在^光感 應時將向上流動,而下端之感光二極體則在受光 ^ ^ 下流動。 兀為應時向 加速儲 電路上 以導引 者。不 未有之 合專利 貴審查 惟 之較佳 精神作 上所述, 能元件反 之電容於 放電電流 僅具有實 新設計, 法發明之 委員詳予 以上所述 實施範例 成各種變 本發明 應速率 充電過 通過放 用功效 其所具 要件, 審查, 之内容 ,大凡 化和修 係有關 之充放 程中形 電電路 ,並為 有新穎 爰法具 並祈早 與所舉 知悉此 飾,仍 於一種充放電電路 電電路,可 成負電位, ,而達到迅 技術思想兩 性與進步性 文申請發明 曰賜准專利 實施例之圖 技藝之人士 應包括在本 藉由一 並於放 速完成 度之發 之增進 專利。 ,至感 示,僅 ’依照 案之專 設於放電 電過程中 放電效果 明及前所 ’完全符 為此謹 德便。 係本發明 本發明之 利範圍内7 design flaws. Of course, the internal energy storage element of the present invention only adds f discharge effect, and in another embodiment, the internal energy storage element can be discarded with a combination of a diode and a transistor, and the same can be achieved by changing the M φ resistance element. Regrets to use. also. In addition, the external photodiode 72 and the internal photodiode 83 may also be used. The same photodiode array is provided, but the photodiode array is divided into two different driving direction arrays. The diode will flow upward when light is sensed, and the photodiode at the lower end will flow under light ^ ^. It should be a guide to the accelerating storage circuit at the appropriate time. It is not unreasonable that the patent is expensive. The better spirit is described above. On the contrary, the capacitor can only have a real new design for the discharge current. The members of the French invention have detailed the above-mentioned implementation examples into various variations. The present invention should be charged at a rate through discharge and its functions. The contents of the review, generalization and repair are related to the charge and discharge medium-sized electrical circuits. In order to have new tools and pray to learn about this decoration as early as possible, it is still a charge and discharge circuit electrical circuit, which can be negative. Those who have achieved both the technical and gender perspectives and progressiveness of the technical application. Those who apply for the invention of the drawing technique of the patented embodiment should be included in this book. The enhanced patent is issued. It is felt that only ‘the discharge effect in the process of discharge according to the design of the case is exactly the same as the previous one’. It is within the scope of the invention of the present invention.
480820 圖式簡單說明 第1圖:係為一習用充放電電路之構造圖;及 第2圖:係為本發明充放電電路之一較佳實施例構造圖。 第10頁480820 Brief description of the drawings Figure 1: is a structural diagram of a conventional charge and discharge circuit; and Figure 2: is a structural diagram of a preferred embodiment of the charge and discharge circuit of the present invention. Page 10
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EP2276174A3 (en) * | 2001-09-28 | 2012-01-18 | Tai-Her Yang | Transistor photoelectric conversion drive circuit |
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EP2276174A3 (en) * | 2001-09-28 | 2012-01-18 | Tai-Her Yang | Transistor photoelectric conversion drive circuit |
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