480563 B7 五、發明說明（） 發明領域 本發明是有關於一種晶圓的製造方法，且特別是有關 於一種在晶圓表層形成無晶格缺陷主動層的方法。 發明背景 無疑地，半導體技術的蓬勃發展對現今電子相關工業 的快速發展有很大的貢獻。而到目前爲止，矽仍是非常重 要的半導體材料，大部分的半導體元件都是建立在矽晶圚 隨著對半導體元件的集積度之要求越來越高，對晶圓 品質的要求也跟著越來越高。一般來說，只有晶圓表面一 定厚度的部分會被使用來製造半導體積體電路，此一部份 一般稱爲主動層(active layer)。對0.18微米以下的製程來 說，希望主動層之厚度至少有10微米厚，且沒有任何晶 格缺陷與污染物，以使在此區域上所製做出之半導體元件 不會受到不良影響而改變其電氣特性，例如發生漏電流等 之問題。 一般爲了提升半導體元件的良率，對晶圓之要求有良 好的聞氧化層完整性（Gate Oxide Integrity ; GOI)、低p/n 接合漏電流（junction leakage)與足夠的污染物吸附量 (gettering capacity)。其中閘氧化層完整性與p/n接合漏電 流都和晶圓主動層之晶格微粒（Crystal Originated Particle，COP)數量有關。COP數目越多，則閘氧化層完 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝 L--- 1 訂--- ------Γ- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 480563 A7 B7 五、發明說明（） 整性越差，P/η接合漏電流越大。而P/n接合漏電流還和 晶圓主動層之污染物濃度有關，污染物濃度越大’ P/n接 合漏電流也越大。至於晶圓的污染物吸附量越大’則必須 增加晶圓之內部污染物吸附力（Intrinsic Gettering ; IG)。 這些晶圓特性都和晶圓的製造過程息息相關。 以目前製造晶圓的技術來說，可約略分成三大類。在 使用Czochralski (CZ)的方法拉晶完成之後’將晶柱切割 成適當厚度之晶圓，至此是共通的製造程序。接下來，第 一種方法是讓切割後之晶圓經化學機械硏磨法’讓晶圓表 面平坦化而成。第二種方法是在切割下來之晶圓經化學機 械硏磨法處理過後，在晶圓表面生成一層磊晶層（epitaxial layer)。第三種方法是在切割後之晶圓經化學機械硏磨法 處理過後，將晶圓置入爐管（furnace)內，以攝氏上千度的 高溫來進行長時間的回火，使晶圓表面之矽原子可以獲得 足夠之動能來進行晶格重組，讓晶圓之主動層沒有晶格缺 陷。 第一種方法，在晶圓的主動層中易生成晶格缺陷，容 易使半導體元件的電氣特性受到不良影響。第二種方法， 雖然生產出來之晶圓的主動層品質較好，但是在製程進入 0.1微米且使用12吋以上的晶圓時，其品質就不符要求了。 因此以第二種方法所製作出來的晶圓將會是未來主流，唯 一的問題是12吋以上的晶圓在回火過程中，容易因面積 太大而彎曲。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公董） 1丨丨！ II----裝---I L----訂-----II--線Γ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 480563 A7 B7 五、發明說明（） 另外，污染物之來源有兩大類，一類是拉晶時在晶格 缺陷發展過程中沈澱於晶柱內之污染物，例如來自拉晶時 所使用之堪鍋的氧、碳’常會造成晶格空洞的產生與生成 氧化矽或碳化矽的沈澱（泛稱爲巨量微缺陷，Bulk Micro Defect ; BMD)。另一類爲晶圓在進行半導體製程中所接觸 到之污染物，多爲金屬類之污染物，例如銅、鎳、金、鐵。 此類金屬污染物，在適當溫度下可以在矽晶格中擴散相當 長的距離，例如在攝氏900度下，銅可以每分鐘擴散600 微米的距離。因此金屬污染物常會造成半導體元件之嚴重 漏電流的問題，例如上述之p/n接合漏電流，造成必須要 有一個機制來自晶圓主動層中去除這些金屬污染物。 BMD與COP是由晶格空缺(vacancy)所衍生而來的。 若在晶體生長過程中，晶格空缺慢慢長大形成晶格空洞， 即爲COP。若是晶格空缺中有污染物如碳等，則會形成一 個BMD之成核點，若再繼續加入污染物，例如氧，再繼 續生長，則就形成氧化矽之BMD。這兩條生成COP或BMD 之路徑是互相競爭的。 習知發現在拉晶過程中，若是有適當的氧溶解在矽晶 格中，在矽晶圓主動層之下形成一些氧化矽沈澱的話，可 以吸附金屬污染物，使金屬污染物遠離晶圓之主動層。後 來在熔融的多晶矽中加入氮化矽，使晶圓中摻入氮。發現 在晶圓中摻入氮之後，可以有效地增加BMD之濃度至1 X101Q cm·3左右以使晶圓有足夠的內部污染物吸附力將金 4 本k張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ---- -----rl ---I L----訂---II ---- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 480563 A7 B7 五、發明說明（） 屬污染物自晶圓的主動層中移走，同時也使COP之體積 明顯地減少。但是其在爐管內之兩階段回火步驟，在第一 階段回火需在攝氏900度下進行約4小時，第二階段回火 需在攝氏1240度下進行約16小時，若再加上升溫與降溫 的時間，至少要花一天的時間才能完成。 發明目的與槪述 因此本發明的目的之一就是在提供一種在晶圓表層形 成無晶格缺陷主動層的方法。此方法可應用在CZ矽晶圓 的製造上’包括在坩鍋中置入熔融的多晶矽，並在熔融多 晶矽中摻入含鹵素的化合物，此含鹵素化合物所含之鹵素 爲氯、溴或碘。接著進行拉晶步驟，自熔融多晶矽中拉出 一晶柱。然後切割拉出之晶柱以形成多片矽晶圓，再於鈍 氣下，對矽晶圚進行電漿回火步驟。然後使用化學機械硏 磨法來平坦化矽晶圓之表面，使該矽晶圓之主動層沒有晶 格缺陷。 根據上述，本發明以含鹵素化合物來摻雜矽晶圓，並 使用電漿回火法來讓晶圓回火。如此不僅可降低晶圓所需 之回火溫度’還可縮短回火時間，大幅降低生產成本，並 且增加晶Η之污染物吸附力。 圖式之簡單說明 爲讓本發明之上述和其他目的、特徵、和優點能更明 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） n n n n n 1· n n n n n ·»1 n n an n n n 一 δ，· n n IMi ϋ ϋ 1 I (請先閱讀背面之注意事項再填寫本頁) 480563 經濟部智慧財產局員工消費合作社印製 A7 ___B7_ 五、發明說明（） 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1圖係依照本發明一較佳實施例之一種在晶圓表層 形成無晶格缺陷主動層的方法流程圖； 第2圖是拉晶步驟之示意簡圖；以及 第3圖爲成品晶圓之結構剖面圖。 圖式之標記說明 200 :坩鍋 210 :熔融的多晶矽 220 :晶柱 230 :拉晶方向 3〇〇 :晶圓 310 :主動層 320 :沈澱 330 :空洞 發明之詳細說明 請同時參照第1圖與第2圖，第1圖係依照本發明一 較佳實施例之一種在晶圓表層形成無晶格缺陷主動層的方 法流程圖，而第2圖爲拉晶步驟之示意簡圖。 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝---— ----訂---------線 ί (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 480563 A7 B7 五、發明說明（） 首先，以Czochralski的方法進f了拉晶（步驟100)，在 坩鍋200中置入熔融的多晶矽210，並在熔融多晶矽210 中摻入含鹵素的化合物。此含鹵素化合物所含之鹵素（X) 爲氯、溴或碘，例如可爲鹵化矽烷類化合物（SiaXbHJ。鹵 化矽烷類化合物例如可爲氯化矽甲烷（SiClmH4_m)、溴化矽 甲烷（SiBrmH4-m)與碘化矽甲烷（SiImH4-m)。 接著自熔融多晶矽210中沿著拉晶方向230拉出一晶 柱220(步驟11〇)。待晶柱220冷卻後，將其切割成適當厚 度之晶圓（步驟120)。再於鈍氣下’對砂晶圓進行電漿回 火法（步驟130)，在此可使用之鈍氣例如包括有氫氣、氦 氣、氖氣或氬氣。然後使用化學機械硏磨法來平坦化矽晶 圓之表面（步驟140)。 所得之矽晶圓成品的剖面結構圖在第3圖上。在第3 圖上，晶圓300之表層爲主動層310，在主動層內沒有任 何晶格缺陷與污染物。在主動層310之下方，亦即晶圓300 之內部則有許多微小之沈澱物320與晶格空洞330。其中 沈澱物320，亦即一般所稱之BMD ’可以吸附大量在半導 體製程中，晶圓300所接觸之金屬污染物，使其遠離主動 層310,而不會破壞在主動層310上所形成之半導體元件。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。480563 B7 V. INTRODUCTION TO THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a wafer, and more particularly, to a method for forming an active layer without lattice defects on the surface layer of a wafer. BACKGROUND OF THE INVENTION Undoubtedly, the booming development of semiconductor technology has contributed greatly to the rapid development of today's electronics-related industries. So far, silicon is still a very important semiconductor material. Most semiconductor components are built on silicon crystals. As the requirements for the integration of semiconductor components become higher and higher, the requirements for wafer quality have also increased. Come higher. Generally, only a certain thickness of the wafer surface is used to fabricate a semiconductor integrated circuit. This part is generally called an active layer. For processes below 0.18 microns, it is desirable that the thickness of the active layer be at least 10 microns thick, and without any lattice defects and contaminants, so that the semiconductor elements made in this area will not be adversely affected and changed. Its electrical characteristics, such as the problem of leakage current. Generally, in order to improve the yield of semiconductor devices, the requirements of the wafer have good Gate Oxide Integrity (GOI), low p / n junction leakage and sufficient gettering. capacity). The gate oxide layer integrity and p / n junction leakage current are both related to the number of Crystal Originated Particles (COP) in the active layer of the wafer. The greater the number of COPs, the gate oxide layer is completed. 2 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page). Install L --- 1 order --- ------ Γ- Printed by the Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 480563 A7 B7 V. Description of the invention () The worse the integrity, the P / η junction leaks The greater the current. The P / n junction leakage current is also related to the contaminant concentration of the active layer of the wafer. The greater the concentration of the contaminant, the greater the P / n junction leakage current. As for the larger the amount of pollutants adsorbed on the wafer, it is necessary to increase the internal pollutant adsorption force of the wafer (Intrinsic Gettering; IG). These wafer characteristics are closely related to the wafer manufacturing process. According to the current technology for manufacturing wafers, it can be roughly divided into three categories. After the crystal is pulled using the Czochralski (CZ) method, the pillars are cut into wafers of an appropriate thickness. This is the common manufacturing process. Next, the first method is to planarize the wafer surface by chemical mechanical honing. The second method is to form an epitaxial layer on the wafer surface after the cut wafer is processed by chemical mechanical honing. The third method is to place the wafer into a furnace tube after the diced wafer is processed by chemical mechanical honing, and perform a long-term tempering at a temperature of thousands of degrees Celsius to make the wafer The silicon atoms on the surface can obtain enough kinetic energy to perform lattice reorganization, so that the active layer of the wafer is free of lattice defects. The first method is that lattice defects are easily generated in the active layer of the wafer, which easily affects the electrical characteristics of the semiconductor element. The second method, although the quality of the active layer of the produced wafer is good, but when the process enters 0.1 micron and uses a wafer of 12 inches or more, its quality does not meet the requirements. Therefore, the wafer produced by the second method will be the mainstream in the future. The only problem is that during the tempering process, wafers larger than 12 inches are easily bent due to the large area. 3 This paper size applies to China National Standard (CNS) A4 (210 X 297 public directors) 1 丨 丨! II ---- install --- I L ---- order ----- II--line Γ (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 480563 A7 B7 V. Description of the invention (2) In addition, there are two major sources of pollutants. One is the pollutants deposited in the crystal pillars during the development of lattice defects during crystal pulling, such as those from the pot used in crystal pulling. Oxygen and carbon often cause the generation of lattice voids and the precipitation of silicon oxide or silicon carbide (commonly known as Bulk Micro Defect; BMD). The other type is the pollutants that the wafer is exposed to during the semiconductor manufacturing process. Most of them are metal pollutants, such as copper, nickel, gold, and iron. Such metal contaminants can diffuse a considerable distance in the silicon lattice at appropriate temperatures. For example, at 900 degrees Celsius, copper can diffuse a distance of 600 microns per minute. Therefore, metal contamination often causes serious leakage current problems of semiconductor devices, such as the p / n junction leakage current described above, which requires a mechanism to remove these metal contaminants from the active layer of the wafer. BMD and COP are derived from lattice vacancy. If lattice vacancies gradually grow during the crystal growth process to form lattice holes, this is COP. If there are pollutants such as carbon in the lattice vacancies, a nucleation point of BMD will be formed. If further pollutants such as oxygen are added, and then continue to grow, BMD of silicon oxide will be formed. These two paths to COP or BMD are competing with each other. It is known that during the crystal pulling process, if appropriate oxygen is dissolved in the silicon crystal lattice, and some silicon oxide precipitates are formed under the active layer of the silicon wafer, it can adsorb metal contaminants and keep the metal contaminants away from the wafer. Active layer. Subsequently, silicon nitride is added to the molten polycrystalline silicon, so that the wafer is doped with nitrogen. It was found that after doping nitrogen into the wafer, the concentration of BMD can be effectively increased to about 1 X101Q cm · 3 so that the wafer has sufficient internal pollutant adsorption force. The 4 k-size standards of gold are applicable to Chinese National Standards (CNS) A4 specifications (210 X 297 male f ---- ----- rl --- I L ---- order --- II ---- (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 480563 A7 B7 V. Description of the invention () The pollutants are removed from the active layer of the wafer and at the same time the volume of COP is significantly reduced. However, it is in two stages in the furnace tube Tempering step, the first stage of tempering needs to be performed at 900 degrees Celsius for about 4 hours, and the second stage of tempering needs to be performed at 1240 degrees Celsius for about 16 hours. If you add the time of heating and cooling, it will take at least It can be completed in one day. Purpose and description of the invention One of the objectives of the present invention is to provide a method for forming an active layer without lattice defects on the surface of a wafer. This method can be applied to the manufacture of CZ silicon wafers' includes Put molten polycrystalline silicon in the crucible, and dope with halogen in molten polycrystalline silicon The halogen contained in the halogen-containing compound is chlorine, bromine, or iodine. Then, a crystal pulling step is performed to pull out a crystal pillar from the molten polycrystalline silicon. Then the pulled crystal pillar is cut to form multiple silicon wafers, and then Plasma tempering is performed on the silicon wafer under inert gas. Then chemical mechanical honing is used to planarize the surface of the silicon wafer so that the active layer of the silicon wafer is free of lattice defects. According to the above, the present invention Silicon wafers are doped with halogen-containing compounds, and plasma tempering is used to temper the wafers. This not only reduces the tempering temperature required for the wafers, but also shortens the tempering time and significantly reduces production costs. It also increases the adsorption capacity of the crystallites. The brief description of the drawing is to make the above and other objects, features, and advantages of the present invention clearer. 5 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Love) nnnnn 1 · nnnnn · »1 nn an nnn a δ, · nn IMi ϋ ϋ 1 I (Please read the notes on the back before filling out this page) 480563 Printed by A7 _B7_ of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The description of the invention () is obvious and easy to understand, and a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: FIG. 1 is a diagram of forming an amorphous layer on a wafer surface according to a preferred embodiment of the present invention. The method flow chart of the active layer of lattice defect; Figure 2 is a schematic diagram of the crystal pulling step; and Figure 3 is a cross-sectional view of the structure of the finished wafer. Marking description of the diagram 200: Crucible 210: Fused polycrystalline silicon 220: Column 230: Crystal pulling direction 300: Wafer 310: Active layer 320: Precipitation 330: Detailed description of the cavity invention Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 1 is a preferred embodiment of the present invention. A flowchart of a method for forming a lattice-free active layer on the surface of a wafer, and FIG. 2 is a schematic diagram of a crystal pulling step. 6 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ----------- install -------- order --------- Line ί (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 480563 A7 B7 V. Description of the invention () First, pull crystals by Czochralski's method (step 100), A molten polycrystalline silicon 210 is placed in the crucible 200, and a halogen-containing compound is doped into the molten polycrystalline silicon 210. The halogen (X) contained in the halogen-containing compound is chlorine, bromine, or iodine, and may be, for example, a halogenated silane compound (SiaXbHJ. The halogenated silane compound may be, for example, chlorosilane (SiCuH4_m), or bromide (SiBrmH4- m) and silicon iodide (SiImH4-m). Next, a crystal pillar 220 is pulled out from the molten polycrystalline silicon 210 along the crystal pulling direction 230 (step 11). After the crystal pillar 220 is cooled, it is cut into an appropriate thickness. Wafer (step 120), and then plasma tempering the sand wafer under inert gas (step 130). The inert gas that can be used here includes hydrogen, helium, neon, or argon. Then chemical mechanical honing is used to planarize the surface of the silicon wafer (step 140). The cross-sectional structure of the finished silicon wafer is shown in Figure 3. On Figure 3, the surface layer of the wafer 300 is the active layer. 310, there are no lattice defects and contaminants in the active layer. Below the active layer 310, that is, inside the wafer 300, there are many tiny precipitates 320 and lattice voids 330. Among them, the precipitate 320, that is, The so-called BMD 'can adsorb a large amount of The contacting of the metal contaminants 300, away from the active layer 310, without damaging the semiconductor element is formed on the active layer 310. From the above embodiment of the present invention, the preferred embodiment, application of the present invention has the following advantages.
1.使用架取代氮化矽做爲矽晶圓之摻雜 物。利用氯、溴、碘與矽之鍵結較弱，以有效地減少COP 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----I-----I i I-----；----^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 480563 五、發明說明（） 之體積，並降低後續所需之回火溫度與回火時間。 2·使用含鹵素化合物來取代氮化矽做爲矽晶圓之摻雜 物，能在晶圓內部產生大量之BMD，使晶圓具有良好之 內部污染物吸附力。 3·有效地減少COP的體積之後，則可以有效地提升閘 氧化層之完整性’以減少閘氧化層之漏電流，並可提升閘 氧化層之崩潰電壓。 4·晶圓所需之回火時間與回火溫度減少之後，再加上 使甩電漿回火法而不是爐管回火法，可以大幅降低生產時 間與生產成本。例如以爐管來回火約需1天的時間才能完 成，若以一次200片晶圓來計算的話，每片所需時間約爲 7.2分鐘。若是使用電漿回火法的話，雖然一次只能處理 一片晶圓，但是每片所需的回火時間不到1分鐘。 5·使用電漿回火法，因爲所需回火的時間短，所以即 使是12吋以上的晶圓，也不會有因長時間受熱而軟化彎 曲之問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------!裝----l·---訂---------線 (請先閱讀背面之注意事項再填寫本頁)1. Use a shelf instead of silicon nitride as a dopant for silicon wafers. Use of weaker bonds between chlorine, bromine, iodine and silicon to effectively reduce COP 7 This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) ----- I ----- I i I -----; ---- ^ --------- ^ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 480563 V. The invention explains the volume of () and reduces the subsequent tempering temperature and tempering time. 2. Use halogen-containing compounds instead of silicon nitride as dopants for silicon wafers, which can generate a large amount of BMD inside the wafer, and make the wafer have good internal pollutant adsorption. 3. After the volume of the COP is effectively reduced, the integrity of the gate oxide layer can be effectively improved to reduce leakage current of the gate oxide layer and increase the breakdown voltage of the gate oxide layer. 4. After reducing the tempering time and tempering temperature of the wafer, coupled with the plasma tempering method instead of the furnace tube tempering method, the production time and production cost can be greatly reduced. For example, it takes about one day to complete the furnace fire. If 200 wafers are used for calculation, the time required for each wafer is about 7.2 minutes. If plasma tempering is used, although only one wafer can be processed at a time, the tempering time required for each wafer is less than 1 minute. 5. Using the plasma tempering method, because the time required for tempering is short, even if the wafer is more than 12 inches, there is no problem of softening and bending due to prolonged heating. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -----------! Packing ---- l · --- Order ------- --Line (Please read the notes on the back before filling this page)