JP2007073594A - Method of manufacturing epitaxial silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce generation of epitaxial defect without addition of new heat treatment process and change in the condition of heat treatment. <P>SOLUTION: The entire surface of a silicon wafer obtained from the nitrogen-doped silicon single crystal is etched in the depth of 4 to 15 nm, an epitaxial layer is grown on the same silicon wafer surface. The doped nitrogen concentration is in the range of 0.5×10<SP>13</SP>atom/cm<SP>3</SP>to 3×10<SP>15</SP>atom/cm<SP>3</SP>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an epitaxial silicon wafer used in a highly integrated device for semiconductors. More particularly, the present invention relates to an epitaxial silicon wafer manufacturing method in which an epitaxial layer is grown on a silicon wafer obtained from a nitrogen-doped silicon single crystal.

  Conventionally, a silicon wafer used as a substrate of a highly integrated device is processed from a silicon single crystal grown by the Czochralski method (hereinafter referred to as “CZ method”). In the CZ method, a silicon polycrystal filled in a crucible composed of an inner quartz container and an outer graphite container is heated and melted with a heater, and a seed crystal is immersed in the surface of the melt. This is a method for growing a single crystal by growing it while rotating it and pulling it upward. The silicon wafer grown by the CZ method includes minute cavity defects that are generated by agglomeration of point defects (vacancies) introduced excessively during crystal growth. When this cavity defect is exposed on the wafer surface by polishing, it becomes a minute pit. The pits exposed on the wafer surface are detected as minute defects by a laser particle counter and are called particles caused by crystals (hereinafter referred to as “COP”).

Since this COP lowers the device yield, it is necessary to reduce the COP density (the number of COPs per unit area) of the wafer. Further, even if a microcavity defect that is not exposed on the wafer surface is present in the device active region near the wafer surface, the device characteristics are deteriorated. For this reason, in a silicon wafer wafer used as a highly integrated device, it is necessary to reduce not only the COP detected on the surface but also the density of microcavity defects existing in the device active region near the wafer surface.
On the other hand, when a silicon single crystal is grown by the CZ method, it is recognized that there exists a temperature region (around 1100 ° C.) where a microcavity defect is formed. For this reason, in order to reduce the cavity defect formed in the wafer, a method of gradually cooling this temperature region is performed. However, when this slow cooling method is adopted, the number of defects per unit volume can be reduced, but the size of individual cavity defects is enlarged. Recently, when the miniaturization of the pattern size is promoted with the progress of the high integration of the device, the size of the COP and the microcavity defect cannot be ignored, and the COP and the microcavity defect are formed on the surface and the device active region. A wafer that does not exist is required.

In response to such a demand, an epitaxial wafer in which an epitaxial layer having almost no COP or microcavity defect is grown on the wafer has been developed as a state-of-the-art device substrate, and is likely to be used in many highly integrated devices. It has become. However, even if an epitaxial wafer having few defects and high crystal integrity is used, device characteristics are deteriorated due to contamination of the epitaxial layer by metal impurities in the subsequent device process.
Such contamination by impurities of metal-based elements becomes more complicated as the density of device integration increases, increasing the opportunity and impact. The elimination of metal contamination is basically the process environment and the cleaning of the materials used, but it is difficult to completely eliminate metal contamination in the device process, and it is important to develop gettering technology as a countermeasure. . This gettering technique is a means for trapping an impurity element that has entered due to contamination in a place (sink) outside the device active region and detoxifying it in the device active region.

The gettering technology is called intrinsic gettering (hereinafter referred to as “IG”), which captures impurity elements using oxygen precipitates that are naturally induced during the heat treatment of the device process. There is something. However, when a high temperature heat treatment at 1050 ° C. to 1200 ° C. is performed on the wafer in the epitaxial process, oxygen precipitate nuclei existing in the wafer cut out from the silicon single crystal are reduced and disappear, and in the subsequent device process, It becomes difficult to sufficiently induce oxygen precipitates serving as gettering sources. For this reason, even if this gettering technique is applied, there arises a problem that a sufficient IG effect cannot be expected for metal impurities throughout the entire process.
Conventionally, in order to solve such problems, silicon is doped with nitrogen when growing a single crystal by the CZ method, and forms oxygen precipitate nuclei inside the wafer that are not easily lost even by high-temperature heat treatment performed in an epitaxial process. A method for producing a single crystal has been proposed (see, for example, Patent Documents 1 and 2). That is, according to the proposed manufacturing method, the thermal stability of the oxygen precipitation nuclei in the crystal is increased by doping and growing nitrogen by the CZ method, and the oxygen precipitation nuclei are reduced and disappeared even by the epitaxial process. It is said that it will be possible to build a silicon wafer that does not.
JP-A-11-189493 (specifications [0009] to [0011], FIG. 1) JP 2000-44389 A (specifications [0012], FIG. 1)

However, the epitaxial layer formed on the wafer surface does not have any defects, but defects such as stacking faults and dislocations, that is, epitaxial defects exist in the epitaxial layer. In order to reduce this epitaxial defect, although the method proposed above discloses that a high-temperature heat treatment is performed for a short time in a hydrogen atmosphere or an inert gas atmosphere before the epitaxial treatment, the epitaxial defect is removed by the high-temperature heat treatment. In order to reduce the temperature, it is necessary to perform heat treatment at a higher temperature or for a longer time than conventionally employed hydrogen bake. Further, when such a heat treatment condition is applied to the wafer, a new problem arises in that the wafer is slipped by a high temperature heat treatment or the throughput is lowered by a long time heat treatment.
An object of the present invention is to provide an epitaxial silicon wafer manufacturing method capable of reducing the occurrence of epitaxial defects without adding a new heat treatment process or changing heat treatment conditions.

According to the first aspect of the present invention, the entire surface of the silicon wafer is etched in the cleaning process from the mirror surface processing of the silicon wafer cut out from the silicon single crystal doped with nitrogen to before the epitaxial process, and then epitaxially formed on the silicon wafer surface. An epitaxial silicon wafer manufacturing method for growing layers.
The invention according to claim 2 is the invention according to claim 1, characterized in that the etching amount of the entire surface of the silicon wafer is 4 to 15 nm.
As a result of investigating the cause of epitaxial defects while changing the conditions for doping nitrogen and the epitaxial processing conditions by the CZ method, the present inventors have found that silicon doped with nitrogen as proved in Examples described later. It has been clarified that the generation of epitaxial defects can be reduced by controlling the etching amount on the surface side in the cleaning process from mirror processing to pre-epitaxial process of a silicon wafer cut out from a single crystal. Therefore, in the method for manufacturing an epitaxial silicon wafer according to the first aspect, the generation of epitaxial defects can be suppressed by etching the surface of the silicon wafer before epitaxial growth. Then, by setting the etching amount to 4 to 15 nm, it is possible to provide a high-quality epitaxial wafer with few epitaxial defects without adding a new heat treatment process or changing the heat treatment conditions in the epitaxial process. it can.

Invention is an invention according to claim 1 or 2, the etching is, row by cleaning liquid or SC1 cleaning solution by a single alternating supply of the HF solution and O ₃ aqueous mixture feed or HF solution and O ₃ water according to claim 3 It is characterized by being.
In the method for manufacturing an epitaxial silicon wafer according to the third aspect, the cleaning liquid can remove the surface thickness of the wafer by 4 to 15 nm without deteriorating the flatness and cleanliness of the wafer.

The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the doped nitrogen concentration is 0.5 × 10 ¹³ atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ . It is characterized by being.
In this epitaxial silicon wafer manufacturing method, oxygen precipitation nuclei that serve as gettering sources can be effectively ensured.

According to the method for producing an epitaxial silicon wafer of the present invention, even an epitaxial wafer made from a silicon single crystal grown by doping nitrogen is etched by 4 nm or more on the surface of the silicon wafer before epitaxial growth. The generation of epitaxial defects can be suppressed. That is, it is possible to provide a high-quality epitaxial wafer with few occurrences of epitaxial defects without adding a new heat treatment process or changing heat treatment conditions in the epitaxial process. Then, etching is, if to be performed by the cleaning liquid or SC1 cleaning solution by a single alternating supply of the mixed feed or HF solution and O ₃ water solution of HF and O ₃ aqueous solution, without deteriorating the flatness and cleanness of the silicon wafer When the surface thickness of the wafer can be removed by 4 to 15 nm and the doped nitrogen concentration is 0.5 × 10 ¹³ atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ , it becomes a gettering source. Oxygen precipitation nuclei can be effectively secured.

Next, the best mode for carrying out the present invention will be described.
The method for producing an epitaxial silicon wafer of the present invention grows a silicon single crystal doped with nitrogen by the CZ method, and in the cleaning process from the mirror processing of the silicon wafer cut out from the silicon single crystal to before the epitaxial process. After etching the entire surface by 4 nm or more, an epitaxial layer is grown on the wafer surface. The nitrogen doping method employed in the present invention may be any method as long as it can dope a required concentration of nitrogen, for example, mixing of nitride into the raw material or melt, nitrogen into the furnace or Single crystal growth with flowing nitrogen compound gas, spraying of nitrogen or nitrogen compound gas onto polycrystalline silicon at a high temperature before melting, use of a crucible made of nitride, and the like can be mentioned. In any case, the concentration of nitrogen doped in the crystal can be adjusted by adjusting the amount of nitride, the concentration of nitrogen gas, or the spraying time thereof.

During the growth by the CZ method, the silicon single crystal is doped with nitrogen to promote the condensation of oxygen in the crystal, increase the density of oxygen precipitation nuclei, and increase the thermal stability. For this reason, it is desirable that the concentration of nitrogen to be doped be in the range of 0.5 × 10 ¹³ atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ . As a result, the thermal stability of the oxygen precipitation nuclei can be ensured. When the doping nitrogen concentration is smaller than 0.5 × 10 ¹³ atoms / cm ³ , the formation of oxygen precipitation nuclei is not promoted, whereas when the nitrogen concentration exceeds 5 × 10 ¹⁵ atoms / cm ³ , There is a problem that the single crystal is dislocated. Here, a more preferable range of the nitrogen concentration to be doped is 0.8 × 10 ¹³ atoms / cm ³ to 1 × 10 ¹⁴ atoms / cm ³ .
A silicon single crystal grown by the CZ method is processed into a wafer according to a normal method. For example, after outer periphery grinding and orientation flat processing, it is sliced with an inner peripheral saw or wire saw, chamfered, lapped, then subjected to chemical etching to remove the work-affected layer, and further polished to an optical gloss It is finished to a mirror surface wafer.

  The characteristic point of the present invention is that an epitaxial layer is grown on the surface of the silicon wafer after etching the surface of the silicon wafer finished by mirror polishing in this manner by 4 nm or more. Here, the purpose of etching is to remove COP that is exposed on the wafer surface by polishing and causes epitaxial defects. For this purpose, this etching must be carried out immediately before the epitaxial growth. If this etching is less than 4 nm, COP that causes epitaxial defects cannot be sufficiently removed. A preferable range of this etching is 4 nm or more and 15 nm or less. Even if etching is performed beyond 15 nm, COP that causes epitaxial defects cannot be further removed. A more preferable range of this etching is 6 nm or more and 10 nm or less.

The surface of the silicon wafer is preferably cleaned by cleaning the surface with a cleaning liquid having an etching effect. Here, examples of the cleaning liquid having an etching effect include a cleaning liquid by mixing supply of HF solution and O ₃ aqueous solution, or a single alternating supply of HF solution and O ₃ water, or SC1 cleaning liquid. The amount of etching differs depending on the cleaning time and the cleaning temperature in the cleaning performed using the cleaning liquid exemplified in these. Therefore, the amount of etching on the silicon wafer surface is controlled by increasing or decreasing the cleaning conditions and the number of times.

Next, examples of the present invention will be described together with comparative examples.
<Example 1>
Nitrogen is doped by the CZ method so that the nitrogen concentration in the crystal is 0.5 × 10 ¹³ atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ , and the oxygen concentration is 13 × 10 ¹⁷ atoms / cm ³ . Two wafers cut from a silicon single crystal and mirror-polished after chamfering, lapping, and chemical etching (hereinafter referred to as “low oxygen concentration wafers”) were prepared.
Separately, nitrogen is doped by the CZ method so that the nitrogen concentration in the crystal is 0.5 × 10 ¹³ atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ , and the oxygen concentration is 15 × Two wafers (hereinafter referred to as “high oxygen concentration wafers”) that were cut out from a silicon single crystal at 10 ¹⁷ atoms / cm ³ and mirror-polished after chamfering, lapping, and chemical etching were prepared.
By controlling the cleaning time of these silicon wafers using SC-1 cleaning liquid having H ₂ O ₂ : NH ₄ OH: H ₂ O = 1: 1: 5 and a cleaning liquid temperature of 70 ° C., the surface of the silicon wafer was reduced to 12 nm. After etching, epitaxial growth was performed. In this manner, each of the four epitaxial silicon wafers obtained by performing the epitaxial process after etching the surface of the silicon wafer by 12 nm in the epitaxial process after the mirror finish was designated as Example 1.

<Example 2>
Two low oxygen concentration wafers identical to Example 1 and two high oxygen concentration wafers identical to Example 1 were prepared.
These mirror-polished silicon wafers were cleaned using an SC-1 cleaning solution having H ₂ O ₂ : NH ₄ OH: H ₂ O = 1: 1: 5 and a cleaning solution temperature of 70 ° C. Thereafter, the surface of the silicon wafer was etched by 7.5 nm by controlling the cleaning time by using a cleaning solution by a mixed supply of an HF solution and an O ₃ aqueous solution, and a cleaning solution by a single alternating supply of HF solution and O ₃ water.
Thereafter, each silicon wafer whose surface was etched was epitaxially grown under the same conditions as in Example 1. In this manner, each of the four epitaxial silicon wafers obtained by performing the epitaxial process after etching the silicon wafer surface by 7.5 nm in the epitaxial process after the mirror finishing was designated as Example 2.

<Comparative Example 1>
Two low oxygen concentration wafers identical to Example 1 and two high oxygen concentration wafers identical to Example 1 were prepared.
These mirror-polished silicon wafers were cleaned using an SC-1 cleaning solution having H ₂ O ₂ : NH ₄ OH: H ₂ O = 1: 1: 5 and a cleaning solution temperature of 70 ° C. Thereafter, the surface of the silicon wafer was etched by 3.5 nm by controlling the cleaning time by using a cleaning solution by a mixed supply of HF solution and O ₃ aqueous solution and a cleaning solution by a single alternate supply of HF solution and O ₃ water.
Thereafter, each silicon wafer whose surface was etched was epitaxially grown under the same conditions as in Example 1. Thus, the four epitaxial silicon wafers obtained by carrying out the epitaxial process after etching the silicon wafer surface by 3.5 nm in the epitaxial process after the mirror finish were used as Comparative Example 1, respectively.

<Comparison test and evaluation>
The epitaxial silicon wafers in Examples 1 and 2 and Comparative Example 1 were measured for the number of epitaxial defects detected on the surface of the epitaxial layer using a surface inspection apparatus.
The results are shown in Table 1, and the relationship between the etching amount and the number of epitaxial defects is shown in FIG.

  As apparent from Table 1 and FIG. 1, in Examples 1 and 2 in which the epitaxial layer is formed after etching the surface of the silicon wafer by 4 nm or more, the number of epitaxial defects is less than 50. Therefore, in the manufacturing method of the present invention in which the epitaxial layer is formed after etching the surface of the silicon wafer by 4 nm or more, the number of epitaxial defects is reduced to less than 50 without adding a new heat treatment process or changing the heat treatment conditions. It can be seen that it can be reduced. On the other hand, Comparative Example 1 in which the etching on the surface of the silicon wafer is less than 4 nm includes those having 50 or more epitaxial defects. This is considered to be due to the fact that COP that causes epitaxial defects cannot be sufficiently removed.

It is a figure which shows the relationship between the etching amount of this invention Example, and the number of epitaxial defects.

Claims (4)

  Epitaxial silicon wafer for growing an epitaxial layer on the silicon wafer surface after etching the entire silicon wafer surface in a cleaning process after mirror processing of the silicon wafer cut out from the silicon single crystal doped with nitrogen and before the epitaxial process Manufacturing method.   The method for producing an epitaxial silicon wafer according to claim 1, wherein an etching amount of the entire surface of the silicon wafer is 4 to 15 nm. The method for producing an epitaxial silicon wafer according to claim 1 or 2, wherein the etching is performed by a cleaning solution or SC1 cleaning solution by a mixed supply of an HF solution and an O ₃ aqueous solution, or a single alternate supply of HF solution and O ₃ water. 4. The method for producing an epitaxial silicon wafer according to claim 1, wherein the doped nitrogen concentration is 0.5 × 10 ¹³ atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ .

Images