TW478146B - Magneto-resistance random access memory array having pseudo spin valve - Google Patents

Abstract

The present invention discloses a magneto-resistance random access memory (MRAM) array having pseudo spin valve; this array comprises: plural pseudo spin valve memory cells having a stack structure; plural parallel, linear bit lines located under plural pseudo spin valve memory cells; and plural word lines comprising continuous segmented line of mutually orthogonal first line, second line and the third line, wherein the first line and the third line are mutually parallel and are orthogonal to the direction of bit line respectively, the second line of plural bit lines are located on top of the spin valve memory cells, and is parallel to the direction of bit line.

Description

478146 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to an array of magneto-resistance memory random access memory (MRAM), and more particularly to an array having a pseudo-like Array of magnetoresistive random access memory (MRAM) of a rotary switch (PSV) -2 Background of the Invention With the half-used area, the cost is early. The solution is that the size of the component that is shrinking is not deeper than one micrometer in ultra-large circuits; for the past few years, in the storage element, the conductor element must be small in order to shrink the space. With the reduction to the range, the accumulation degree of the magnetoresistive elements of the type integrated VLSI) bulk circuit is constantly expanding, and the chip (chip) remains the same, or even shrinks, in order to continue to reduce the trend of the future development of the high-tech industry. Small circuit design rules (designru 1e). Therefore, the area is also based on the circuit design specifications (designru 1 e is the development of semiconductor technology, integrated circuit components, 'sub-micron range. When the semiconductor is continuously reduced to', some problems in process shrinkage have arisen. Electricity, (Very Large Scale Integrated 2 has a large variety of memory types. In recent industry processes, a kind of non-volatile memory access has been developed. Magnetoresistance

Call / 〇 V. Description of the invention (2) Memory random memory (MRAM) is an integrated base memory and has an unlimited memory (DRAM) direction to store data, so it becomes close to the strong magnetic area Recall the body cell. According to this, the random access memory is based on complementary metal. The resistance to random reading and writing times of the magnetoresistance differs from that of the magnetic memory, so it can be kept non-volatile. Magnetism The resistance of the material, one of which is magnetized memory or magnetoresistive random access: MRAM) is a semi-oxidized memory. Its memory cell line holds the array memory of some types of memory cells. The magnetoresistive random conductors and magnets are non-volatile and dynamic. With the information of strong magnetism, the magnetic section of the access area of the memory device can be called magnetic memory. Recorded as magnetization

2. The two main techniques used for magnetoresistive random access memory (MRAM) are pseudo spin switch (p s e ud e s p i n v a 1 v e; PS V) and magnetic tunnel junction (MTJ) methods. The interface between giant magnetoresistance (GMR) and magnetic channels proposed today

The theory of materials gives the potential of magnetoresistive random access memory high speed, low operating voltage and high density. There are two types of strong magnetoresistive (GMR) structures: a spin valve (SV) and a pseudo-spin switch (PSV). In the spin switch memory element, the polarization direction of one magnetization layer (fixed layer) is fixed and the polarization direction of the other magnetization layer (free layer) can be changed. Based on the direction of magnetic polarization associated with the pinned layer. In this architecture, the state of the memory can be determined by comparing the resistance of a GMR storage element with a reference memory cell.

478146 V. Description of the invention (3) The structure similar to a spin switch is composed of two magnetized layers with different thicknesses and a copper layer as an intermediate layer. Due to the anisotropic shape in the sub-micron size, magnetized layers of different thicknesses have different exchange fields (sw i t c h i n g f i e 1 d). At the moment of magnetization, the two magnetized layers can obviously form anti-parallel polarity and parallel polarity, which will generate high resistance and low resistance of the thin film, respectively. A conventional quasi-spin-switched memory cell stores data in two possible polarizations of a thick magnetized layer. By simultaneously implementing an induced current and a negative and a positive finger current (d i g i t c u r r e n t), the bits can be read non-destructively. Selecting the finger current intensity can control the magnitude of the magnetic field generated. The combination of finger current and induced current is sufficient to open a thin magnetized layer, but not enough to open a thick magnetized layer. Figure 1A shows an array of magnetoresistive random access memory (MRAM) cells of a conventional magnetoresistive memory cell. This array contains a set of parallel bit lines 1 1 0 A, 1 1 Ο B on a horizontal plane. The electrical conduction lines of 1 1 0 C are regarded as parallel word lines 1 2 0 A, 1 2 0 B, 1 2 0 C on the other horizontal plane with the other group. The bit lines 1 1 0 A, 1 1 Ο B, 1 1 0 C and the character lines 1 2 0 A, 1 2 Ο B, 1 2 0 C are at a 90-degree angle with each other, so that they go from top to bottom When observed, the two sets of lines are staggered with each other, as shown in Figure 1B. As shown in the first figure C, a memory cell 1 3 0 is located at an intersection in a vertical space where each word line 1 2 0 B and a bit line 1 1 0 C cross each other. The memory cell 130 is a vertical stacking structure, and the vertical stacking structure includes a pseudo-spin switch 140. The pseudo-spin switch 1 40 has a fixed layer 150 with a fixed magnetization direction, a free layer 160 with a changeable magnetization direction, and an intermediate layer 170 between the fixed layer and the free layer.

478146 V. Description of the invention (4) During the operation of the array, the magnetization at the two ends and the corner subsidence is inconsistent, which generates an additional torque to make it easier to reverse the process, so the conversion field is lower. In a quasi-spin switch memory, the magnetization directions of the hard and soft layers must be opposite for read and write operations, respectively. For the read operation, the amplifier is first reset to zero, then an induced current is applied to the active memory bit and the reference bit, and a negative finger current is applied to the active memory bit. When the finger current is converted into the forward direction, the induced current is still saved, and the output of the amplifier is flashing. Therefore, bit data can be measured by detecting changes in the signal strength between the active bit memory cell and the reference memory cell. However, this traditional structure will lead to some problems. The conventional MR-RAM with pseudo-spin switch is composed of two orthogonal bit lines and word lines, as shown in Figure 1B. In the write mode, the bit line and the word line are polarized to a thick magnetization layer between the induced fields. Therefore, a stronger induced magnetic field is needed to form a magnetoresistance, that is, the conventional MR-RAM with pseudo-spin switches has a smaller magnetoresistance ratio. In addition, a higher write current is also required. Accordingly, only by aligning the magnetic field with the bit line segment can a stronger magnetic resistance be generated. In view of the above reasons, we need a new array of memory cells of magnetoresistive random access memory (MRAM) in order to improve the subsequent

478146 V. Description of the invention (5) Yield and yield of the process. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the conventional method for manufacturing magnetoresistive random access memory (MRAM) has many disadvantages. The present invention provides a method that can be used to overcome the problems in the traditional process. . The main object of the present invention is to provide a method for manufacturing a magnetoresistive random access memory (MRAM). The invention can form a new magnetoresistive random access memory (MRAM) array to replace the traditional structure and obtain a better magnetoresistive reproducibility. Therefore, this method can be applied to deep sub-micron technology of semiconductor elements. Another object of the present invention is to provide a method for forming a memory cell of a magnetoresistive random access memory (MRAM). The method can form a step-shaped word line segment parallel to the bit line at the memory cell of the pseudo-spin switch, so as to obtain a stronger induced magnetic field, that is, the present invention has a larger magnetoresistance ratio. Therefore, the method of the present invention requires only a lower write current. According to this, the present invention can provide a magnetoresistive random access memory with better magnetoresistive reproducibility, so as to increase the yield and yield of the manufacturing process, and thus reduce the cost. Therefore, the method of the present invention can meet economic benefits.

478146 V. Description of the invention (6)-According to the above-mentioned purpose, the present invention discloses a new array of magnetoresistive random access memory (MR AM) with a spin switch. The array includes: a plurality of pseudo spin-switch memory cells (pse ud0 spinva 1 ve) with a stack structure, the stack structure is composed of a pinned layer, an interlayer And a free layer; on a horizontal plane, it is regarded as a parallel electric conduction line of a plurality of bit lines, wherein the plurality of bit lines are straight lines and are located in a plurality of spin switch memories Under the fixed layer of the cell; and on the other horizontal plane as a plurality of character lines (parallel electrically conductive lines of w0r (jiine), where 'the plurality of character lines are all including orthogonal The concatenation of the first straight line, the second straight line, and the third straight line = two mutually parallel first and third straight lines are orthogonal to the direction of one bit respectively, and the second straight line of a plurality of character lines is located in a plurality of switch memories Above the free layer of the cell, and increase the magnetoresistance ratio (magnetresis1; ance rati〇) with respect to the direction of the bit line. .. .. Detailed description of the invention of 5-4: The direction of the present invention is one Array. $ Can be thoroughly Understand the detailed steps for accessing memory in this issue. Obviously, the special details familiar to those skilled in the art in the description of column I of the present invention, ^ = are limited to the semiconductor process steps and are not described in detail to avoid: :::, Known to avoid Xe cost invention is unnecessary

478146 V. Description of the invention (7) Restrictions. The preferred embodiments of the present invention will be described in detail as follows. However, in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. . Referring to the second figure, in a first embodiment of the present invention, a pseudo-spin switch valve 210 having a stack structure is first provided. The stack structure includes at least one Pinned 1 ayer 220 of multi-layer magnetized material (such as Ni, Co, Fe alloy), where the polarization direction of the fixed layer 22 0 is consistent and fixed • One is located at the fixed layer 2 2 0 The upper interlayer 230, wherein the material of the intermediate layer 230 includes at least one metal material (for example, copper material); and the intermediate layer 230 has a multilayer magnetization material (such as Ni, C). , Fe alloy). Free layer 240, wherein the free layer 240 has a variable polarization direction.

On the horizontal plane of the fixed layer 2 2 0, a first electrically conductive line 2 50 is located below the fixed layer 2 2 0, wherein the first electrically conductive line 2 50 includes at least one bit line and the first electrically conductive line 2 50 is a line parallel to the quasi-spin switch memory cell 2 1 0. On the horizontal plane of the free layer 2 40, a second electrical conduction line 2 60 is located above the free layer 2 40. The second electrically conductive line 2 6 0 includes at least one word line and the second electrically conductive line 2 60 is a first line segment 2 7 0 A, a second line segment 2 7 0 B, and a third line segment 2 including successive connections. 7 0 C continuous polyline (for example, zigzag), where 'di first line Ί and 2 7 0 A and second line segment 2 7 0 C are parallel to each other and the first line segment 2 7 0 A

Page 10 478146 V. Description of the invention (8) The third line segment 2 7 0 C is intersected with the direction of the first electrical conduction line 2 50 respectively, and the second line segment 2 7 〇 B is located in the spin switch memory cell 2 Above the free layer 2 0 of 10, and parallel to the direction of the first electrical conduction line 250, the magnetic resistance ratio (magnetresi stance ratio) can be increased by referring to Figures 3A and 3B. In a second embodiment of the present invention, a plurality of bit lines 3 1 0 parallel to each other are first provided on a first horizontal plane, wherein the plurality of bit lines 3 1 0 are straight lines parallel to each other. Then, a plurality of quasi-spin-like switch memory cells 3 2 0 having a stack structure are formed on the plurality of bit lines 3 1 0, and each quasi-spin-like switch memory cell 3 2 0 includes at least: A fixed layer 3 3 0 on the bit line 3 1 0, wherein the 'solid-layer 3 3 0' has a multilayer magnetization material (such as Ni, Co, Fe alloy), and the fixed layer 33 0 has a uniform and fixed polarization direction Unchanged; an intermediate layer 340 formed on the solid layer 3 3 0, wherein the material of the intermediate layer 340 includes at least one copper material; a free layer 3 5 0 formed on the intermediate layer 3 4 0, Among them, the free layer 350 has a multilayer magnetization material (such as Ni, Co, Fe alloy), and the free layer 350 has a variable polarization direction. After that, on a second horizontal plane, a plurality of word lines 3 6 0 are formed on a plurality of quasi-spin switch memory cells 3 2 0 of a free layer 3 5 0, where each word line 3 6 0 System is a stepped continuous polyline, which is formed by the first, second, and third line segments 3 7 0a and 3 7 0B that are orthogonal to each other. 0 A is orthogonal to the direction of bit line 3 1 0, and the second line segment 3 7 0 of word line 3 6 0 is parallel to the direction of bit line 3 1 0 and

478146 V. Description of the invention (9) It is located above the free layer 3 50 and can increase the magnetic resistance ratio by this. As described above, in the embodiment of the present invention, a method for manufacturing a magnetoresistive random access memory (MRAM) is provided. The invention can form a new configuration structure of the magnetoresistive random access memory to replace the traditional structure and obtain a better reproducibility of the magnetoresistive. Therefore, this method can be applied to deep sub-micron technology of semiconductor elements. In addition, the method can form a stepped word line segment parallel to the bit line at the memory cell of the pseudo-spin switch to obtain a stronger induced magnetic field, that is, the present invention has a larger magnetic resistance Ratio, as shown in the third B diagram. On the other hand, since the method of the present invention only requires a lower write current, the present invention can provide a magnetoresistive random access memory with better magnetoresistive reproducibility to increase the yield and yield of the process. , And can reduce costs accordingly. In other words, the method of the present invention can be economically beneficial. Of course, the present invention may be used in a process for forming a spin-switch-like memory cell, or it may be used in the manufacture of any magnetoresistive random access memory element. Moreover, the present invention uses a method in which the word lines and the bit lines are parallel to each other to obtain a stronger induced magnetic field and can reduce the write current. So far, it has not been developed for the process of magnetoresistive random access memory. For deep sub-micron processes, this method is a better and feasible magnetoresistive random access memory process. Obviously, according to the description in the above embodiments, the present invention may have some limitations.

478146 V. Description of invention (ίο) Many amendments and differences. Therefore, it needs to be understood within the scope of the appended claims. In addition to the above detailed description, the present invention can be widely implemented in other embodiments. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following application patents Within range.

Page 478146 Brief description of the diagram. Figure 1A shows a perspective view of the configuration of a conventional pseudo-spin switch-like reluctance random access memory; Figure 1B shows a conventional pseudo-spin switch-like reluctance random access Top view of the memory configuration; Figure 1C shows a cross-sectional view of the structure of a conventional pseudo-spin switch-like memory cell; and Figure 2 is a diagram of a pseudo-spin-like switch according to a first preferred embodiment of the present invention. A sectional view of the structure of a memory cell; and FIGS. 3A and 3B are configuration diagrams of a magnetoresistive random access memory with a pseudo-spin switch in a second preferred embodiment of the present invention. The main part of the symbol: 110A bit line. 110B bit line. 110C bit line. 120A character line. 120B character line. 120C character line. 130 Traditional magnetoresistive random access memory cells. 140 Traditional pseudo-spin switch.

478146

Brief description of the drawing 150 160 170 210 220 230 240 250 250 260 2 7 0A 2 7 0B 2 7 0 C 310 320 330 340 350 360 3 7 0A 3 7 0B The layers are fixed by the middle layer. Pseudo-spin switch memory cells. Fixed layer. middle layer. Free layer. First wire layer. Second wire layer. The first line segment. The second line segment. The third line segment. Bit lines. Memory cells that resemble spin switches. Fixed layer. middle layer. Free layer. Character lines. The first line segment. The second line segment.

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Claims (1)

478146 6. Scope of patent application 1. A pseudo-spin switch memory cell configuration structure, which is one of the magnetoresistive random access memories. The pseudo-spin switch memory cell configuration structure includes at least: a first electrical conduction line; A pseudo-spin switch memory cell, the pseudo-spin switch memory cell is located above the first electrical conduction line; and a second electrical conduction line above the pseudo-spin switch memory cell, the second electrical conduction line includes A continuous polyline that successively connects one of a first straight line, a second straight line, and a third straight line, wherein the first straight line and the third straight line are parallel to each other and the first straight line and the third straight line are respectively connected to the first electrical conduction line. The directions of the lines are staggered, and the second straight line is located above the spin switch memory cell and parallel to the direction of the first electrical conduction line. 2. The quasi-spin switch memory cell configuration structure described in item 1 of the scope of the patent application, wherein the above-mentioned first electrical conduction line includes at least one bit line. 3. The configuration structure of the pseudo-spin-like memory cell as described in item 1 of the scope of patent application, wherein the pseudo-spin-like memory cell includes at least one stacked structure. 4. The quasi-spin switch memory cell configuration structure described in item 3 of the scope of the patent application, wherein the above-mentioned stacked structure includes at least: a fixed layer with multiple layers of magnetized material, the fixed layer is located in the first electrical Above the conductive line; an intermediate layer, which is connected to the fixed layer; and Guide to the wire 〇 Electricity, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, one layer, two layers, the 478,146. The quasi-spin switch memory cell configuration structure described in item 4 of the scope of the patent application, wherein the above-mentioned fixed layer includes at least a fixed polarization direction. 6. The quasi-spin switch memory cell configuration structure described in item 4 of the scope of the patent application, wherein the above intermediate layer includes at least one metal material. 7. The pseudo-spin-like memory cell configuration structure described in item 4 of the scope of the patent application, wherein the above free layer includes at least one variable polarization direction. 8. The quasi-spin switch memory cell configuration structure described in item 1 of the scope of the patent application, wherein the above-mentioned second electrical conductive line includes at least one word line. 9. An arrangement structure of a plurality of pseudo-spin-like magnetoresistive random access memories, the arrangement structure of the magnetoresistive random access memory at least comprising: a plurality of first electrical conductive lines parallel to each other; Memory cells with pseudo-spin-like switches, the plurality of memory cells with pseudo-spin-like switches are respectively located above the plurality of first electrical conduction lines; and a plurality of second electrical conduction lines with step-shaped continuous polylines lie in Page 17 478146 6. The scope of the patent application is above the plurality of memory cells with pseudo-spin-like switches. Among them, through the plurality of second electrical conduction wires of the plurality of memory cells with pseudo-spin switches. The line segment and the direction of the first electrically conductive line are parallel to each other, and thereby the magnetic resistance ratio can be increased. I. The arrangement structure of the magnetoresistive random access memory with a plurality of pseudo-spin switches as described in item 9 of the scope of the patent application, wherein the plurality of first electrical conductive lines includes at least one bit line. II _ The configuration structure of the magnetoresistive random access memory having a plurality of pseudo-spin-like switches as described in item 9 of the scope of the patent application, wherein the plurality of memory cells having the pseudo-spin-like switches include at least one convolution structure. 1 2 · The configuration structure of the magnetoresistive random access memory having a plurality of pseudo-spin switches as described in item 11 of the scope of the patent application, wherein the above-mentioned stacked structure includes at least: a plurality of fixed materials with multiple layers of magnetized material Layers, the plurality of fixed layers are located on the plurality of first electrical conduction lines; a plurality of intermediate layers, the plurality of intermediate layers are connected to the plurality of fixed layers; and a plurality of free layers having a multilayer magnetization material Connected to the plurality of intermediate layers and located under the plurality of second electrical conduction lines, wherein the distant line segments of the memory cell passing through the plurality of second electrical conduction lines having a pseudo-spin switch and the 与The directions of several free layers are parallel to each other. Page 18 478146 6. Application scope 1 3. The configuration of the magnetoresistive random access memory with a plurality of pseudo-spin switches as described in item 12 of the scope of application for patents, in which the above-mentioned plurality of fixed layers At least one fixed polarization direction is included. 14. The configuration structure of the magnetoresistive random access memory having a plurality of pseudo-spin switches as described in item 12 of the scope of the patent application, wherein the plurality of intermediate layers include at least one metal material. 1 5. The configuration of the magnetoresistive random access memory having a plurality of pseudo-spin switches as described in item 14 of the scope of the patent application, wherein the above-mentioned metal material includes at least one copper material. 16. The arrangement structure of the magnetoresistive random access memory having a plurality of pseudo-spin switches as described in item 12 of the scope of the patent application, wherein the plurality of free layers described above include at least one variable polarization direction. 1 7. The configuration of the magnetoresistive random access memory having a plurality of pseudo-spin switches as described in item 9 of the scope of the patent application, wherein the plurality of second electrical conductive lines includes at least one word line. 18. The configuration structure of the magnetoresistive random access memory having a plurality of pseudo-spin-like spin switches as described in item 9 of the scope of the patent application, wherein the plurality of second electrical conductive lines fail to pass the plurality of pseudo-like Spin-switch memory cell The plurality of coordination lines of the magnetoresistive body whose directions of electrical conduction lines intersect are a plurality of fixed number of medium character lines which are orthogonal to each other in the complex, and the plurality of arrangement structures of the random access memory are added since then. The structure includes at least: a fixed layer on the bit line; an intermediate layer on the fixed layer; a free layer on the interlayer; and 'the plurality of character lines are above the stepped free layers, of which, a plurality of A line segment and a plurality of first line segments are not orthogonal to each other through the bit line, and the complex layer is above the layer and is in line with the bit magnetic resistance ratio. 6. The line segments of the scope of patent application are related to the plurality of 19. The kind can increase the magnetoresistance ratio, the magnetoresistive random access memory, a plurality of mutually parallel plurality are respectively located in the plurality of links to the plurality of links to the A plurality of continuous polylines parallel to each other and the plurality of character lines are connected by the second line segment to form a plurality of free layers and are parallel to each other through the complex line through the second line segment, 20. The configuration of the magnetic anode [I, left stack access memory, such as ^ W, 4 people m —, r, as described above, can be borrowed as described in item No. 9 of the scope of the patent application. Each of the plurality of fixed layers 5 ^ k has a fixed polarization direction. 2 1 · As described in item 19 of the scope of the patent application, the configuration of the galvanic structure can be obtained, and the magnetic resistance of i from day t follows the complex number of m above which contains a copper U. At least Page 20 478146 VI. Application for patent scope 2 2. The configuration of the magnetoresistive random access memory that can increase the magnetoresistance ratio as described in item 19 of the scope of patent application, wherein the above-mentioned plurality of free layers include at least one Variable polarization direction. Page 21