TW503393B - Magneto-resistance random access memory array having pseudo spin valve - Google Patents

Abstract

The present invention discloses a magneto-resistance random access memory (MRAM) array having pseudo spin valve. The array comprises: plural pseudo spin valve memory cells having a stacked structure; plural linear, parallel word lines on top of the plural pseudo spin valve memory cells; and plural bit lines comprising the continuous broken lines of mutually orthogonal first line, second line and third line, wherein the first line and the third line are parallel, and are orthogonal to the direction of a word line, the second line of plural bit lines is located on plural pseudo spin valve memory cells, and is parallel to the direction of a word line.

Description

503393 V. Description of the invention (i) 5-1 Field of invention: The present invention relates to an array of magnetoresistive random access memory (MRAM), and in particular to a method of forming An array of magnetoresistive random access memory (MRAM) of a rotary switch (psv). 5-2 Background of the Invention: As the accumulation of semiconductor elements continues to expand, the area of use of chips must remain the same, or even shrink, in order to continuously reduce the unit cost of the circuit. In order to comply with the future development trend of the high-tech industry, the only way is to continuously refine the circuit design rules (d e s 丨 g η Γ u 1 e). Therefore, the space area occupied by the components also gradually decreases with the circuit design specifications (desi.gn rule). With the development of semiconductor technology, the size of integrated circuit components has been reduced to the sub-micron range. When the semiconductor is continuously reduced to the range of the sub-micron range, some problems in process shrinkage arise. There are many types of memory in the field of Very Large Scale Integrated circuits (VLSI). In recent years, a memory random access memory (MRAM) that can be used as a non-volatile storage element has been developed in the integrated circuit industrial process. Magnetoresistive random access

V. Description of the invention (2) Conductor and magnetic memory are non-volatile and dynamic random access. With the magnetic information of the strong magnetic field, it can be called magnetoresistance by changing the magnetic state. "Magnetic memorization: The body of the __ series is based on the integration of complementary s: pieces, the magnetic: d-body has an unlimited number of reads and writes, but the memory is different from the spot". In this direction, the asset m is stored, because the two is remembering the time of the somatic cell line, so i Λ is not stored while I secretly keep it ”and / or Ma non-volatile. The magnetic memory cell can change the resistance of the material close to the strong magnetic region. Some types of magnetic memory cell H. A magnetized memory cell: array: random access memory or magnetoresistive random access memory. The two main implementations of magnetoresistive random access memory (MRAM) technologies are pseudo spin switch (PSV) and magnetic tunnel junction (MTJ) methods. The current theory of giant magnetoresistance (GMR) and magnetic channel interface materials has given the magnetoresistive random access memory high speed, potential operation voltage, and high density. There are two types of strong magnetoresistive (GMR) structures: one is a spin valve (SV), and the other is a pseudo-spin switch (PSV). In a spin-switch memory element, the polarization direction of one magnetization layer (fixed layer) is fixed, while the polarization direction of the other magnetization layer (free layer) can be changed. The information stored in this free layer is based on Based on the direction of magnetic polarization associated with the pinned layer. In this architecture, the state of the memory can be determined by comparing the resistance of a GMR storage element with a reference memory cell. The structure of a pseudo-spin switch consists of two magnetized layers of different thicknesses and one

Page 5 503393 V. Description of the invention (3) It is composed of a copper layer which is an intermediate layer. Due to the anisotropic shape in the sub-micron size, magnetized layers of different thicknesses have different shtchi_fields. At the moment of magnetization, the two magnetized layers can obviously form antiparallel polarity and parallel polarity ', which will generate high resistance and low resistance of the thin film, respectively. A conventional quasi-spin-switched memory cell stores data in two possible polarizations of a thick magnetized layer. By simultaneously implementing an induced current and a negative and a positive finger current (d i g i t c u r r e n t), the bits can be read non-destructively. Selecting the finger current intensity can control the magnitude of the magnetic field generated. The combination of finger current and induced current is sufficient to open a thin magnetized layer, but not enough to open a thick magnetized layer. Figure 1A shows an array of magnetoresistive random access memory (MRAM) cells of a conventional magnetoresistive memory cell. This array contains a set of parallel bit lines 11 0 A, 11 0 B, 11 on a horizontal plane. The 0 C electrical conduction lines are parallel to the other groups on the other horizontal plane as 120A, 120B, 120C electrical and conduction lines. The directions of the bit lines 110A, 110B, and 110C and the character lines 120A, 120B, and 120C are at a 90-degree angle with each other, so that when viewed from top to bottom, the two sets of lines are staggered with each other, as shown in the first figure B. As shown in the first c figure, a memory cell 1 3 0 'is located at an intersection in a vertical space where each character line 1 2 0 b and a bit line 1 1 0 c cross each other. The memory cell 130 is a vertically stacked structure, and the vertical stacked structure includes a pseudo-spin switch 1440. The pseudo-spin switch 1 40 has a fixed layer 15 with a fixed magnetization direction, a free layer 160 with a variable magnetization direction, and an intermediate layer 170 between the fixed layer and the free layer.

503393 V. Description of Invention (4)

During the operation of the array, the magnetization at the two end points and the corner subsidence is non-uniform, which generates additional torque to make it easier to reverse the process, so the transition field is lower. In a quasi-spin switch memory, the magnetization directions of the hard and soft layers must be opposite for read and write operations, respectively. For the read operation, the amplifier is first reset to zero, then an induced current is applied to the active memory bit and the reference bit, and a negative finger current is applied to the active memory bit. When the finger current is converted into the forward direction, the induced current is still saved, and the output of the amplifier is flashing. Therefore, bit data can be measured by detecting changes in the signal strength between the active bit memory cell and the reference memory cell.

However, this traditional structure will lead to some problems. The conventional MR-RAM with pseudo-spin switch is composed of two orthogonal bit lines and word lines, as shown in Figure 1B. In the write mode, the bit line and the word line are polarized to a thick magnetization layer between the induced fields. Therefore, a stronger induced magnetic field is needed to form a magnetoresistance, that is, the conventional MR-RAM with pseudo-spin switches has a smaller magnetoresistance ratio. In addition, a higher write current is also required. Accordingly, only by aligning the magnetic field with the bit line segment can a stronger magnetic resistance be generated. In view of the above reasons, we need a new array of memory cells of magnetoresistive random access memory (MRAM) in order to improve the yield and yield of subsequent processes.

Page 7 V. Description of the invention (5) 5-3 Purpose and summary of the invention: In view of the above background of the invention, the traditional method of making magnetoresistive resistors & J It can be used to overcome the problems in the traditional manufacturing process. The main purpose of the present invention is to provide a method of j_xiao. The present; shape; magnetic :: access to the memory M mmr ιπποο 乃 月 Φ 成A new type of magnetoresistance random storage (MRAM) < array is used to replace the traditional structure with good reproducibility of magnetoresistance. Therefore, this method provides a technical towel for deep submicron technology. Another object of the invention of a semiconductor device is to provide a method for forming a memory cell of a magnetoresistive random access memory (MRAM). A square switch is formed at the memory cell of the local switch to form a 2-rotation α ^ 5 with the i-element line) 1 ^ ^ θ & Ding again from the ladder-shaped bit line segment to pay a stronger induced magnetic field, that is, the current resistance ratio. Therefore, the method of the present invention only needs a perch & < 乂 乂 acupoint magnetic field, the present invention can provide a η: magnetic: m input current. Based on this. Therefore, the method of the present invention can meet the requirements; it can be reduced to a new one with similar appearance. According to the above-mentioned purpose, the present invention discloses

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503393 V. Description of the invention (6) Several arrays of spin switch magnetoresistive random access memory have a stack structure (pseudo-spin valve), which is composed of a layer and a middle Interlayer and a self); parallel electrical conduction lines as a plurality of words) on a horizontal plane, wherein a plurality of characters are regarded as a plurality of bits on a fixed layer of a plurality of spin switch memory cells The “plurality of bit lines” in the bit line are several bits that are orthogonal to each other (the straight line, the second straight line, and the third straight line are continuously folded. The first straight line and the third straight line are respectively a number of bits. The second straight line of the line is located above the plurality of spin layers and is parallel to the direction of the character line. The detailed description of the invention of 5-4: The direction discussed in the present invention is a magnetic array. A detailed understanding of the present invention will lead to detailed steps. Obviously, the implementation of the present invention is a special detail familiar to those skilled in the art. Another step is not described in the details in order to avoid fabrication. Examples will be described in detail In addition to the detailed description, the present invention can also be widely used. This array includes: a multi-rotary switch memory cell (a pinned layer (free layer, word line, and line are straight lines, and bits; and Another horizontally parallel electrical conductive line, its orthogonal) line, and the directions parallel to each other are orthogonal, and the complex switching memory cell is free to increase the magnetoresistance ratio. The resistance random access memory is not mentioned in the following description. Limited to the semiconductor aspect, the well-known cost invention is not necessary as follows, but in addition to this implementation in other implementations

503393 V. Description of the invention (7) In the example, and the scope of the present invention is not limited, it is subject to the scope of the following patents. Refer to the second figure. In the first embodiment of the present invention, a A pseudo spin valve 210 similar to a stack structure. The stack structure includes at least a pinned 1 ay er with multiple layers of magnetized material (such as Ni, Co, Fe alloy). 220, wherein the polarization direction of the fixed layer 220 is uniform and fixed; an intermediate layer 230 on the fixed layer 220, wherein the material of the intermediate layer 230 includes at least one metal material (for example, A copper layer); a free layer 240 having a multilayer magnetization material (such as Ni, Co, Fe alloy) on the intermediate layer 230, wherein the free layer 240 has a variable polarization direction. On a horizontal plane, a first electrical conductive line 2 50 is located above the free layer 2 40. The first electrical conductive line 2 50 includes at least one word line and the first electrical conductive line 2 50 is parallel. Straight line of quasi-spin switch memory cell 2 1 0. On the other horizontal plane, a second electrical conducting wire 26 is located under the fixing layer 220. The second electrical conductive line 2 60 includes at least one bit line and the second electrical conductive line 2 60 is a continuous polyline including a first line segment 270A, a second line segment 270B, and a third line segment 270 C. (For example, zigzag), where the first line segment 2 70 A and the third line segment 2 7 0 C are parallel to each other and the first line segment 2 70 A and the third line segment 2 7 0 C are respectively The directions of the conductive lines 2 50 are staggered, and the second line segment 2 7 0 B is located below the fixed layer 220 of the spin switch memory cell 21 0 and is in line with the first telex

Page 10 503393 V. Description of the invention (8) —- The directions of the wires 25 0 are parallel to each other, thereby increasing the magnetoresistance ratio (magnetres i stance rati ο) 〇 Refer to Figures 3A and 3b. In a second embodiment of the present invention, a plurality of character lines 310 parallel to each other are first provided on a first horizontal plane, wherein the plurality of character lines 310 are straight lines parallel to each other. Then, a plurality of quasi-spin-like switch memory cells 3 2 0 having a stack structure are formed on a plurality of bit lines 3 1 0, and each quasi-spin-like switch memory cell 320 includes at least: The free layer 350 under the element line 31 °, wherein the free layer 350 has a multilayer magnetization material (such as Ni, c 0, {? E alloy), and the free layer 350 has a variable polarization direction; An intermediate layer 340 formed under the free layer 350, wherein the material of the intermediate layer 340 includes at least one copper material; a fixed layer 330 'formed under the intermediate layer 340, wherein the fixed layer 330 has a multilayer magnetization material (E.g. ni, c 〇,

Fe alloy), and the polarization direction of the fixed layer 330 is uniform and fixed: not changed. After that, a plurality of bit lines 3 6 0 are formed 'on a first horizontal plane' under a fixed layer 3 3 0 of a plurality of pseudo-spin-like memory cells 3 2 0, wherein each bit line 3 6 0 is A continuous polyline with a step shape is formed by connecting an orthogonal first line segment 370A and a second line segment 3 70B, and the first line segment 3 7 0 A and the character line 3 1 0 And the direction of the second line segment 3 7 0 B of the bit line 3 6 0 and the character line 3 1 0 are parallel to each other and located below the fixed layer 3 3 0, and the magnetoresistance ratio can be increased accordingly. .

Page 11 503393 V. Description of the invention (9) As described above, in the embodiment of the present invention, a method for manufacturing a magnetoresistive random word fetch memory (Dragon Am) is provided. The invention can form a new configuration structure of the magnetoresistive random access memory to replace the traditional structure and obtain a better reproducibility of the magnetoresistive. Therefore, this method can be applied to deep sub-micron technology of semiconductor elements. In addition, the method can form a step-like bit line segment parallel to the word line at the memory cell of the pseudo-spin switch to obtain a stronger induced magnetic field, that is, the present invention has a larger magnetoresistance ratio. As shown in the third figure b. On the other hand, since the invention requires only a lower write current, the present invention can provide a magnetoresistive random access memory with a good magnetoresistance reproducibility to increase = I to 2 rate 'I This can reduce costs. In other words, this issue: j, is enough to meet the economic benefits. The method can, of course, be applied to the manufacturing process of the boundary j, and it may also be applied to the magnetic field of the suspected spin-switch memory cell. … The present invention uses the word line and the bit body to make a stronger induction magnetic field and can reduce the write current j: phase to obtain — ;; the system of magnetoresistive random access memory has not yet been developed Process. Magnetoresistive random access memory: It is inferred that, in addition to the claims of the present invention, the present invention also

May have a wide range of terms

503393 Fifth, the invention description (ίο) is implemented in other embodiments. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following application patents Within range. .

Page 13 503393 Brief description of the diagram. The first diagram A shows a perspective view of the configuration of a conventional pseudo-spin switch-like magnetoresistive random access memory. The first diagram B shows a conventional pseudo-spin switch-like reluctance random access. Top view of the memory configuration; Figure 1C shows a cross-sectional view of the structure of a conventional pseudo-spin switch-like memory cell; and Figure 2 is a diagram of a pseudo-spin-like switch according to a first preferred embodiment of the present invention. A sectional view of the structure of a memory cell; and FIGS. 3A and 3B are configuration diagrams of a magnetoresistive random access memory with a pseudo-spin switch in a second preferred embodiment of the present invention. The main part of the symbol: 11 0 A bit line. 110B bit line. 11 0 C bit line. 1 2 0 A character line. 120B character line. 1 2 0 C character line. 130 Traditional magnetoresistive random access memory cells. 14 0 The traditional pseudo-spin switch.

Page 14 503393 Brief description of the diagram 150 Fixed layer 0 160 Free layer 0 170 Intermediate layer 〇210 Pseudo-spin-open 220 Fixed layer 〇230 Intermediate layer 〇240 Secret layer 〇250 First wire layer 260 Second wire layer 270A One line segment 270B second line segment 270C second line segment 〇310 character line 〇320 pseudo-swivel 330 fixed layer 0 340 middle layer 〇350 free layer 〇360 bit line 0 370A first-line segment 0 370B line segment 〇

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Claims (1)

503393 VI. Scope of patent application 1. An array of pseudo-spin switch memory cells, which is one of magnetoresistive random access memories. The array of pseudo-spin switch memory cells includes at least: a first electrical conduction line, wherein the The first electric conduction line has a word line; a pseudo-spin switch memory cell, the pseudo-spin switch memory cell is located below the first electric conduction line; and a first Two electrical conductive lines, the second electrical conductive line has a one-bit line, and the second electrical conductive line includes a continuous polyline that successively connects a first straight line, a second straight line, and a third straight line, wherein the first A straight line and the third straight line are parallel to each other and the first straight line and the third straight line are intersected with the direction of the first electric conduction line, respectively, and the second straight line is located above the spin switch memory cell and is parallel to the first electric line. The directions of the conductive lines are parallel to each other. 2. The array of quasi-spin-switch memory cells as described in item 1 of the scope of the patent application, wherein the quasi-spin-switch-memory cells described above include at least one stacked structure. 3. The quasi-spin-switch memory cell array as described in item 2 of the scope of the patent application, wherein the above-mentioned stacked structure includes at least: a fixed layer having multiple layers of magnetized material, the fixed layer is located in the second On the second straight line of the electric conduction line; an intermediate layer connected to the fixed layer; and a free layer with multiple layers of magnetized material located on the first electric conduction line Page 16 503393 Sixth, the scope of patent application ~~, the free layer is connected to the intermediate layer. 4. The quasi-spin-switch memory cell array as described in item 3 of the scope of the patent application, wherein the above-mentioned fixed layer 炱 3 is fixed and the polarization direction is unchanged. 5. As described in the scope of the patent application, item 3 The pseudo-spin switch memory cell array, wherein the intermediate layer described above does not include a metal material. of. The turning of the cell to the body side It's turning off is very similar to the presumptive inclusion of the item to the third level. The self-contained Fan Shuli junior high school invites its ¢-, ρ * ΠΊ 歹 6 7. An array of complex conductors which are similar to the complex conductors of the plurality of conductors which have a plurality of conductors, and the reluctance is used by a plurality of each other as a plurality of rotary switches; The telex has an quasi-like line segment and an quasi-spin switch-like magnetoresistive random access memory access memory array including at least a parallel m-th electric conduction line, the i i first telex plural Character lines; ψ memory cells that are similar to spin switches, the plurality of memory cells are respectively located at the first and second continuous lines of the first electrical conduction line: the electrical conduction line is located at: 4 = off Below, where the Km plural bit lines pass through the flute two two # t ° the direction of the plural second telex-electric "lines of the known somatic cell is parallel to each other, and Page 17 503393 VI. Patent Application Fan Garden Increase the magnetoresistance ratio. 8 · The array of magnetoresistive random access memories with a plurality of pseudo-spin-like switches as described in item 7 of the scope of the patent application, wherein the plurality of memory cells with pseudo-spin-like switches include at least one convolution structure . 9 · The array of a plurality of pseudo-spin-like magnetoresistive random access memories as described in item 8 of the scope of the patent application, wherein the above-mentioned stacked structure includes at least: a plurality of free layers having multiple layers of magnetized material, the A plurality of free layers are located under the plurality of first electrical conduction lines; a plurality of intermediate layers, the plurality of intermediate layers are connected under the plurality of free layers; and a plurality of fixed layers having multiple layers of magnetized material are connected to Below the plurality of intermediate layers and located on the plurality of second electrical conduction lines, wherein: the line segments of the plurality of second electrical conduction lines passing through the plurality of memory cells having pseudo-spin-like switches are fixed to the plurality of electrical conduction lines The directions of the layers are parallel to each other. 10. The array of a plurality of pseudo-spin-open magnetoresistive random access memories as described in item 9 of the scope of the patent application, wherein the plurality of fixed layers include at least a fixed polarization direction. Π · An array of magnetoresistive random access memories as described in item 9 of the scope of the patent application, having a plurality of pseudo-spin-like switches ′ wherein the plurality of intermediate layers described above 503393 VI. Patent application scope At least one metal material. if :: ί The U-shaped array with a plurality of pseudo white spins < access memory arrays described in item U, wherein the above-mentioned metal material to > a contains a copper material.男 q Male Γ is an array with a plurality of quasi-spin-like spin switches ρ ^ as described in Item 9 of the Scope / Scope, where the plurality of free layers described above include / contain a variable polarization direction. V,] 11 ® ^^ ^ ^ ^ ^ ^ ^ ^ μ ^ i ^ M Conductive key = ΐ accesses the memory array, wherein the plurality of second electric wires P · # 2 are described above through the plurality of The line segments of the memory cells of the spin switch intersect with the directions of the plurality of first electrical conduction lines.丄 An array of 5 resistance iC magnetoresistance ratio magnetoresistive random access memory. The array of magnetoresistance IK machine access memory includes at least a plurality of parallel character lines; 禝 several of which are respectively located in the complex number Free 厣 below the character line;, a plurality of intermediate layer factories connected to the plurality of free layers, a plurality of fixed ^ connected to the plurality of intermediate layers, and a bit line of the big line 'the plurality The bit line is a step M m 'mj / the knife is located under the fixed layers, where " 疋 line consists of a plurality of first line segments and a plurality of orthogonal lines that are orthogonal to each other. Page 19 503393 VI. The second line segment of the scope of patent application is connected and formed, and the plurality of first line segments do not pass under the plurality of fixed layers and are orthogonal to the plurality of character lines, and the plurality of The second line segment passes under the plurality of fixed layers and is parallel to the plurality of word lines, thereby increasing the magnetic resistance ratio. 16. The array of reluctance random access memory capable of increasing the reluctance ratio as described in item 15 of the scope of the patent application, wherein the plurality of fixed layers include at least a fixed polarization direction. 1 7. The array of reluctance random access memory capable of increasing the reluctance ratio as described in item 15 of the scope of patent application, wherein the plurality of intermediate layers mentioned above include at least one copper material. 1 8. The array of reluctance random access memory capable of increasing the reluctance ratio as described in item 15 of the scope of the patent application, wherein the plurality of free layers mentioned above contain at least one variable polarization direction. Page 20