478103 l08twf.doc/002 Λ7 B7 五、發明說明（I ) 本發明是有關於一種場效電晶體之製程，且特別胃有 關於一種場效電晶體中之雙間隙壁之製造方法。 當元件的積集度愈來愈高之後，NMOS之能量、消耗， 將成爲繼I買利用NMOS進行g受g十並製造積體電路上的困 難。因此，具備低能耗優點的CMOS電晶體，即逐漸取代 NMOS而成爲業界的主流。現今的超大型積體電路，皆以 CMOS爲主要的設計基礎。 然而在CMOS中共存的P型場效電晶體與n型場效 電晶體，在形成各自的源極/汲極區時，係所使用不同的 摻質進行摻雜後，再一同進行回火步驟，以形成源極/汲 極。由於不同的雜質之間具有不同的擴散速率，導致在進 行回火的製程中，發生摻質擴散不均之現象，致使在P型 場效電晶體部分因摻質擴散太快而造成短通道效應，或是 在N型場效電晶體部份因摻質擴散太慢而造成未擴散完 成。 因此，習知之改善方法，係在不同的場效電晶體中的 各別利用不同摻質濃度進行摻雜，以利用濃度上的差異， 調整各摻質之擴散速率，以避免發生摻質擴散不均的現 象，然而，此法難以在整體製程上進行有效地控制，且擴 散後之源極/汲極之尺寸形狀無法完全控制。 本發明提出一種雙間隙壁之形成方法，係提供一基 底，在基底中至少包括有第一元件與第二元件，其中第一 元件與第二元件中分別形成有閘介電層與閘極。接著於基 底之上依序形成第一絕緣層與第二絕緣層，再移除位於第 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Ί-口*" · 經濟部智慧財產局員工消費合作社印製 478103 7l08twf.doc/002 A7 B7 五、發明說明（1) 二元件中之第二絕緣層。接著，移除位於第一元件中之第 二絕緣層，以於第一元件中的閘極側壁上形成第一間隙 壁，再移除部份第一絕緣層，以於第二元件中的閘極側壁 上形成一第二間隙壁。 在本發明中，係利用在P型場效電晶體/ N型場效電 晶體中，依據兩者之擴散速率差異比例，形成尺寸不同之 第一間隙壁與第二間隙壁，以藉由物理方式地控制，使在 基底中之摻質均能擴散均勻，且可形成形狀固定之源極/ 汲極區，並提高整體製程之控制性。 另外，在本發明中的第一間隙壁與第二間隙壁係利用 二層不同材質間隙壁材料，以兩次蝕刻的方式所形成，如 此’可利用簡單之製程各別形成第一間隙壁與第二間隙壁 所需之厚度，以降低製程之複雜性，而增加製程的控制性。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之單說明 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 胃1圖至第5圖所示爲本發明之一較佳實施例之雙間 隙壁之形成方法的示意圖。 1QG:基底 102:元件隔離結構 i〇4a，104b :閘介電層 !〇6a，l〇6b ··閘極 4 本紙張尺度適用中國國家標準（CNg)A4 規格（210 X 297公釐） 478103 71〇8twf.doc/〇〇2 Λ7 B7 五、發明說明（> ) (請先閱讀背面之注意事項再填寫本頁) 108a，108b :淡摻雜區 Π0 :第一元件 112 :第二元件 114，114 a :第一絕緣層 114b :第二間隙壁 116，11 6 a :第二絕緣層 116b :第一間隙壁 118a，118b :源極/汲極區 實施例 第1圖至第5圖所示爲本發明之一較佳實施例之雙間 隙壁之形成方法的示意圖。 經濟部智慧財產局員工消費合作社印製 請參照第1圖所示，提供一基底100，在基底100上 至少以形成有第一元件110與第二元件112，且於第一元 件110與第二元件112之間形成有元件隔離結構102以作 爲區隔。又於第一元件110中形成有閘介電層102a與閘 極104a，於第二元件112中形成閘介電層102b與聞極 l〇4b。其中基底1〇〇之材質包括矽，閘介電層102a、102b 之材質包括氧化矽，形成閘介電層l〇2a、102b之方法包 括熱氧化法。閘極104a、l〇4b之材質包括摻雜複晶矽、 金屬矽化物或摻雜複晶矽/金屬矽化物，形成閘極l〇4a、 l〇4b之方法包括化學氣相沈積法。 另外，第一元件110/第二元件112包括P型場效電晶 體(P-FET)/ N型場效電晶體(N-FET)或高電壓元件(例如是 I/O區)/低電壓元件(例如是core區）。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478103 7108twf.d〇c/002 Λ7 B7 五、發明說明（t) (請先閱讀背面之注意事項再填寫本頁) 之後，分別利用閘極104a、104b爲罩幕於第一元件110/ 第二元件112之基底100中形成淡摻雜源極/汲極區l〇8a、 108b，此淡摻雜區108a、108b即爲輕微摻雜汲極（Ughtly Doped Drain，LDD)，形成淡摻雜區108a、l〇8b的方法 包括離子植入法，例如利用約爲40仟電子伏特至80仟電 子伏特之能量，植入約爲5xl012離子/平方公分至5xl〇14 離子/平方公分的砷離子或磷離子的劑量。 接著，請參照第2圖所示，在基底100之上形成第一 絕緣層114，其中第一絕緣層114之材質包括二氧化矽， 形成第一絕緣層114之方法包括利用化學氣相沈積法。再 於第一絕緣層114之上形成第二絕緣層116，其中第二絕 緣層之材質包括氮化矽。另外，第一絕緣層114與第二絕 緣層116之厚度，視製程之間隙壁或源極/汲極區所需要 之尺寸作爲沈積厚度之依據。 經濟部智慧財產局員工消費合作社印製 接著’請參照第3圖所示，利用微影蝕刻之技術，移 除位於第二元件112中之第二絕緣層106，以暴露位於第 二元件112上之第一絕緣層114。同時，保留位於第一元 件110中之第二絕緣層116a。其中移除第二絕緣層106之 方法包括乾蝕刻法或濕蝕刻法。 接著，請參照第4圖所示，移除位於第一元件11〇中 之部份第二絕緣層116a，以在閘極l〇6a之側壁上形成第 一間隙壁116b，其中移除部份第二絕緣層U6a的方法包 括非等向性蝕刻法。又，第一間隙壁116b之頂點與閘極 l〇6a之頂面位於同一水平面上。 6 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 478103 Λ7 五、發明說明（f ) 接著，請參照第5圖所示，移除部份第一絕緣層114， 以在閘極106b之側壁上形成第二間隙壁114b，並於閛極 106a與第一間隙壁116b之間的殘留部分第一絕緣層 114a。其中移除部分第一絕緣層114之方法包括非等向性 蝕刻法，可利用氟化碳電漿蝕刻進行。 之後，利用具有第一間隙壁116b之閘極106a及具有 第二間隙壁114b之閘極106b爲罩幕，對基底100進行重 摻質植入步驟，以在閘極106a、106b兩側之基底1〇〇中 形成源極/汲極區118a、118b。 在習知在CMOS中共存的P型場效電晶體與N型場 效電晶體，在形成各自的源極/汲極區時，係所使用不同 的摻質進行摻雜後，再一同進行回火步驟，以形成源極/ 汲極。由於不同的雜質之間具有不同的擴散速率，導致在 進行回火的製程中，發生摻質擴散不均之現象，致使在p 型場效電晶體部分因摻質擴散太快而造成短通道效應，或 是在N型場效電晶體部份因摻質擴散太慢而造成未擴散完 成。 因此，習知之改善方法，係在不同的場效電晶體中的 各別利用不同摻質濃度進行摻雜，以利用濃度上的差異， 調整各摻質之擴散速率，以避免發生摻質擴散不均的現 象’然而，此法難以在整體製程上進行有效地控制，且擴 散後之源極/汲極之尺寸形狀無法完全控制。 在本發明中，係利用在P型場效電晶體/ N型場效電 晶體中’依據兩者之擴散速率差異比例，形成尺寸不同之 7 (請先閱讀背面之注意事項再填寫本頁) 訂： •線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 478103 7108twf.doc/ 002 A 7 _ 137 _ 五、發明說明（& ) 第一間隙壁與第二間隙壁，以藉由物理方式地控制，使在 基底中之摻質均能擴散均勻，且可形成形狀固定之源極/ 汲極區，並提高整體製程之控制性。 另外，在本發明中的第一間隙壁與第二間隙壁係利用 二層不同材質間隙壁材料，以兩次蝕刻的方式所形成，如 此，可利用簡單之製程各別形成第一間隙壁與第二間隙壁 所需之厚度，以降低製程之複雜性，而增加製程的控制性。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾。 (請先閱讀背面之注意事項再填寫本頁) . · -丨線· Φ 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）478103 l08twf.doc / 002 Λ7 B7 V. Description of the Invention (I) The present invention relates to a process of a field effect transistor, and particularly relates to a method for manufacturing a double-spacer wall in a field effect transistor. After the component accumulation becomes higher and higher, the energy and consumption of NMOS will become a difficulty in manufacturing integrated circuits using NMOS for g and g. Therefore, CMOS transistors with low power consumption advantages have gradually replaced NMOS and become the mainstream in the industry. Today's very large integrated circuits are based on CMOS. However, the P-type field-effect transistor and the n-type field-effect transistor coexisting in CMOS, when forming their respective source / drain regions, are doped with different dopants, and then tempered together. To form a source / drain. Due to different diffusion rates between different impurities, the phenomenon of uneven dopant diffusion occurs during the tempering process, resulting in the short channel effect due to the dopant diffusion in the P-type field effect transistor part. Or, in the N-type field effect transistor part, the diffusion is not completed due to the slow diffusion of dopants. Therefore, the conventional improvement method is to use different dopant concentrations for doping in different field effect transistors to adjust the diffusion rate of each dopant by using the difference in concentration to avoid dopant diffusion. However, this method is difficult to effectively control the overall process, and the size and shape of the diffused source / drain cannot be completely controlled. The present invention provides a method for forming a double-gap wall, which provides a substrate including at least a first element and a second element, wherein a gate dielectric layer and a gate are formed in the first element and the second element, respectively. Then, the first insulating layer and the second insulating layer are sequentially formed on the substrate, and then the third paper size is removed to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the note on the back first) Please fill in this page for more information) Ί- 口 * " · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478103 7l08twf.doc / 002 A7 B7 V. Description of the invention (1) The second insulation layer in the two components. Next, the second insulating layer located in the first element is removed to form a first gap wall on the gate side wall of the first element, and then a portion of the first insulating layer is removed to form a gate in the second element. A second gap wall is formed on the electrode sidewall. In the present invention, the first gap wall and the second gap wall with different sizes are formed in the P-type field-effect transistor / N-type field-effect transistor according to the ratio of the difference in the diffusion rates of the two, so as to use physical It can be controlled in a way to make the dopants in the substrate diffuse evenly, and can form a fixed source / drain region, and improve the controllability of the overall process. In addition, in the present invention, the first gap wall and the second gap wall are formed by using two layers of gap wall materials of different materials and etched twice, so that the first gap wall and the gap wall can be formed separately by a simple process. The thickness of the second spacer wall is required to reduce the complexity of the process and increase the controllability of the process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: The single of the drawings illustrates the intellectual property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperative (please read the precautions on the back before filling this page) Figures 1 to 5 of the stomach are schematic diagrams of the method for forming the double gap wall in a preferred embodiment of the present invention. 1QG: substrate 102: element isolation structure 〇4a, 104b: gate dielectric layer! 〇6a, 106b ·· gate 4 This paper size applies to China National Standard (CNg) A4 specification (210 X 297 mm) 478103 71〇8twf.doc / 〇〇2 Λ7 B7 V. Description of the invention (>) (Please read the notes on the back before filling this page) 108a, 108b: Lightly doped region Π0: First element 112: Second element 114, 114a: first insulating layer 114b: second spacer 116, 11 6a: second insulating layer 116b: first spacer 118a, 118b: source / drain region embodiment 1 to 5 Shown is a schematic diagram of a method for forming a double-spacer wall according to a preferred embodiment of the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 1 to provide a substrate 100 on which at least a first element 110 and a second element 112 are formed, and the first element 110 and the second element Element isolation structures 102 are formed between the elements 112 as a separation. A gate dielectric layer 102a and a gate electrode 104a are formed in the first element 110, and a gate dielectric layer 102b and a gate electrode 104b are formed in the second element 112. The material of the substrate 100 includes silicon, and the material of the gate dielectric layers 102a and 102b includes silicon oxide. The method of forming the gate dielectric layers 102a and 102b includes a thermal oxidation method. The materials of the gate electrodes 104a and 104b include doped polycrystalline silicon, metal silicide, or doped polycrystalline silicon / metal silicide. Methods for forming the gate electrodes 104a and 104b include chemical vapor deposition. In addition, the first element 110 / the second element 112 includes a P-type field effect transistor (P-FET) / N-type field effect transistor (N-FET) or a high voltage element (for example, an I / O region) / low voltage Element (for example, the core area). 5 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 478103 7108twf.d〇c / 002 Λ7 B7 V. Description of the invention (t) (Please read the precautions on the back before filling this page) After that, lightly doped source / drain regions 108a and 108b are formed in the substrate 100 of the first element 110 / second element 112 by using the gate electrodes 104a and 104b as masks, respectively. The lightly doped regions 108a and 108b That is, a lightly doped drain (LDD) is used to form the lightly doped regions 108a and 108b. The method includes ion implantation. For example, using an energy of about 40 仟 electron volts to 80 仟 electron volts, The dose of arsenic or phosphorus ions is about 5 × 1012 ions / cm 2 to 5 × 10 14 ions / cm 2. Next, as shown in FIG. 2, a first insulating layer 114 is formed on the substrate 100. The material of the first insulating layer 114 includes silicon dioxide. A method of forming the first insulating layer 114 includes using a chemical vapor deposition method. . A second insulating layer 116 is formed on the first insulating layer 114. The material of the second insulating layer includes silicon nitride. In addition, the thickness of the first insulating layer 114 and the second insulating layer 116 depends on the required thickness of the spacer or source / drain region of the process as the basis for the thickness of the deposition. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, please refer to FIG. 3, and use the photolithography technique to remove the second insulating layer 106 located on the second element 112 to expose the second element 112. The first insulating layer 114. At the same time, the second insulating layer 116a located in the first element 110 remains. The method in which the second insulating layer 106 is removed includes a dry etching method or a wet etching method. Next, referring to FIG. 4, a part of the second insulating layer 116 a located in the first element 11 is removed to form a first gap wall 116 b on the side wall of the gate 106 a, and a part is removed. The method of the second insulating layer U6a includes an anisotropic etching method. Moreover, the apex of the first gap wall 116b and the top surface of the gate electrode 106a are located on the same horizontal plane. 6 This paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) 478103 Λ7 V. Description of the invention (f) Next, please refer to Figure 5 to remove part of the first insulation layer 114, In order to form a second gap wall 114b on the sidewall of the gate electrode 106b, and a portion of the first insulating layer 114a remaining between the gate electrode 106a and the first gap wall 116b. The method for removing a part of the first insulating layer 114 includes an anisotropic etching method, which can be performed using a carbon fluoride plasma etching. After that, the gate electrode 106a having the first gap wall 116b and the gate electrode 106b having the second gap wall 114b are used as masks, and the substrate 100 is re-doped with implantation steps so that the substrates on both sides of the gate electrodes 106a, 106b are formed. Source / drain regions 118a, 118b are formed in 100. In the conventional P-type field-effect transistor and N-type field-effect transistor that coexist in CMOS, when forming their respective source / drain regions, different dopants are used for doping, and then back together. Fire step to form source / drain. Due to the different diffusion rates between different impurities, the phenomenon of uneven dopant diffusion occurs during the tempering process, resulting in a short channel effect in the p-type field effect transistor because the dopant diffuses too quickly. Or, in the N-type field effect transistor part, the diffusion is not completed due to the slow diffusion of dopants. Therefore, the conventional improvement method is to use different dopant concentrations for doping in different field effect transistors to adjust the diffusion rate of each dopant by using the difference in concentration to avoid dopant diffusion. However, this method is difficult to effectively control the overall process, and the size and shape of the diffused source / drain cannot be fully controlled. In the present invention, it is formed in the P-type field-effect transistor / N-type field-effect transistor according to the ratio of the diffusion rate difference between the two to form a size 7 (please read the precautions on the back before filling this page) Revision: • Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to the Chinese National Standard (CNS) A4 (21〇X 297 public love) 478103 7108twf.doc / 002 A 7 _ 137 _ V. Description of the invention (&Amp;) The first gap wall and the second gap wall are controlled by physical means so that the dopants in the substrate can diffuse uniformly, and a fixed shape source / drain region can be formed, and the whole is improved. Controlling process. In addition, in the present invention, the first gap wall and the second gap wall are formed by two etchings using two layers of different gap wall materials. In this way, the first gap wall and the gap wall can be formed separately by a simple process. The thickness of the second spacer wall is required to reduce the complexity of the process and increase the controllability of the process. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. (Please read the precautions on the back before filling this page). ·-丨 line · Φ Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)