3584twf.doc/008 A7 B7 五、發明説明（f ) 本發明是有關於一種之相容於低電壓元件之胃 件製造方法，且特別是有關於一種以摻雜離子之井（Well) 當作高電壓元件漂移區之高壓元件製造方法。 當元件日益縮小時’隨之縮短的通道長度（channel Length)會使電晶體的操作速度變快，但因通道縮短而衍生 的問題也會日益嚴重，此即所謂的短通道效應、（Sh〇rt Channel Effect)。若施加的電壓不變，而電晶體的通道長 度縮短，根據電場=電壓/長度的公式可以得知，通道內的 電子的能量將會藉由電場增強而提升，進而增加電崩潰 (Electrical Breakdown)的情形。另一方面，若電晶體的通 道長度不變，而電壓增大，電場的強度也會增強，使得通 道內的電子能量提高，同樣會產生電崩潰的現象。 舉例而言，元件做爲高密度數位影音光碟（Digital Versatile Disk ; DVD)和液晶顯示器（Liquid Crystal Display; LCD)的驅動器時，需承受12~30伏特的高電壓。 一般的高壓元件主要是利用隔離層和隔離層下方的漂移區 (Drift Region)，來增加源極/汲極區和閘極之間的距離，使 元件在高電壓的狀況下，仍能正常運作。 第1A-1D圖是習知一種高電壓元件製造流程剖面示意 圖。首先，請參照第1A圖，提供一具有第一型雜質的半 導體基底(未圖示），其中已形成具有第二型雜質的井10。 當第一型雜質是N型雜質時，則第二型雜質是P型雜質； 當第一型雜質是P型時，則第二型雜質是N型。P型雜質 例如是硼或鎵，而N型雜質例如是砷或磷。其次，以加熱 3 本紙張尺度速用中國國家標率（CNS ) Λ4規格（210X297公釐)~" (請先閱讀背面之注意事項苒填寫本頁) 亵------------崎 經Μ部中*#唪局®工坊於合作社印53 A7 3584twf.doc/008 ____ _ _B7_ 五'發明説明（>) 氧化的方式，在井10上形成墊氧化層20。接著，以低壓 化學氣相沉積法（Low Pressure Chemical Vapor Deposition)，在墊氧化層20上，形成氮化砂層30。 其次，請參照第1B圖，進行微影蝕刻步驟，去除部 分未被光阻40覆蓋的氮化矽層30，形成氮化矽層50。接 著，以離子植入法，進行砷植入，形成具有第一型雜質的 漂移區60。 接著，請參照第1C圖，先去除光阻40，然後以溼式 氧化法和使用氮化矽層50做爲罩幕，在漂移區60上和氮 化矽層50兩側，形成鳥嘴(Bird's Peak)外觀的場氧化層 (Field Oxide)70，同時，剛才植入的砷’因高溫而往下驅 入(Drive In)井1〇內，擴大漂移區60。場氧化層7〇的鳥 嘴部分伸入氮化矽層50兩側的下方，使得氮化矽層50兩 側翹起。 然後’請參照1D圖，以溼式蝕刻法，去除氮化矽層 。再以溼式蝕刻法’去除墊氧化層20。接著，以乾式氧 化法，在場氧化層70和井10上，形成一層薄而電性品質 佳的氧化層，用以做爲閘氧化層8〇。然後，沉積一層導電 材料，例如多晶矽，在閘氧化層8〇上，形成多晶矽層， 用以做爲閘極90。然後，進行微影蝕刻步驟，去除未被光 阻覆蓋的多晶矽’留下閘極90。之後，使声離子植入技術， 植入一低濃度且高能量的第一型雜質，接著去除光阻，並 以熱驅入法，形成具有第一型雜質的漂移區100。隨後， 植入一高濃度且低能量的第一型雜質，分別在閘極9〇兩 _____ — 4 本紙張尺度通國家標率（^T^T2丨0X297公釐）---- (請先閱讀背面之汶意事項再填寫本頁) -*1Τ 妗境部屮次榡準局貝Η消费合什社印來 經消部中央標卑局貝工消资合作社印梦 3584twf.doc/008 . « A7 ___________ B7 _ 五、發明説明㈠） —一'''― 側的井ίο表面下，形成源極110和汲極區120。 ^而，如第1D圖所示，習知利用一種漂移區的結構， 以提_朋潰電壓之方法，需多層光罩才能達到要求，消耗 很多製作漂移區光罩的時間與成本，使得生產效率受到限 制。 因此本發明的主要目的就是在提供一種可以與低電壓 元件製造流程相互配合之高電壓元件製造方法，與低電壓 元件之製程相互配’減少所使用的光罩次數，降低循環時 間（Cycle Time)。 爲達成本發明之目的，提出一種相容於低電壓元件之 高電壓元件製造方法，以植入離子之井當作習知高電壓元 件之漂移區來進行高電壓元件之製作，因此可以僅用—個 光罩即可同時定義高電壓元件之部份并與低電壓元件之 井，而不必以一個光罩定義低電壓之井，再以另一光罩定 義高電壓元件之漂移區，省下一道製作漂移區光罩之成本 與時間，降低循環時間3 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉〜較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A-1D圖繪示習知一種高電壓元f牛製造流程剖面示 意圖；以及 第2A_2G圖繪示依照本發明一較佳實施例，一種相容 於低電壓元件之高電壓元件製造方法剖面示意圖。 5 (請先閱讀背面之注意事項再填寫本頁}3584twf.doc / 008 A7 B7 V. Description of the Invention (f) The present invention relates to a method for manufacturing a gastric part compatible with low voltage components, and in particular, to a well doped ion well (Well) as Manufacturing method of high-voltage component in high-voltage component drift region. When the component is shrinking, the channel length shortened will make the transistor operate faster, but the problems caused by the shortening of the channel will become increasingly serious. This is the so-called short channel effect, (Sh〇 rt Channel Effect). If the applied voltage does not change, and the channel length of the transistor is shortened, according to the formula of electric field = voltage / length, it can be known that the energy of the electrons in the channel will be enhanced by the enhancement of the electric field, thereby increasing the electrical breakdown. Situation. On the other hand, if the channel length of the transistor is not changed, and the voltage is increased, the strength of the electric field will be enhanced, so that the energy of the electrons in the channel will be increased, and the phenomenon of electrical collapse will also occur. For example, when a component is used as a driver for a high-density digital video disc (Digital Versatile Disk; DVD) and a liquid crystal display (Liquid Crystal Display; LCD), it needs to withstand a high voltage of 12-30 volts. General high-voltage components mainly use the isolation layer and the drift region under the isolation layer to increase the distance between the source / drain region and the gate, so that the component can still operate normally under high voltage conditions. . Figures 1A-1D are schematic cross-sectional views of a conventional high-voltage component manufacturing process. First, referring to FIG. 1A, a semiconductor substrate (not shown) having a first-type impurity is provided, and a well 10 having a second-type impurity has been formed. When the first-type impurity is an N-type impurity, the second-type impurity is a P-type impurity; when the first-type impurity is a P-type, the second-type impurity is an N-type impurity. The P-type impurity is, for example, boron or gallium, and the N-type impurity is, for example, arsenic or phosphorus. Secondly, use the Chinese National Standard (CNS) Λ4 specification (210X297 mm) to heat 3 papers quickly ~ " (Please read the precautions on the back first and fill in this page) Obscene --------- --- Saki Ward M Department * # 唪 局 ® 工坊 印 53 A7 3584twf.doc / 008 ____ _ _B7_ Five's description of the invention (>) Oxidation method, a pad oxide layer 20 is formed on the well 10. Next, a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition) method is used to form a nitrided sand layer 30 on the pad oxide layer 20. Next, referring to FIG. 1B, a lithography etching step is performed to remove a portion of the silicon nitride layer 30 not covered by the photoresist 40 to form a silicon nitride layer 50. Next, arsenic implantation is performed by ion implantation to form a drift region 60 having a first type impurity. Next, referring to FIG. 1C, first remove the photoresist 40, and then use a wet oxidation method and a silicon nitride layer 50 as a mask to form a bird's beak on the drift region 60 and on both sides of the silicon nitride layer 50 ( Bird's Peak field oxide layer 70, and at the same time, the arsenic implanted just now is driven into the Drive In well 10 by the high temperature, and the drift region 60 is enlarged. The bird's beak portion of the field oxide layer 70 extends below both sides of the silicon nitride layer 50, so that both sides of the silicon nitride layer 50 are lifted. Then, please refer to the 1D diagram and remove the silicon nitride layer by wet etching. Then, the pad oxide layer 20 is removed by a wet etching method. Next, a thin oxide layer is formed on the field oxide layer 70 and the well 10 by a dry oxidation method to serve as the gate oxide layer 80. Then, a layer of conductive material, such as polycrystalline silicon, is deposited, and a polycrystalline silicon layer is formed on the gate oxide layer 80 as the gate electrode 90. Then, a lithography etching step is performed to remove the polycrystalline silicon 'which is not covered by the photoresist, leaving the gate electrode 90. Then, a sono-ion implantation technique is used to implant a low-concentration and high-energy first-type impurity, and then the photoresist is removed, and a drift region 100 having the first-type impurity is formed by a thermal drive-in method. Subsequently, a high-concentration and low-energy type-I impurity was implanted in the gate electrode 90 ° _____ — 4 This paper is up to the national standard (^ T ^ T2 丨 0X297mm) ---- (Please (Please read the matter on the back before filling in this page)-* 1Τ Printed by the Ministry of Health, the Ministry of Health, the Associated Bureau, the Consumers 'Union, and the Central Bureau of Standards, the Ministry of Consumer Affairs, the Beige Consumers' Cooperative, Yinmeng 3584twf.doc / 008 «A7 ___________ B7 _ V. Description of the Invention ㈠) —The wells on the side of '' '′ form a source 110 and a drain region 120. ^ However, as shown in FIG. 1D, it is known to use a structure of a drift region to increase the voltage. A multilayer photomask is required to meet the requirements, which consumes a lot of time and cost for making a mask in the drift region, making production Efficiency is limited. Therefore, the main purpose of the present invention is to provide a method for manufacturing a high-voltage component that can cooperate with the manufacturing process of a low-voltage component, and match the manufacturing process of the low-voltage component. 'Reduce the number of photomasks used and cycle time.' . In order to achieve the purpose of the present invention, a method for manufacturing a high-voltage element compatible with a low-voltage element is proposed. The ion-implanted well is used as a drift region of a conventional high-voltage element to manufacture a high-voltage element. — A photomask can define the part of the high-voltage component and the well of the low-voltage component at the same time, instead of defining a low-voltage well with one photomask, and then defining the drift region of the high-voltage component with another photomask, saving The cost and time of making a mask for the drift region together to reduce the cycle time 3 In order to make the above and other objects, features, and advantages of the present invention more obvious and easy to understand, the following exemplifies ~ preferred embodiments, and cooperates with the drawings Detailed description is as follows: Brief description of the drawings: Figures 1A-1D show a cross-sectional schematic diagram of a conventional high-voltage element manufacturing process; and Figures 2A_2G show a compatible embodiment according to a preferred embodiment of the present invention. Schematic cross-sectional view of a method for manufacturing a high-voltage element on a low-voltage element. 5 (Please read the notes on the back before filling in this page)
本紙張尺度適州肀國國家標埤（rNS)A4^格（2丨〇><297公楚） &漭部中泱榡卑局β-T消於合作社印絮 3584twf.doc/008 A 7 B7 五、發明説明（it ) 圖式之標記說明： 10 、 202 、 206 、 206b :井 2Q、208、208a :墊氧化層 30、50、210 :氮化矽層 40、300 :光阻 60、100 :漂移區 70、212 :場氧化層 80、216、216b :閘氧化層 90、218、218b :閘極 200 :半導體基底 200a:局壓兀件區 200b :低壓元件區 204 :氧化層 220、220b :源極 222、222b :汲極 224 :其它離子摻雜區 實施例 第2A-2G圖繪示依照本發明一較佳實施例，一種相容 於低電壓元件之高電壓元件製造方法剖面示意圖。 請參照第2A圖，在一具有第一型雜質的半導體基底 200,定義一高壓元件區200a與一低壓元件區200b。首先， 以加熱氧化的方式，在半導體基底200上形成氧化層204， 於高壓元件區200a以微影和離子植入技術，植入第二型 雜質，在半導體基底200中形成具有第二型雜質的井202， 6 ---------------訂------絲 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適川中國國家標卒（（’NS ) Λ4規格（210X297公嫠） 3584twf.doc/008 A7 B7 五、發明説明（ir ) 藉高溫擴散，使所植入的離子往下趨入矽底材內。其中當 第一型雜質是N型雜質時，則第二型雜質是P型雜質；當 第一型I雜質是P型雜質時，則第二型雜質是N型雜質。 請參照第2B圖，再以微影和離子植入技術，植入第 一型雜質，於高壓元件區200a之井202中形成兩個具有 第一型雜質的井206,作爲高壓元件源/汲極區在高電壓操 作之漂移區，同時，於低壓元件區200b形成一個具有第 —型雜質的井206b。藉高溫擴散，使所植入的離子往下趨 入砂底材內。 請參照第2C .圖，以蝕刻法去除氧化層204，於含氧 的環境中，以熱氧化的方式形成一層墊氧化層208於半導 體基底200之上，再沉積一層氮化矽層（Si3N4)210，例如 低壓化學氣相沉積法。 請參照第2D圖，進行微影蝕刻步驟，去除部分未被 光阻300覆蓋的氮化矽層210,而留下部份氮化矽層210a， 以供後續場氧化層之製作。 請參照第2E圖，定義並進行離子植入，形成經第二 型離子摻雜的井207，將晶片送入氧化爐管內，利用濕式 氧化法，於含有水氣的環境中，進行場氧化層212的成長。 部份墊氧化層208遭氮化矽層210a所覆蓋，因爲水分子 與氧不易透過氮化矽層210a，因此遭氮化矽層210a所覆 蓋之墊氧化層208不會有二氧化矽的產生，但其他未被氮 化矽層210a覆蓋的部份墊氧化層208，將被氧化而形成由 二氧化矽所構成鳥嘴外觀的場氧化層212。並且，場氧化 7 (請先閱讀背面之注意事項再填寫本頁) -------，tr 經濟部中次榡率局員工消费合作社印裝 ^in a^w 本紙張尺度適用中國國家標率（（、NS ) Λ4規格（210Χ297公釐） 3584twf.doc/008 A7 ______ B7 五明説明（乙) 〜 層212之下爲含第二型離子摻雜的井2〇7。 請參照第2F圖，以溼式鈾刻法，去除氮化矽層21〇 再以懸式蝕刻法，去除墊氧化層208a。接著，以乾式氧化 法，在高壓元件區200a之場氧化層212和井2〇2上，形 成一層薄而電性品質佳的氧化層’用以做爲閘氧化層216。 同時，在低壓兀件區200b之場氧化層212和井206b上， 形成一層薄而電性品質佳的氧化層，用以做爲閘氧化層 216b。 在閘氧化層216、216b上，形成多晶矽層，然後，進 行微影触刻步驟’去除未被光阻覆蓋的部分多晶砂層以做 爲闻電壓兀件之聞極218和低電壓元件之閘極218b。 請參照第2G圖’之後，使用離子植入法，分別在高 電壓元件閘極218兩側的井206表面下與低壓元件區200b 之兩場氧化層212之間、井206的表面下之摻雜區，植入 一高濃度且低能量的第一型雜質，同時在低壓元件區2〇〇b 之閘極218b兩側的井206b表面下植入一高濃度且低能量 的第二型雜質。以完成高壓元件區200a之源極220和汲 極222、低壓元件區200b之源極220b和汲極222b與其它 離子摻雜區224。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 (1)以植入離子之井當作習知高電壓件之漂移區，因 此可以用一個光罩即可同時定義高電壓元件之部份井與低 電壓元件之井，省下一道製作漂移區光罩之成本。 8 本紙张尺度珀用中國國家標.中（CNS ) Λ4規格（210X297公羡） I II (請先閲讀背面之注意事項再填寫本頁) 訂 經满部中决榡準局貞Η消費合作社印製 3584twf. doc/008 A 7 B7 五、發明説明（7) (2) 可以僅用一個光罩即可同時定義高電壓元件之部份 井與低電壓元件之井，如此高電壓元件與低電壓元件有共 同的製程，可以降低製程時間。 (3) 藉由摻雜離子之井當作習之高電壓元件的漂移區， 利用摻雜離子之井所提供不同的電荷傳導特性，得以驅動 各種顯示器所需的電壓値。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (锖先閱讀背面之汰意事項再填寫本頁) 9 本紙張尺度进州中國國家標率（CNS ) Λ4規格（2丨0X297公釐）This paper is a national standard (rNS) A4 ^ (2 丨 0 > < 297 Gongchu) & the Ministry of Health, National Bureau of Justice, β-T disappeared from the cooperative print 3584twf.doc / 008 A 7 B7 V. Description of the invention (it) Symbols of the drawings: 10, 202, 206, 206b: Well 2Q, 208, 208a: Pad oxide layer 30, 50, 210: Silicon nitride layer 40, 300: Photoresist 60, 100: drift regions 70, 212: field oxide layers 80, 216, 216b: gate oxide layers 90, 218, 218b: gate 200: semiconductor substrate 200a: local voltage element region 200b: low-voltage element region 204: oxide layer 220, 220b: Source 222, 222b: Drain 224: Other ion doped regions Embodiments 2A-2G illustrate a method for manufacturing a high voltage component compatible with low voltage components according to a preferred embodiment of the present invention Schematic cross-section. Referring to FIG. 2A, a semiconductor substrate 200 having a first type impurity defines a high-voltage element region 200a and a low-voltage element region 200b. First, an oxide layer 204 is formed on the semiconductor substrate 200 by thermal oxidation. A second-type impurity is implanted in the high-voltage element region 200a by lithography and ion implantation technology, and a second-type impurity is formed in the semiconductor substrate 200. Well 202, 6 --------------- Order ------ Silk (Please read the precautions on the back before filling in this page) This paper is suitable for China National Standards (('NS) Λ4 specification (210X297) 嫠 3584twf.doc / 008 A7 B7 V. Description of the invention (ir) The implanted ions are pushed down into the silicon substrate by high temperature diffusion. Among them, the first type When the impurity is an N-type impurity, the second-type impurity is a P-type impurity; when the first-type I impurity is a P-type impurity, the second-type impurity is an N-type impurity. Please refer to FIG. 2B, and then use lithography and Ion implantation technology implants first-type impurities, and forms two wells 206 with first-type impurities in the well 202 of the high-voltage element region 200a as the drift region of the high-voltage element source / drain region operated at high voltage, and A well 206b with a first-type impurity is formed in the low-voltage element region 200b. The implanted ions are caused to diffuse by high temperature diffusion. The bottom layer is moved into the sand substrate. Referring to FIG. 2C, the oxide layer 204 is removed by etching. In an oxygen-containing environment, a pad oxide layer 208 is formed on the semiconductor substrate 200 by thermal oxidation, and then deposited. A silicon nitride layer (Si3N4) 210, such as a low pressure chemical vapor deposition method. Referring to FIG. 2D, a lithographic etching step is performed to remove a portion of the silicon nitride layer 210 that is not covered by the photoresist 300, leaving a portion The silicon nitride layer 210a is used for the production of subsequent field oxide layers. Please refer to Figure 2E to define and perform ion implantation to form a second type ion-doped well 207, and send the wafer into the oxidation furnace tube for use. In the wet oxidation method, the field oxide layer 212 is grown in an environment containing water vapor. Part of the pad oxide layer 208 is covered by the silicon nitride layer 210a, because water molecules and oxygen cannot easily pass through the silicon nitride layer 210a, so The pad oxide layer 208 covered by the silicon nitride layer 210a will not generate silicon dioxide, but other parts of the pad oxide layer 208 not covered by the silicon nitride layer 210a will be oxidized to form a silicon dioxide layer. The field oxide layer 212 constituting the appearance of the bird's beak. Hua 7 (Please read the precautions on the back before filling out this page) -------, tr Printed by the Consumers ’Cooperatives of the Ministry of Economic Affairs, China ’s Ministry of Economic Affairs ^ in a ^ w (, NS) Λ4 specification (210 × 297 mm) 3584twf.doc / 008 A7 ______ B7 Wuming description (B) ~ Under layer 212 is a well 207 containing a second type ion doping. Please refer to FIG. 2F, The silicon nitride layer 21 is removed by a wet uranium etching method, and the pad oxide layer 208a is removed by a suspension etching method. Next, a thin oxide layer ′ is formed as a gate oxide layer 216 on the field oxide layer 212 and the well 202 of the high-voltage element region 200a by a dry oxidation method. At the same time, a thin oxide layer with good electrical quality is formed on the field oxide layer 212 and the well 206b of the low-voltage element region 200b as the gate oxide layer 216b. On the gate oxide layers 216 and 216b, a polycrystalline silicon layer is formed, and then a lithography step is performed to remove a portion of the polycrystalline sand layer not covered by the photoresist to serve as the gate of the voltage sensing element 218 and the gate of the low voltage element. Pole 218b. After referring to FIG. 2G, the ion implantation method is used between the surface of the well 206 on both sides of the high-voltage element gate 218 and between the two field oxide layers 212 of the low-voltage element region 200b and the surface of the well 206. A high-concentration and low-energy first-type impurity is implanted in the impurity region, and a high-concentration and low-energy second-type impurity is implanted under the surface of the well 206b on both sides of the gate 218b of the low-voltage component region 200b. . The source 220 and the drain 222 of the high-voltage element region 200a, the source 220b and the drain 222b of the low-voltage element region 200b, and other ion-doped regions 224 are completed. As can be seen from the above-mentioned preferred embodiments of the present invention, the application of the present invention has the following advantages. (1) The well with implanted ions is used as the drift region of the conventional high-voltage components, so a photomask can be used to define some wells of high-voltage components and wells of low-voltage components at the same time. Cost of photomask. 8 This paper scale uses the Chinese national standard. China (CNS) Λ4 specification (210X297). I II (Please read the precautions on the back before filling out this page.) 3584twf. Doc / 008 A 7 B7 V. Description of the invention (7) (2) It is possible to define part of the wells of high-voltage components and wells of low-voltage components at the same time with only one photomask, so that high-voltage components and low-voltage The components have a common process, which can reduce the process time. (3) By using the ion-doped well as the drift region of the conventional high-voltage element, the different charge conduction characteristics provided by the ion-doped well can be used to drive the voltages required for various displays. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (锖 Please read the description on the back of the page before filling in this page) 9 This paper is scaled into the state China National Standards (CNS) Λ4 specification (2 丨 0X297 mm)