TW476117B - Method to achieve larger L-shape spacer width - Google Patents

Abstract

In the spacer etching step of the sub-micron composite spacer process, plasma will attack corner. This makes spacer width very sensitive to the over etching time during the conventional composite spacer etching process, which leads to reduced spacer width and affects device performance if the spacer width is too short. In the inventive spacer process, a silicon nitride film is deposited on the TEOS layer for a conventional composite semiconductor thin-film substrate completed front end process. The deposited silicon nitride film, regarded as a sacrificial layer, will protect side wall of the TEOS layer during etching step to obtain a vertical TEOS layer profile. Therefore, maximum spacer width can be retained to achieve the effect of improved device performance after repetitive etching steps in the process.

Description

476117

Field of the Invention = The present invention is related to the manufacturing process of semiconductor devices, especially the method for making composite spacers using sub-micron technology. BACKGROUND OF THE INVENTION: An integrated circuit includes millions of components formed in a specific area, and these components are connected using electrical conductive interconnects to perform a special function. In order to achieve high-performance integrated circuits or increase the density of wafers, the size of semiconductors is getting smaller and smaller. As the size of components is getting smaller, the electrical connection structure connecting semiconductor components has become more and more Precision. MOS is one of the most widely used components in integrated circuits. The so-called MOS (Metal-Oxide Semiconductor) is a combination of three different materials, including electronic lightning strikes (0) and semiconductor layers (S). The M 0 S transistor is basically a metal oxide semiconductor transistor consisting of a gate, a source, and a four-terminal electronic component hole. It is mainly composed of a metal layer (M) and an oxide. It is a kind of junction electrode and substrate electrode. In order to achieve high-performance metal oxide semiconductor transistors, their size has also been continuously meeting the requirements of the current industry competition trends, such as the current requirements for components must be higher: higher operating speed, and lower operating power, then #, easy It is affected by the time delay of the impedance Rc and the contact resistance between the electrode and the source. Performance: When the M0S element is smaller, the length of the channel will follow. W due to the blue 476117 of the transistor. 5. Description of the invention (2) The speed of the operation will be faster. Problems caused by the reduction of the channel length began to occur, causing the starting voltage (vt) to drop, the gate applied voltage to control the non-polar current of the Mos transistor, and the increase in the number of hot electrons, leading to more load. Doubling of electrons, problems such as Elec tri cal Breakdown, Hot Electron Effects, etc., collectively referred to as the Short Channel Effect. 〇To solve the thermionic effect of short-channel MOS transistor elements, currently A widely adopted solution in the industry is to add a set of doped sources and η-type regions where the source and non-polarity of the original Mos are close to the channel. , Called ldd (slightly doped drain,

Light Doped Drain). The electric field distribution of M0S with LDD design will move to the drain 'and the electric field will be lower than that of M0S without LDD design, so the influence of the thermoelectronic effect can be reduced. In addition, the effect of the thermoelectronic effect on Another effect is that the electrons generated by the impact of thermionic electrons are mostly absorbed by the drain, and some electrons will move across the interface of the silicon dioxide layer to the gate. Most of these electrons will be trapped in the oxide layer. The charge of the oxide layer is changed, and it continues to increase with the operation of Mos, which results in a change in the starting voltage. The design of LDD can also reduce the occurrence of such problems. Generally, the manufacturing method of M0S transistor is to generate an open-electrode dielectric and a silicon structure on a semiconductor substrate, so that the surface of the semiconductor substrate is at least exposed to the device.

476117 V. Description of the invention (3) In the source and drain regions, a permeable diffusion barrier is created on the surface of the region used by the source and drain regions to form a doped layer. The heterolayer covers the range of the f source and drain regions, the surface of the diffusion barrier that can be doped and the surface of the silicon structure, and the silicon structure is doped so as to form the gate electrode through the diffusion of the doped layer, and the source electrode The drain region can be formed at the same time through the diffusion of the doped layer, wherein the dopant substance will diffuse and pass through the permeable diffusion barrier. Tetraethyl silicate (TE0s) is commonly used in the production of MOS.

Si02LPCVD reaction ’because of the step coverage of TEOS-Si02 (step

Coverage) ability is very good, has been widely used in the semiconductor industry, such as "Spacer" (Spacer), because the production of the barrier wall, the metal layer used to make contact has not been deposited, so the reaction temperature will not It has a great impact on the manufacturing process or other characteristics of the entire component, such as the distribution of infiltration. In the conventional technology, please refer to Figure 1A ~ Figure 1D. First, the process has been completed in Figure 1A. On the semiconductor substrate 100, gate oxide layer 101 and gate complex crystal layer 102 are formed through successive deposition, lithography, and etching steps. The gate compound layer 102 is fabricated by an ion implantation method with an acceleration voltage of 15 to 25 KeV. LDD103 containing N; an oxide film 104 was deposited by low pressure chemical vapor deposition (LPCVD), the reaction gas is TE0S, the deposition temperature is about 650 ~ 750 ° C, and the operating pressure is 1 ~ 5 t 〇rr; Plasma chemical vapor deposition (pecv D) was used to deposit a silicon nitride layer 105. The reaction gas was Si H2C12, the deposition temperature was about 250 ~ 400 ° C, and the operating pressure was 5torr; a TE0S was deposited by LPCVD. -

Page 6 476117 V. Description of the invention (4) The oxide layer 106 is TEOS, the deposition temperature is about 650 ~ 750 C, and the operating pressure is 1 ~ 5torr. Next, please refer to FIG. 1B. After the etching formula using CHF3 and 02 as the reaction atmosphere, the etching selection ratio is Bu 2. The original TEOS layer 107 has a rounded arc profile after etching. The width of the gap wall is also reduced to dl ', which indicates that the gap wall width will become shorter and shorter as the over-etching time increases, and the width and the over-etching time have a linear relationship. Next, please refer to FIG. 1C. In the next step, a spacer (〇xide) 10 is used as an etching curtain, and an etching formula using CH3F and CF4 as a reaction atmosphere is used. The etching selection ratio is about 10. The original L type The gap wall gap width d 1 is further shortened to d 2. After the silicon nitride is etched, the gap wall does not shrink entirely because the selective etching with high silicon nitride is used for the silicon nitride etching. Fig. 1D After removing the TE0S layer through the HF pickling step, the final l-type gap wall width is shown as d2, and the final gap wall width d2 is smaller than the original film deposition width. The subsequent ion implantation step with an acceleration voltage of 30-40KeV is implanted with N + to form two electrodes of MOS, source 107 and drain 108. At this time, it already contains LDD and can be connected to metal化 process. Therefore, in the sub-micron composite spacer process and the spacer etching step, the plasma will attack the corner, so that the shape of the silicon nitride layer becomes more arc-shaped after being etched, so it is etched in the traditional composite spacer. Process

Page 7 476117 5. In the description of the invention (5), the width of the spacer is very sensitive to the Over Etching time, which also reduces the width of the spacer. Too short the width of the spacer will directly affect the performance of the device . Purpose and summary of the invention: The purpose of the present invention is to improve the manufacturing method of the width of the L-shaped gap wall, to improve the traditional L-shaped gap wall manufacturing process in the past. The effect of short channels, maximize the effectiveness of the component.

In the L-shaped gap wall process, a silicon nitride film is further deposited on the TEOS layer on the conventional composite semiconductor thin film substrate that has completed the previous process, which is regarded as a sacrificial layer. This nitride layer is passed through During the engraving process, the sidewall of the TE0S layer (Sidewal 1) will be protected, and a vertical TE0S layer profile will be obtained, so that even after repeated etching steps in the process, the original maximum gap wall width can be maintained to improve the component. Efficacy. Therefore, the independent width after etching can be obtained during the etching process of the composite spacer. Although there is one more procedure than the traditional process, the etching method does not need to be completely changed, and only modification is required. Detailed description of the invention: The present invention is different from the traditional traditional partition wall manufacturing process, which has been completed in Figure 2A

Page 8 476117 V. Description of the invention (6) On the semiconductor substrate 200 in the previous process, the gate oxide layer 2 01 and the gate compound layer 2 002 are formed by successive deposition, lithography, and engraving steps. Generally, the gate oxide layer 201 can be in an oxygen-containing environment at a temperature of 750 to 丨 丨 00. Oxidation is formed between rhenium, and the thickness is generally about 15 ~ 60 A, or the gate oxide layer 2 01 can be completed by using CVD. Subsequently, a chemical vapor deposition method was used to deposit a polycrystalline silicon layer 200 covering the gate oxide layer 201 with a thickness of 2000 A, and then a photoresist pattern was defined on the polycrystalline silicon layer 202. The last name is the polycrystalline stone layer 200 and the gate oxide layer 201 to define the pattern of the gate structure, and then remove the photoresist. Next, the gate structure is used as a mask for ion implantation, and ions are implanted into the substrate 200 using an ion implantation technique with an acceleration voltage of 15-25KeV, and a side containing N- is formed near the gate. Slightly doped the drain (LDD) 2 0 3 to reduce the hot carriers in the channel. An oxide film 204 is deposited by LPCVD with a thickness of about 80 A, the reaction gas is TEOS, the deposition temperature is about 650 ~ 750 ° C, and the operating pressure is 5torr; the silicon nitride layer is deposited by PECVD, with a thickness of 2.5 About 400 ~ 500 A, its reaction gas is usually Si H4, NH3, N2, N20 or Si H2C 12, NH3, N2, N20, deposition temperature is about 2 50 ~ 4 0 0 ° C, operation The pressure is Bu 5torr; a TEOS-oxide layer 206 is deposited by LPCVD, the thickness is about 600 ~ 800 A, the reaction gas is TE0S, and the deposition temperature is about 650 ~ 750 C. The operating pressure is 1 ~ 5torr.

Page 9 476117 V. Description of the invention (7) And on the composite spacer film, a sacrificial layer of silicon nitride 207 'is deposited by PECVD to a thickness of about 150 ~ 250 A, and the reaction gas is SiH4, NH3, N2, N2 〇 or SiH2Cl2, NH3, N2, N20, the deposition temperature is about 250 ~ 400 ° C, the operating pressure is Bu 5torr. The above-mentioned double-spacer width composed of the oxide stone layer 206 and the nitride stone layer 205, and the width of the silicon nitride sacrificial layer 207 can be controlled by individually depositing the oxide stone layer and the silicon nitride layer. Determined by thickness. Next, please refer to FIG. 2B, which is the main etching reaction. Using TEOS #etching selectivity close to nitride stone, the plasma etching method is selected as the etching method, and the etching formula is CHF3 and CF 4 as the reaction atmosphere. The etching selection ratio is 丨~ 2, forming a nitride wall at the TE 0 S margin. Figure 2C shows the TE0S over-etching reaction. Using high TE0S silicon nitride etching selectivity, the plasma etching method is selected by plasma etching, and He and CD are the main etching atmospheres. Its surname engraving selection ratio is about 5, and the te0S after etching. The width from the margin to the gate is d3. As shown in FIG. 1D, in the silicon nitride etching step, a spacer (0xide) 205 is used as an etching mask, and plasma etching is selected by using a high-silicon-TEOs * etching selectivity method to select CH3F and 〇2 are the main etching atmospheres. The #etching selection ratio is greater than 1 〇, and the contour is still maintained after silicon nitride etching.

Page 10 476117 V. Description of the invention (8) Leaving 'The width of the L-shaped gap wall and the width between the TEOS margin and the gate are the same as d3. In FIG. 2E, the TEOS layer 206 is acid-washed and removed with hydrofluoric acid (HF), and finally a first barrier wall 2 made of silicon oxide is formed on the side wall of the gate structure, and the second barrier wall 2 is formed. 0 5 is above the side wall of the first gap wall 204, and the final L-shaped gap wall width still appears as d3, which shows that the L can be controlled by the thickness of the sacrificial layer film by splitting the film wall width in the compound gap Gap wall width. Subsequently, an ion implantation step with an L-shaped barrier gate structure is used, and an ion implantation step with an acceleration voltage of 30 to 40 KeV is implanted. Two electrodes of N +, MOS, source 208 and drain 2 are implanted. 〇9, at this time has been followed by the metallization process. Figure 3A shows the SEM photo of the stunned person, bamboo stove, K, p, and sigmoid, as shown in Figure 2A. The SEM photo of the width of the wall of the recognition / special film / children's product gap has been completed. On the semiconductor substrate 2000, a gate electrode Ί :: dead crystal layer 202 is formed on the semiconductor substrate 200 by lithography, lithography, and etching steps, and an inclusion is formed on the near side. The complex compound 203, the oxide film 2 04, the doped nitride layer 205, and the doping of the silicon nitride layer 205: and: the silicon nitride sacrificial layer 207. At this time, the silicon nitride anchor emulsion layer 206, the gate width is 1 3 2 5 I, and the sacrificial layer is perpendicular to the margin of the sacrificial layer. FIG. 3B is a photo using the method of the present invention. As shown in the figure, the L-shaped gap wall after the final gap is pulled and deposited on the composite gap wall film is ^ ^ 1 2 5 A, which proves that the sacrificial layer 2

476117 V. Description of the invention (9) After repeated etching steps, the L-shaped spacer wall width is still effective. Compared with the previous process, a larger spacer wall width can be obtained. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. For those skilled in the art, modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Page 12 476117 Brief description of the drawings Figure 1A is a cross-sectional view of a conventional thin film system deposited by a composite film. Figure 1B is a cross-sectional view of the effect of the width of the spacer wall with the over-etching time in a conventional TEOS etching step. Figure 1C is a cross-sectional view of a conventional spacer manufacturing process after silicon nitride etching. As shown in Fig. 1D, after the traditional process steps of the partition wall, the sectional view of the L-shaped partition wall is finally presented. As shown in FIG. 2A, a sacrificial layer is deposited on the composite spacer film. Figure 2B shows a cross-sectional view of a silicon nitride spacer formed on the TEOS margin after the main etching step. As shown in FIG. 2C, after the TEOS over-etching step, a cross-sectional view of a small silicon nitride spacer wall remains. As shown in FIG. 2D, a cross-sectional view of the outline after the silicon nitride is etched is still retained. Fig. 2E is a cross-sectional view of the width of the gap wall after TEOS is removed by pickling. FIG. 3A is an SEM photograph of the width of the barrier wall of the composite film in FIG. 2A. Fig. 3B is a SEM photograph of the final L-shaped spacer after the etching step is performed after using the method of the present invention. %

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Claims (1)

476117 VI. Application Patent Scope 1 A method for obtaining a larger L-shaped spacer wall width, the method at least comprises: forming a gate dielectric layer on a semiconductor substrate; forming a polycrystalline silicon layer on the gate dielectric layer Etch the polycrystalline silicon layer and the gate dielectric layer using a lithography and etching process to form a gate structure, and use a deposition process to deposit a first dielectric layer and a second dielectric on the completed polycrystalline silicon gate An electrical layer and a third dielectric layer film; forming a sacrificial layer film on the third dielectric layer film; after the main etching process, the sacrificial layer forms a small gap wall on the margin of the third dielectric layer; forming a first L Type spacers on the side wall of the gate structure, and second L-type spacers on the side wall of the first spacer to form a double spacer structure surrounding the gate structure; performing an ion implantation to form the source and The drain is in the semiconductor substrate. 2. The method according to item 1 of the scope of patent application, wherein the first dielectric layer mentioned above must have a different etching selectivity ratio than the second dielectric layer. 3. The method according to item 1 of the scope of patent application, wherein the above-mentioned second dielectric layer must have a different etching selection ratio than the third dielectric layer. 4. The method according to item 1 of the patent application range, wherein the sacrificial layer film described above contains a nitride. Page 14 476117 6. Scope of patent application 5 The method according to item 1 of the scope of patent application, wherein the sacrificial layer film mentioned above must have a different etching selection ratio from the third dielectric layer. 6. The method according to item 1 of the patent application range, wherein the first partition wall mentioned above contains an oxide. 7. The method according to item 1 of the patent application range, wherein the above-mentioned second partition wall contains a nitride. Among the above-mentioned sacrificial layer films, the above-mentioned method of the sacrificial layer film described in item 1 of the scope of application includes a method of forming using LPCVD. 9 The method according to item 1 of the scope of patent application The formation method includes the use of PECVD. 10. The method according to item 1 of the scope of patent application, wherein after forming the above gate structure, it further comprises forming a lightly doped drain in the substrate. Engine Page 15