TW473952B - Structure for reducing flip-chip package stress - Google Patents

Structure for reducing flip-chip package stress Download PDF

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Publication number
TW473952B
TW473952B TW90102289A TW90102289A TW473952B TW 473952 B TW473952 B TW 473952B TW 90102289 A TW90102289 A TW 90102289A TW 90102289 A TW90102289 A TW 90102289A TW 473952 B TW473952 B TW 473952B
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Taiwan
Prior art keywords
flip
stress
patent application
scope
reducing
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TW90102289A
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Chinese (zh)
Inventor
Pei-Hua Tsau
Jr-Chiang Chen
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Taiwan Semiconductor Mfg
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Priority to TW90102289A priority Critical patent/TW473952B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Abstract

The present invention discloses a kind of structure for reducing the flip-chip package stress. At first, a chip with upside down is provided and is connected with a package base board through a solder bump. Then, the glue-shaped underfill is used to fill the gap in between. After that, the surface having wave-shaped stiffener is formed at the edge of the base board in order to decrease the base board warpage and relieve the stress. At last, a heat spreader is used to cover the top of the wave-shaped stiffener, and solder balls connected with system are formed on the other side of the base board.

Description

473952 五、發明說明（1) 發明領域： 本發明係關於一種覆晶（Flip Chip ;FCM公# . 的結構，ϋ ϊ,ϊ β «tv φ . )封裝技術 的構#別疋關於-種減少覆晶封袈應力的結構改良。 發明背景： 按，i C封裝的主要功能包括··保護c、 ， (ch 1 ρ)和外界系統裝置之間訊息傳遞的介面，所/以本 因系ί產品的功能性都是影響IC封裝技術發展的 產品的要求是輕薄短小，就要有減少 Z '寸的技術，IC製程微細化，造成晶粒内包含的邏 輯線路增加，就要想辦法在晶粒外多增加_些輸入與輸出 信號的腳位。由於這些需求的林林總總造成;許多^ ^的 新一代的封裝方式，如：球柵陣列（BGA)、晶片尺寸封裝 (CSP )、多晶片模組（multi_chip module ; MCM )、覆 曰曰 曰曰 (FC )等先進技術應運而生。其中覆晶封裝由於減少了 片至外界系統裝置之間訊息傳遞的路徑距離，而具有較 佳的電氣特性，成為頗受矚目的下一世代封裝技術。 印參閱圖一，為一典型的覆晶封裝結構示意圖，晶粒 1的正面朝下和基板（substrate)3上的焊接凸塊（s〇ider bump)5相連’然後把膠狀的填裝物（1111(161^丨11)7充滿其間 的孔隙再加以固化以增加焊接凸塊的強度，基板 (substrate)3另一面則是與系統相連的錫球（s〇lder ba 11) 9 ’因為基板與晶粒的熱膨脹係數之間的差異，在填 473952 五、發明說明（2) 裝物固化之後此封裝結構不可避免的會產生彎曲，對小尺 寸的覆晶封裝結構而言，這彎曲形變程度或許尚在可容許 的範圍之内’但對大尺寸的所謂高效能（high performance)覆晶封裝結構而言，這彎曲形變程度必須推 辦法加以控制了。 、心 通常的解決方法是在基板3的邊緣，加上一塊支揮用 的^板（stiffener)i3並用膠帶（或膠）u黏在基板上再 覆盍上散熱板（heat sink)或是散熱片（heat s一preaderMS，以增加此封裝結構的散熱能力，如圖二所 不，如此一來就可以減少基板因熱膨脹所產生的彎曲了。 所述夾板（stiffener)13—般是金屬材質的平面薄板並在 中央區域有著適當的開孔以避開晶粒，然而，這 卻因為夾板（5衍{&1^〇13的存在而增加了晶粒盥焊接° 塊接面之間，以及焊接凸塊與基板接面之間的應力 (^tress)，反而會影響了封裝結構及焊接凸塊^面可靠 的”结構進-步加 發明之概述： 本發明之主要目的是提供一種減少覆曰 構，以提昇覆曰曰曰封裝結構及焊接凸塊接龙裝應力的結 w j罪性。 '11 473952 五、發明說明（3) 一- ^，明的另一目的是提供一種減少覆晶封裝應力的結 構’藉著形成表面具有波浪狀夾板（stif fener)，以減少 基板因熱膨服所產生的彎曲了。 本發明係使用下列結構來達到上述之各項目的：首 先’如同習知技藝般在一已完成超大型積體電路元件之晶 粒將其正面朝下，並透過焊接凸塊（s〇lder bump)與一封 裝基板（substrate)相連，然後把膠狀的填裝物 (under f i 11)充滿其間的孔隙再加以固化以增加焊接凸塊 ^ 的強度。 ® ' 1 ί 接下來的敘述，為本發明之重點所在，藉著形成表面 具有波浪狀夾板（stiffener)在基板的邊緣，一方面減少 \ 了夾板在單位面積的質量以纾解應力，但因夾板之轉動慣丨 量並未因為面積減少而相對減少，故減低基板彎曲的效果 並未因而減低，另一方面同時又增加了上表面的面積，而 增加了此封裝結構的散熱能力，以減少基板因熱膨脹所產 生的彎曲，一舉兩得的解決了習知結構的種種缺點，最 後’在波浪狀夾板（sti f fener)之上覆蓋一散熱片之後，』 再形成與系統相連的錫球（solder bal 1)於基板的另一 面，本發明所述之一種減少覆晶封裝應力的結構於焉完 成。 、、、473952 V. Description of the invention (1) Field of the invention: The present invention relates to the structure of a flip chip (Flip Chip; FCM). Ϋ ϊ, ϊ β «tv φ. Structural improvement of flip chip sealing stress. Background of the invention: According to the main functions of the i C package, the protection of the message transmission interface between c,, (ch 1 ρ) and external system devices, so the functionality of the product is affecting the IC package. The requirements for technology-developed products are light, thin, and short. Z'-inch technology is required. The IC process is miniaturized, which increases the number of logic circuits included in the die. It is necessary to find ways to increase the number of inputs and outputs outside the die. Signal pins. Because of these requirements, many new generation packaging methods, such as: ball grid array (BGA), chip size package (CSP), multi-chip module (MCM), cover ( FC) and other advanced technologies came into being. Among them, flip chip packaging has better electrical characteristics because it reduces the path distance of information transmission between the chip and external system devices, and has become a next generation packaging technology that has attracted much attention. Please refer to Figure 1. It is a schematic diagram of a typical flip-chip package structure. The front side of the die 1 is connected to the solder bump 5 on the substrate 3, and then the gel-like filling material is connected. (1111 (161 ^ 丨 11) 7 fills the pores in between and then solidifies to increase the strength of the solder bumps, and the substrate 3 (substrate) 3 is a solder ball (solder ba 11) connected to the system 9) 9 'Because the substrate The difference between the coefficient of thermal expansion of the crystal and the grain, after filling 473952 V. Description of the invention (2) The package structure will inevitably bend after the package is cured. For small-sized flip-chip package structures, the degree of bending deformation Maybe it is still within the allowable range ', but for the so-called high-performance flip-chip packaging structure of large size, the degree of bending deformation must be controlled by pushing. The usual solution is to use the substrate 3 Edge, add a stiffener i3 and use tape (or glue) u to adhere to the substrate, and then overlay a heat sink or heat sink (preaderMS) to increase this. Thermal performance of package structure The force, as shown in Figure 2, can reduce the bending of the substrate due to thermal expansion. The stiffener 13 is generally a flat metal plate with appropriate openings in the central area to avoid Die, however, this is due to the presence of the plywood (5 衍 {& 1 ^ 〇13, which increases the stress between the die joints and the solder joints, and between the solder bumps and the substrate joints (^ tress ), But it will affect the package structure and the reliability of the structure of the solder bump. "The structure of the step-by-step plus invention is summarized. The main purpose of the present invention is to provide a reduced structure to improve the package structure and solder bump. The sin nature of the block solitaire stress. '11 473952 V. Description of the invention (3) A-^, Ming another purpose is to provide a structure to reduce the stress of flip-chip packaging 'by forming a surface with a wavy plywood (stif fener) to reduce the bending of the substrate due to thermal expansion. The present invention uses the following structure to achieve the above-mentioned objectives: First, 'as is known in the art, a crystal of a large-scale integrated circuit element has been completed. Straighten it Facing downwards and connected to a packaging substrate through solder bumps, and then filling the voids there between with a gel-like filler (under fi 11) and then curing to increase the solder bumps ^ Strength. ® '1 ί The following description is the focus of the present invention. By forming a surface with a wavy stiffener on the edge of the substrate, on the one hand, the mass of the splint in a unit area is reduced to relieve stress. However, because the moment of inertia of the splint has not been relatively reduced due to the reduction in area, the effect of reducing the bending of the substrate has not been reduced. On the other hand, the area of the upper surface has been increased, which increases the heat dissipation capacity of the packaging structure. In order to reduce the bending of the substrate due to thermal expansion, the two disadvantages of the conventional structure are solved in one fell swoop, and finally 'after a heat sink is covered on the sti fender,' a solder ball connected to the system is formed ( solder bal 1) On the other side of the substrate, a structure for reducing the stress of a flip-chip package according to the present invention is completed. ,,,

第6頁 ^PSd52 么發明說明（4) 圖式間要說明： 圖一為習知技藝覆晶封裝結構之示意圖。 |圖二為習知技藝高效能覆晶封裝結構之示意圖。 |圖二為覆晶封裝結構焊接凸塊之示意圖。 圖四（a)(b)(c)為本發明實施例波浪狀夾板之示意圖。 圖五為本發明實施例高效能覆晶封裝結構之示意圖。 ! I圖號說明： 1 -晶粒 I | 5-烊接凸塊 9 -錫球 | 1 3 -夾板 I 2卜護層 i 23-焊墊 53-銅墊 發明詳細說明： 3 -基板金屬接塾 7 -填裝物護層 U-膠帶 1 5 -散熱板 5 1 -金屬凸塊 52-焊錫球 本發明是有關於覆晶球拇陣列（flip — chip ball grid array ; FC-BGA)封裝的結構，在詳細說明中是運用具體實 施例說明本發明的原則與精神。 以下之實施例將自已完成超大型積體電路元件之晶粒 製作後開始描述，所述晶粒1表面有一層護層 (passivation layer)21並打開若干開口提供焊墊（bondPage 6 ^ PSd52 Description of the invention (4) To be explained between drawings: Figure 1 is a schematic diagram of a flip chip package structure of the conventional art. | Figure 2 is a schematic diagram of a high-performance flip-chip packaging structure with conventional techniques. | Figure 2 is a schematic diagram of a solder bump of a flip-chip package structure. Figure 4 (a) (b) (c) is a schematic diagram of a wave-shaped plywood according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a high-performance flip-chip packaging structure according to an embodiment of the present invention. Description of I drawing number: 1-die I | 5-connecting bump 9-solder ball | 1 3-plywood I 2 protective layer i 23-solder pad 53-copper pad Detailed description of the invention: 3-substrate metal connection塾 7-Filler protective layer U-tape 1 5-Heat sink 5 1-Metal bump 52-Solder ball The present invention relates to a flip-chip ball grid array (FC-BGA) package The structure, in the detailed description, uses specific embodiments to explain the principles and spirit of the present invention. The following embodiments will be described after the fabrication of the dies for the ultra-large integrated circuit components has been completed. The surface of the dies 1 has a passivation layer 21 and opens several openings to provide bonding pads.

第7頁 473952 五、發明說明（5) ~ pad)23用作信號的輸入與輸出，接續，形成金屬凸塊 (metal bump)51於晶粒之銲墊結構上，然後，再藉由焊錫 球52及銅墊53與基板3相連接，其中所述金屬凸塊、焊錫 球和銅墊的複合層就是前述之焊接凸塊（s〇lde：r bump)5， 其尺寸大小一般是銲塾直徑約為100 mm的圓形，而高度約 | 為7 5 mm，如圖三所示，所述金屬凸塊51可使用金或鉛錫合| 金（PbSn alloy)。 然後，把膠狀的填裝物（uncler π π )7充滿其間的孔隙1 再加以固化以增加焊接凸塊的強度，接下來的敘述，為本丨 發明之重點所在，藉著形成表面具有波浪狀夾板 (stiffener)13在基板3的邊緣，一方面減少了夾板在單位： 面積的質量以抒解應力，但因夾板之轉動慣量並未因單位； 面積減少而相對減少，故減低基板彎曲的效果並未因而減； 低’另一方面同時又增加了上表面的面積，而增加了此封| 裝結構的散熱能力，以減少基板因熱膨脹所產生的彎曲\丨 一舉兩得的解決了習知結構的種種缺點。 i 所述夾板（stiffener)的波浪狀，鋸齒典、溝 | 渠^、網1等各1凹凸不平的起.伏，而波浪狀的位置可以i 在夾板的上表面13a如圖四（A)所示，也可以在夾板的下表 面13b如圖四（B)所示，或甚至同時存在於夾板的上下表面 1 3 c如圖四（C)所示，至於波浪狀的形成方式則可以利用姓 刻、機械工具、鑄模或是直接用外力撞擊均可。Page 7 473952 V. Description of the invention (5) ~ pad) 23 is used as the input and output of the signal. Then, a metal bump 51 is formed on the die pad structure. Then, the solder ball is used. 52 and the copper pad 53 are connected to the substrate 3, wherein the composite layer of the metal bump, solder ball and copper pad is the aforementioned solder bump (solder: r bump) 5, and its size is generally about It is a circle of 100 mm, and the height is about 75 mm. As shown in FIG. 3, the metal bump 51 may be made of gold or lead-tin alloy (PbSn alloy). Then, the gel-like filling (uncler π π) 7 is filled in the pores 1 between them and then cured to increase the strength of the welding bumps. The following description is the main point of the invention. By forming the surface with waves The shape of the stiffener 13 on the edge of the substrate 3 on the one hand reduces the number of splints in the unit: the mass of the area to express the stress, but because the moment of inertia of the splint is not due to the unit; the area is reduced, so the substrate bending is reduced. The effect has not been reduced; on the other hand, the area of the upper surface has been increased at the same time, and the heat dissipation capacity of the package structure has been increased to reduce the bending caused by the thermal expansion of the substrate. Various disadvantages. i The wavy shape of the stiffener, jagged, groove | canal ^, net 1 and other undulations, and the wavy position can be i on the upper surface 13a of the splint as shown in Figure 4 (A) As shown, it can also be shown on the lower surface 13b of the plywood as shown in Fig. 4 (B), or even exist on the upper and lower surfaces of the plywood 1 3c as shown in Fig. 4 (C). As for the wavy formation method, it can be used Last name engraving, machine tool, casting mold or direct impact with external force.

第8頁 473952 五、發明說明（6) 最後，形成與系統相連的錫球（solder ball)9在基板 (substrate)3的另一面，若是要進一步增加此封裝結構的 散熱能力，可以在波浪狀夾板（st i f f ener)之上覆蓋著散 熱板15(或是散熱片），並用膠帶11加以固定如圖五所示， 本發明所述之一種減少覆晶封裝應力的結構於焉完成。 綜上所述 1.本發明之覆 力。 2 ·本發明之覆 (stiffener 3 ·本發明之覆 轉動慣量並 彎曲的效果 4 ·本發明之覆 (stiffener 裝結構的散 曲0 ’本發明所提供較習知技術具有下列優點： 晶封裝結構，可以具有較佳的形變控制能 晶封裝結構，由於具有波浪狀夾板 )’減少了單位面積的質量以纾解應力。 曰曰封攻結構由於具有波浪狀夾板，因夹板之 未因單位面積減少而相對減少，故減低基板 並未因而減低。 晶封裝結構，由於具有波浪狀夾板 )，增加了上表面的面積，因而增加了此封 熱能力，也減少基板因熱膨脹所產生的f 矛用較佳實施例詳細說明本發明，而韭萨 制本發明的範圍，闵比' ^ ^ ^ 个知月，而非限 而作些微的改變啟辋敕 丄丄 化月匕明瞭，適當 不脫離本發明之牆说 文我所在，亦 申和範圍，故都應視為本發明的進一步 473952 五、發明說明（7) 實施狀況。謹請 貴審查委員明鑑，並祈惠准，是所至 禱0Page 8 473952 V. Description of the invention (6) Finally, a solder ball 9 connected to the system is formed on the other side of the substrate 3. If the heat dissipation capability of this packaging structure is to be further increased, it can be formed in a wave shape. The stiffener is covered with a heat sink 15 (or a heat sink) and fixed with an adhesive tape 11 as shown in FIG. 5. A structure for reducing the stress of a flip-chip package according to the present invention is completed. To sum up 1. The coverage of the present invention. 2 The cover of the present invention (stiffener 3) The effect of the cover of the present invention on the moment of inertia and bending 4 The cover of the present invention (the deflection of the stiffener mounting structure 0 'The present invention provides the following advantages over the conventional technology: crystal package structure, It can have a better deformation control energy crystal packaging structure, because it has a wave-shaped plywood) 'reduced the mass per unit area to relieve stress. Due to the wave-shaped plywood, the closed-tapping structure, because the plywood has not been reduced due to the unit area Relatively reduced, so the substrate is not reduced. The crystalline package structure, because it has a wavy plywood), increases the area of the upper surface, thus increasing the heat sealing ability, and reducing the use of the substrate due to thermal expansion. The examples illustrate the present invention in detail, and the scope of the invention made by the chives is not less than ^^^^ months, but not limited to make a slight change. The wall says that where I am, and also the scope, it should be regarded as a further 473952 of the present invention. V. Description of the invention (7) Implementation status. I would like to ask your reviewing committee to make a clear reference and pray for the best.

第10頁 473952 圖式簡單說明 圖式簡要說明： 圖一為習知技藝覆晶封裝結構之示意圖。 圖二為習知技藝高效能覆晶封裝結構之示意圖。 圖三為覆晶封裝結構焊接凸塊之示意圖。 圖四（A)(B)(C)為本發明實施例波浪狀夾板之示意圖。 圖五為本發明實施例高效能覆晶封裝結構之示意圖。Page 10 473952 Brief description of the drawings Brief description of the drawings: Figure 1 is a schematic diagram of the flip chip packaging structure of the conventional art. FIG. 2 is a schematic diagram of a high-performance flip-chip packaging structure according to conventional techniques. FIG. 3 is a schematic diagram of a solder bump of a flip-chip package structure. FIG. 4 (A) (B) (C) is a schematic diagram of a wave-shaped plywood according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a high-performance flip-chip packaging structure according to an embodiment of the present invention.

秦 第11頁Qin Page 11

Claims (1)

473952 六、申請專利範圍 申請專利範圍： V 1· -種減少覆晶封裝應力的結構，係包括：丨 一晶粒’其表面有著護層（passivation)及複數個金屬焊 丨 墊結構； 一封裝基板； ； 複數個焊接凸塊（s〇Uer bump)以連接所述晶粒之金屬焊 I 墊與所述封裝基板； I 至少一個波浪狀夾板（s t i f f e n e r)介於所述晶粒與所述封 裝基板之間。 2 ·如申請專利範圍第1項所述之減少覆晶封裝應力的結 j 構，更包括一散熱板覆蓋於所述夾板及所述晶粒的上表 面0 3 ·如申請專利範圍第1項所述之減少覆晶封裝應力的結 ! 構，其中波浪狀係位於所述夾板的上表面。 卜4·如申請專利範圍第1項所述之減少覆晶封裝應力的結 構，其中波浪狀係位於所述夾板的下表面。 5 ·如申請專利範圍第1項所述之減少覆晶封裝應力的結 構，其中波浪狀係位於所述夾板的上下表面。 6 ·如申請專利範圍第1項所述之減少覆晶封裝應力的結 構，其中所述波浪狀是溝渠狀。 I 7·如申請專利範圍第1項所述之減少覆晶封裝應力的結 I 構，其中所述波浪狀是鋸齒狀。 | 8 ·如申請專利範圍第1項所述之減少覆晶封裝應力的結 構，其中所述波浪狀是網狀。 I 473952 六、申請專利範圍 一 9 · 一種減少覆晶封裝應力的結構，係包括： 一晶粒，其表面有著護層及複數個金屬焊墊結構； " 一封裝基板； 複數個悍接凸塊以連接所述晶粒之金屬焊墊與所述封裝基 板； 至少一個波浪狀夾板介於所述晶粒與所述封裝基板之間’ i 其中波浪狀係位於所述夹板的上表面。 + 10·如申請專利範圍第9項所述之減少覆晶封裝應力的結 構，更包括一散熱板覆蓋於所述夾板及所述晶粒的上表 面。 广 11·如申請專利範圍第9項所述之減少覆晶封裝應力的結 構，其中所述波浪狀是溝渠狀。 P 12·如申請專利範圍第9項所述之減少覆晶封裝應力的結 丨_ 構，其中所述波浪狀是錄齒狀。 1 3 ·如申請專利範圍第9項所述之減少覆晶封裝應力的結 構，其中所述波浪狀是網狀。 1 4 · 一種減少覆晶封裝應力的結構，係包括： 一晶粒，其表面有著護層結構及複數個金屬焊塾結構； 一封裝基板； 複數個焊接凸塊以連接所述晶粒之金屬焊墊與所述封裝基ι· 板； ” 4 至少一個波浪狀夾板介於所述晶粒與所述封奘美板 其中波浪狀係位於所述爽板的上下表^裝基板之間 15 ·如申請專利範圍第丨4項所述之減少覆晶封裝應力的結473952 VI. Scope of patent application Patent scope: V 1 ·-A structure to reduce the stress of flip-chip packaging, including: 丨 a die with a passivation on the surface and a plurality of metal pads; a package; A substrate; a plurality of solder bumps to connect the metal pads of the die to the package substrate; I at least one stiffener between the die and the package Between substrates. 2 · The structure for reducing the stress of a flip-chip package as described in item 1 of the scope of patent application, further including a heat dissipation plate covering the upper surface of the splint and the die 0 3 · As item 1 of the scope of patent application The structure for reducing stress of a flip-chip package, wherein the wavy system is located on the upper surface of the plywood. Bu 4. The structure for reducing the stress of the flip-chip package according to item 1 of the scope of the patent application, wherein the wavy system is located on the lower surface of the plywood. 5. The structure for reducing the stress of the flip-chip package according to item 1 of the scope of the patent application, wherein the wavy system is located on the upper and lower surfaces of the plywood. 6 · The structure for reducing the stress of a flip-chip package according to item 1 of the scope of the patent application, wherein the wave shape is a trench shape. I 7. The structure for reducing stress of a flip-chip package as described in item 1 of the scope of the patent application, wherein the wave shape is a sawtooth shape. 8 · The structure for reducing the stress of a flip-chip package as described in item 1 of the scope of patent application, wherein the wave shape is a mesh shape. I 473952 VI. Scope of patent application 9 · A structure for reducing the stress of flip-chip packaging, including: a die, the surface of which has a protective layer and a plurality of metal pad structures; " a package substrate; A block to connect the metal pads of the die with the package substrate; at least one wavy plywood is interposed between the die and the package substrate; where the wavy system is located on the upper surface of the plywood. + 10 · The structure for reducing the stress of a flip-chip package according to item 9 of the scope of the patent application, further comprising a heat sink covering the upper surface of the plywood and the die. Guang 11. The structure for reducing the stress of a flip chip package as described in item 9 of the scope of the patent application, wherein the wave shape is a trench shape. P12. The structure for reducing the stress of a flip-chip package as described in item 9 of the scope of the patent application, wherein the wave shape is a tooth shape. 1 3 · The structure for reducing the stress of a flip-chip package as described in item 9 of the scope of patent application, wherein the wave shape is a mesh shape. 1 4 · A structure for reducing the stress of a flip-chip package, comprising: a die with a protective layer structure and a plurality of metal welding pads on its surface; a package substrate; a plurality of solder bumps to connect the metal of the die Solder pads and the packaging substrate; "4 at least one wavy plywood is interposed between the die and the sealed beautiful board, wherein the wavy system is located between the upper and lower surfaces of the cool board 15; Junction to reduce the stress of the flip chip package as described in item 4 of the patent application 第13頁 473952 六、申請專利範圍 構，更包括一散熱板覆蓋於所述夾板及所述晶粒的上表 > 面。 ·· 16. 如申請專利範圍第14項所述之減少覆晶封裝應力的結 構，其中所述波浪狀是溝渠狀。 ; 17. 如申請專利範圍第14項所述之減少覆晶封裝應力的結 | 構，其中所述波浪狀是鑛齒狀。 18. 如申請專利範圍第14項所述之減少覆晶封裝應力的結 構，其中所述波浪狀是網狀。 髒Page 13 473952 6. The scope of the patent application structure further includes a heat sink covering the upper surface > of the splint and the crystal grains. ·· 16. The structure for reducing the stress of a flip-chip package according to item 14 of the scope of the patent application, wherein the wave shape is a trench shape. 17. The structure for reducing the stress of a flip chip package as described in item 14 of the scope of the patent application, wherein the wavy shape is a dentate shape. 18. The structure for reducing the stress of a flip-chip package according to item 14 of the scope of patent application, wherein the wave shape is a mesh shape. dirty 第14頁Page 14
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