TW472458B - Multi-stage comparator with auto-zero - Google Patents

Abstract

The present invention proposes plural differential amplifiers directly connected in series. The output of each stage is proceeded with auto-zero operation in the first period by the way of negative feedback, and provide bias voltage to the amplifier in the same stage in the second period to proceed the input value comparison of the stage. Thereby, auto-zero and comparison are proceeded sequentially according to the stage number sequence of each amplifier, so as to stabilize the bias point of the comparator in each period, and also to reduce the offset voltage and switch noise of the amplifier in each stage.

Description

4 ^ 2458

The present invention relates to a multi-stage comparator with auto-zero, and more particularly to a comparator used in an analog-to-digital converter (ADC) and a comparison method thereof. 2Background of the Invention: Among the two cars, the necessary and the multi-device-the value of existence. Set-up period The period of charge is usually far away. Comparator is commonly used in electronic circuits to compare the magnitude of the input signal value. For example, in an analog-to-digital circuit (ADC), a comparator must be used as one of its components. The traditional comparator has a single stage. The diagram shown in Figure A is the traditional single stage comparison. Ideally, a differential amplifier should produce a differential output with a value of zero when it enters into a differential wheel. However, in practice, differential amplifiers should inevitably have an offset voltage of 'Traditionally using a differential amplifier 丨 0, it will be stored in the capacitor Caz via the feedback path between the offset compensation (or between the doubles (as p 1 and p 2 shown in the first B diagram), and from p2 to p3 Compare ^ This stored charge is used to compensate the differential amplifier 10. Because the traditional single = f uses-stage amplification, its gain value needs to be higher (pass ^ y. Therefore, 'offset its offset (offset ) The voltage and charge are also too large. In addition, the capacitor CAZ J controls the influence of the clock drift. In addition, the input

472458 V. Description of the invention (2) The individual common mode (common mode) voltages of the terminal voltages VN, VP and the node voltages VNh νρ are likely to be different, thus resulting in different offset (〇ffset) voltages. Even during the offset compensation period between p 1 and P2, stability problems may be caused because the amplifier uses unit gain and its negative feedback path. Zhong Yu here 'Most of the traditional comparators use a multi-stage series connection. The second figure shows a schematic diagram of a traditional multi-stage (two-stage) comparator, and its control clock is similar to that shown in the first B diagram. Although the multi-stage comparator can be used to reduce the gain of the mother stage to reduce the bias (0ffse1 :) voltage and switch noise, however, according to the following formula:

Va2 = Val x (Cc / (Cc + C)) will make the voltage of Va2 less than Val, which will cause the sensitivity of the comparator to decrease, increase the response time, and thus reduce the operating speed. The third diagram A, the third diagram B, and the third diagram c show another schematic diagram of a conventional multi-stage (three-stage) comparator. Its control clock is similar to that shown in the first 8 diagram. Therefore, the comparator generates a digital output after three stages of processing, and then directly feeds back the parasitic current from the last stage to the bias input terminal β I AS and Β IASN 'to achieve the compensation of the bias voltage The biggest disadvantage of this comparator is that its DC bias voltage is easy to drift off, causing the bias points during the compensation period and the comparison period to be inconsistent, so it cannot be normal

472458 V. Description of the invention (3) Operation. In view of the shortcomings mentioned above, it is urgent to propose a comparator, which can not only effectively reduce the amplifier offset voltage and switch noise, but also ensure the bias during the automatic offset compensation period and the comparison period. The voltage at the pressure point can be kept stable, and the response time (reaction time) can be reduced to improve the operation speed. 5-3 Purpose and Summary of the Invention: II In the above background of the invention, many shortcomings of traditional single-stage or multi-stage comparators are produced. The present invention aims to propose a multi-stage comparator with automatic offset compensation to reduce Offset voltage of the amplifier and switch noise. Another object of the present invention is to provide a multi-stage comparator whose bias point voltage can be kept stable during the automatic offset compensation period and the comparison period. ^ It is still another object of the present invention to provide a multi-stage comparator, in which a direct series connection between stages is used to reduce the reaction time (r e s p o n s e t i m e) to increase the operating speed. According to the above-mentioned object, the multi-stage comparator system provided by the present invention

Page 6 472458 V. Description of the invention (4) A plurality of differential amplifiers are connected in series, and the output terminal of each differential amplifier is directly connected to the input terminal of the next-stage differential amplifier. For each stage amplifier ', a set of capacitors are connected to the positive output terminal and the negative output terminal of the amplifier of the same stage through a feedback path, respectively. According to the number of stages of the amplifier, a switching device is used to form a closed loop (clOsed) of the feedback path for charging the capacitor, thereby achieving automatic offset correction (aut0_zer0) of each stage of the amplifier. Then, during the comparison period, it is coupled and provides a bias voltage to the amplifier of the same stage, so that the bias point of the comparator will not drift, so as to ensure the normal operation of the comparator. 5-4 Detailed description of the invention: The fourth diagram A shows two stages according to the present invention, ^ as λα ^ ^ _ V, ^ ~ ... double auto-zero offset (auto-zero) 2 = the fourth diagram B is for the time being Pulse control signal diagram. Although: the two-stage comparator 4 is used as the preferred embodiment of the present invention, ㈣ 'is still included in the protection scope of the present invention; that is, the wooden structure of the present invention can be applied to other multi-level people'. Occasion. Furthermore, although the embodiment of the comparator of the present invention is used in Danyou # 夂 桊 发 a, ηπ, Α is also used in the analog to digital circuit (ADC), the comparator of the present invention can also be used with the 1J image. Suitable for other applications. As shown in Figure 4A, the two cores p, + git & two-stage benefit 4 are mainly composed of differential operational amplifiers 4 U and 4 2.. Π Μ 1 0 * «A k Cheng 'Among them, the positive output private and negative output ends of the first stage differential amplifier 40 are respectively pulled by the rubbish pine knife and the J is later connected to the second stage differential amplifier 42

472458 V. Description of the invention (5)-Negative input and positive input. It is worth noting that the connection mode of the amplifiers at all levels does not have to be the same as that shown in this embodiment, and the change of the connection mode will not affect the main operation of the present invention. Since the comparators of each level in the invention are directly coupled in series, the response time can be reduced to improve the operation speed. Generally, after the last stage of the multi-stage amplifier 4, a latch circuit (Utch) 44 is added, which can be used to raise the output signal level of the comparator to the level of the power supply or to pull it down to ground. It is used to maintain (h 〇 d) the state or potential of the signal within a predetermined time. In this embodiment, 'differential input k number V sum and V sumr are respectively input to the positive input terminal and the negative input terminal of the differential amplifier 40 through the input and the valley trough Ci n', and then the signal is transmitted by the differential amplifier 40. Magnified, the phase difference of the amplified differential output signal is 180 degrees. Because a multi-stage amplifier is used, the gain (ga i η) value of each stage of the amplifier can be designed and controlled so as not to be too large. For example, the gain value is set to be less than 10. This can reduce the offset electrical house and switch noise of the amplifier. The output of the 'differential amplifier 40 is then connected to capacitors C1A and C1B via switches 46A and 46B in a negative feedback manner, respectively. Generally, the switches 46A and 46B are implemented by a transmission gate (TG), and other switching devices can also be applied. During the auto-zero period (or reset period) of 11 to 12 (picture 4B), switches 46A and 46B will be closed (closed), so capacitors C1A and cib are charged. .

Page 8 472458 V. Description of the invention (6) As each level performs automatic offset correction, the previous level will perform the automatic offset correction before the next level, so it can ensure that the offset (Of f set) electric house is effective. Elimination or compensation. During the comparison from t2 to t3, another set of switches 47A and 47B is closed and the charged capacitors ci A and C1B provide the bias voltage required by the differential amplifier 40, as shown Nodes BIAS and BIASN. In the present invention, the bias voltage of each stage of the comparator is independently generated and provided, so that the DC bias points of the amplifiers of each stage can be maintained stable and consistent during the autozero period and the compare period. There will be no bias drift to ensure the normal operation of the comparator. The connection and operation of the second-stage differential amplifier 42 is the same as that of the first-stage differential amplifier 40, and its output is connected to the capacitors C2A and C2B through switches 48A and 48B in a negative feedback manner, respectively. During the auto-zero period from t3 to t4 (figure B), the switches 48A and 48B will be closed 'so that the capacitors C2A and C2B are charged. During the comparison after t4, another set of switches 49A and 49B is closed and the charged capacitors C2A and C2B provide the bias voltage required by the differential amplifier 42. The fifth figure shows the internal structure of the differential amplifier 40 (or 42) and the external negative feedback path. Current source circuit 4 0 1

472458 V. Description of the invention (7) The current supply in part of it, the drive circuits 4 0 3 A and 4 0 3 B are used to amplify the signals of the positive input terminal and the negative input terminal of the amplifier, respectively. The amplifier 40 has fixed loads 405 A and 405B 'connected to corresponding driving circuits 403A and 403B, respectively, for generating output signals of the positive and negative output terminals of the amplifier 40. It is particularly noted that the 'amplifier 40 has bias loads 407A and 407B' in parallel to the fixed load 405 stage 405B, respectively; among them, the load values of the bias load 40 7A and 4 0 7B are controlled by the bias input βΙΑ ^ BI ASNi, respectively. The sixth figure shows the detailed circuit of the two-stage amplifier 40, 42 of the present invention, which is 2 °. Among them, the current source circuits of the first and second stages are respectively 421 and 421; the drive circuits are 403 and 423; fixed. Negative 405B and 407A and 407B are all connected to Gutang's posture soil; ^ Since Lifan, Baifan, Baiye has received the reference voltage VREF of Gute. Bias The load size is 40 7A, 4〇7β in the first stage, and 0 in the second stage. The load value is subject to the bias input (also

And the second level (MAS1, BIASN1), the first level of _, MASN seventh A, seventh B, and seventh c process technology, respectively, in differential input, ten or three different shapes, get The analog timing diagram of the two-stage comparator = the waveform between the age of 13 represents the first-stage comparator #, and the waveform after time 11 to 11 represents the output signal of the second-stage comparator The simulation timing diagram of the eighth figure C is similar to the eighth figure of the eighth J and the eighth B. The difference is that the differential wheel input signal is changed to two; Description of the invention (8) It is obvious that after two stages of automatic offset compensation have been completed sequentially, the offset voltage of the differential output signal has been significantly compensated (or reset). In view of the above description of the embodiment of the present invention, it can be understood that the present invention utilizes a multi-stage comparator directly connected in series, wherein each stage sequentially performs automatic offset correction, bias voltage and execution voltage comparison respectively, thereby reducing response time. To increase operating speed. Because the gain (ga i η) of each stage of the amplifier can be designed and controlled so as not to be too large, the bias voltage (of fset) of the amplifier and switch noise can be reduced. Moreover, the bias voltage of each stage of the comparator is generated and provided separately, so that the DC bias points of the amplifiers at all levels can maintain stability and consistency during the aut0-zero period and the comparison period. There will be no bias drift to ensure the normal operation of the comparator. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

472458 Brief description of the diagram The first diagram A shows a schematic diagram of a traditional single-stage comparator. The first B diagram shows the clock control signal diagram of the first A diagram. The second figure shows a schematic of a traditional multi-stage (two-stage) comparator. Figures A, B and C show another schematic diagram of another conventional multi-stage (three-stage) comparator. The fourth diagram A shows a system diagram of a two-stage auto-zero comparator according to the present invention. The fourth diagram B shows the clock control signal diagram of the fourth diagram A. The fifth figure shows a schematic diagram of the internal architecture of each stage of the differential amplifier of the present invention. The sixth diagram shows a detailed circuit implementation diagram of the two-stage amplifier of the present invention. Figures 7A, 7B, and 7C respectively show the analog timing of the two-stage comparator for three different process technologies when the differential input signal is 20 m V. Illustration. Figures A, B, and C show the three different

Page 12 472458 The diagram briefly describes the process technology. The analog timing diagram of the two-stage comparator is obtained when the differential (d i f f r e n t i a 1) input signal is 2 m V. Symbols of main parts: 4 two-stage auto-zero comparator 1 0 traditional single-stage differential amplifier 40 first-stage differential amplifier 42 second-stage differential amplifier 44 latch (1 atch) circuit 46A, 46B switch 47A, 47B switch 48A, 48B switch 49A, 49B switch 4 0 1 (first stage) current source circuit 4 2 1 (second stage) current source circuit 403 (403A, 403B) (first stage) drive circuit 4 2 3 (second stage) drive circuit 40 5A, 40 5B (first stage) fixed load 425A, 425B (second stage) fixed load 40 7A, 4 0 7B (first stage) bias load 427A, 427B (first stage) Two-level) bias load

Caz capacitor C i η input capacitor C1A, C1B capacitor

Page 13 472458

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Claims (1)

472458, patent application scope 1. A multi-stage comparator with auto-zero, including at least a positive number of differential amplifiers in series, each differential amplifier has a positive pull-in and a negative input Terminal, and has a positive output terminal and a negative output terminal-each of the positive output terminal and the negative output terminal of the differential amplifier is connected to the negative input terminal and the positive input terminal of the differential amplifier in the next stage; Each group of the capacitors is connected to the positive output terminal and the negative output terminal of the same-stage differential amplifier through a feedback path, respectively. A multi-array first switching device is located in the feedback path, and the _th switching device According to the number of stages of the plurality of differential amplifiers connected in series, the feedback path is closed so as to charge the electric valley device, thereby achieving automatic compensation of each of the differential amplifiers. Auto-zero; and > Number New · Second switching devices are respectively connected to the charging capacitor, according to the order of the number of stages of a plurality of differential amplifiers in series, the corresponding corresponding capacitors are sequentially And electrically coupled to provide a bias charge to the same level differential amplifier, thereby generating the final stage differential amplifier in a comparator output signal, respectively. 2 · For example, please refer to the multi-stage comparator of item 1 of the patent, in which the phase difference between the positive output terminal and the negative output terminal of the differential amplifier is about 180 degrees. 3. The multi-stage comparator according to item 1 of the patent application range, wherein the differential amplifier is a differential operational amplifier (differential operational amplifier). Page 15 472458 Case No. 89116488 6. Patent Range Amplifier] Amendment 4. If the multi-stage comparator of the first patent range is applied, it also includes a device connected to the last stage of the differential amplifier, which is used to convert the difference. The output signal level of the amplifier is raised to the level of the power supply, or pulled down to ground. 5. If the multi-level comparator of item 4 of the scope of patent application, the above-mentioned device is used to maintain (h ο 1 d) the state of its input signal for a predetermined period of time. A multi-stage comparator, in which the above device includes a latch circuit. 7. If the multi-stage comparator of item 1 of the scope of patent application, wherein the first switching device and the second switch device mentioned above each include a transmission gate ° difference 8. As much as of the scope of patent application item 1 Level comparator, in which the gain (gai η) of each of the amplifiers is less than about 10. 9. A multi-stage comparator with automatic offset correction (aut 〇- zer 〇), including at least a plurality of comparators connected in series, each stage of the comparator has a positive input terminal and a negative input terminal, and has a positive output terminal And a negative output, each of the comparators has at least: Page 16 472458 VI. Patent application range Current source device 'for providing current supply to other parts of the comparator'> First drive device 'for amplifying the signal of the positive input terminal; Second drive device' for Amplify the signal of the negative input terminal; a first fixed load connected to the first driving device to generate an output signal of the positive output terminal; a second fixed load connected to the second driving device and To generate an output signal of the negative output terminal; a first bias load 'is connected in parallel to the first fixed load, and the load value of the first bias load is controlled by a first bias input; a second bias The load 'is connected in parallel to the second fixed load, and the load value of the second bias load is controlled by a second bias input; the first feedback filter device is connected to the first feedback path through a first feedback path Between the first driving device and the first bias load for generating an auto-zero charge, and then controlling the first bias input with the charge, thereby making the first drive The bias value of the device is maintained substantially stable; and a second feedback filtering (fi Iter) device is connected between the second driving device and the second bias load through a second feedback path for generating an automatic Compensation bias (aut〇-zer〇) charge 'Parallel uses the charge to control the first-low voltage input', thereby making the bias value of the second driving device roughly 俾 不 词 · steady 1 〇. As applied The multi-stage comparator of item 9 of the patent 472458 6. The patent application scope feedback filtering device includes at least: an automatic bias compensation switch device, which sequentially forms a closed circuit during the automatic bias compensation (au t 〇-zer 〇) sequence according to the number of stages of the plurality of comparators connected in series. (Closed), so that each of the comparators achieves automatic offset correction automatically; an automatic offset correction capacitor connected to the automatic offset correction switch device to be charged during the automatic offset correction; a bias switch device connected in series to the automatic offset correction device The bias switching device is formed in accordance with the number of stages of the plurality of comparators connected in series in order to form a closed circuit during the comparison (comparance) in order to provide the first bias input of the comparator of the same level. The multi-stage comparator of item 9, wherein the above-mentioned second feedback filtering device includes at least: an automatic offset compensation switch device, which is in accordance with the number of stages of the plurality of comparators connected in series, and performs auto-zero compensation. During this period, a closed circuit (c 1 〇sed) is formed in sequence, so that each of the comparators achieves automatic offset compensation; an automatic offset capacitor is connected to the automatic offset switching device. The bias switching device is connected in series to the automatic bias switching device, which is sequentially formed in accordance with the number of stages of the plurality of comparators connected in series during the comparison period. Closed circuit to provide the second bias input of the comparator of the same level 1 2. As the multi-stage comparator of item 9 of the scope of patent application, the above comparison Page 18 472458 Case No. 89116488 A_η 6. Scope of patent application The phase difference between the positive output terminal and the negative output terminal of the device is about 180 degrees. 1 3. The multi-stage comparator of item 9 in the scope of patent application, wherein the above-mentioned comparator is a differential operational amplifier ° 1 4. The multi-stage comparator of item 9 in the scope of patent application, further including A device is connected to the comparator of the last stage, and is used to raise the output signal level of the comparator to the level of the power source, or pull it down to the ground potential. 15. The multi-level comparator of item 14 in the scope of patent application, wherein the above device is used to maintain (ho 1 d) the state of its input signal for a predetermined period of time. 16. The multi-stage comparator of item 15 in the scope of patent application, wherein the above device includes a latch circuit. 17. The multi-stage comparator of item 10 in the scope of patent application, wherein each of the above-mentioned automatic bias switching device and bias switching device includes a transmission gate. 18. If the multi-stage comparator of item 11 of the scope of patent application, wherein the above-mentioned automatic bias switching device and bias switching device each include a transmission gate circuit (transmission gate) ° Page 19 472458 VI. Patent application scope 1 9. The multi-stage comparator of item 9 of the patent application scope, wherein the gain (g a i η) value of each of the above comparators is less than about 10. 2 0. — A multi-level comparison method for automatic offset correction (aut 〇-zer 〇), including at least a positive input signal and a negative input signal; amplifying the positive input signal and the negative input signal to generate a positive output Signal and a negative output signal; feedback the positive output signal and the negative output signal respectively during the first offset period to achieve the first level of automatic offset correction; during the first comparison period, the positive input signal and the negative The input signal is compared at the first level, and a bias voltage is provided by the feedback so that the bias voltages in the offset period and the comparison period are approximately equal; and sequentially in the subsequent offset period and the subsequent comparison period It is used for automatic offset correction of the lower stage, providing bias voltage and numerical comparison, whereby the positive output signal and negative output signal generated in the last stage are the final comparison output signals. 2 1. The method according to item 20 of the scope of patent application, wherein the magnification of the positive input signal and the negative input signal is less than about 10%. 2 2. The method according to item 20 of the scope of patent application, wherein the phase difference between the positive output signal and the negative output terminal is about 180 degrees. Page 20 Page 21