TW472328B - Damascene processing for cap layer with low temperature and low power deposition - Google Patents

Abstract

The present invention discloses a manufacturing method for damascene structure on the semiconductor substrate which includes the following steps: first, forming a low-k material layer on the semiconductor substrate; conducting the plasma chemical vapor deposition in an environment with the temperature at about 10 to 70 degree C and the power at about 50 to 120 watts to form the carbon-doped oxide layer on the low-k material layer as the CMP cap layer; next, etching the carbon-doped oxide and the low-k material layer to form the opening pattern therein and expose part of the surface of semiconductor substrate. The carbon-doped oxide can protect the underneath low-k material layer from damage in the etching process; then, form the conductive damascene structure in the opening pattern.

Description

472328 V. Description of the invention g) 'One'-Field of the invention: The present invention and a method for making a copper damascene structure in a semiconductor process include P, in particular, a layer of porous low-dielectric constant material in the application of "Porous" "redundant" A low-temperature / low-power covering layer is deposited thereon to prevent the 1 ow-k film layer from being damaged under the plasma environment when there is a > covering layer, and voids are generated. BACKGROUND OF THE INVENTION:

Ik continues the progress of the semiconductor industry. In the development and design of ultra large integrated circuits (ULSI), ‘in order to meet the design trend of high-density integrated circuits’, the size of various components has been reduced to sub-micron. And due to the continuous shrinking of components, 'many defects or problems that can be ignored in traditional technology, in the process of subtle production, there will be relative amplification effects, making the process conditions more stringent, and related Semiconductor processes are also more complex. In general, in order to effectively isolate conductive elements in integrated circuits, a large amount of dielectric materials are often applied to produce the required insulation effect. Therefore, in the traditional semiconductor manufacturing process, a large amount of materials such as silicon oxide, silicon nitride, and silicon oxynitride are used to construct the dielectric layer required in the integrated circuit. However, as process sizes continue to shrink, metal patterns are arranged in a more dense manner, which in turn leads to a significant increase in parasitic capacitance in the entire integrated circuit. As a result, the operating characteristics of the produced components will be affected improperly.

Page 4 472328 V. Description of the invention (2) The response of the integrated circuit is reduced and the use efficiency and lifetime of the integrated circuit are reduced to form a semiconducting k). The metal map will be more focused, and the dielectric coefficient can be reduced by the product method, which will also reduce the dielectric required in the parasitic process. However, the case will be more stringent, and the use of high deposition is required. material. However, it encountered phase capacitance, extensive electrical layers, and upcoming dense demands. It is produced for the low-dielectric molecular polymerization. The influence of the insulation layer is 0.10. Therefore, it is difficult to apply the dielectric material to the dielectric system. In the current low-media, in order to improve the micron with the current materials to make, the number of about 2. Some porous minimum ruler about 0.1 13 microelectric coefficient of material (10 watts supply process of about less than 3 and In other words, there is a lot of research in the related field of dielectrics of semiconductors based on dielectric materials. It may be a low-porosity material with a chemical vapor deposition of 0 ~ 2.5. The words “the materials on the semiconductor substrate have been defined in advance. A masking layer is deposited on the plasma-enhanced dielectric material. Then, after the etching process, the ashes can be defined” It is possible to supply a semiconductor substrate by using a chemical connection to a porous low-dielectric constant material, and in a half-material layer and various functional elements. Deposition of a silver etch stop layer and porous low-strength chemical vapor deposition ) Materials such as nitrided stone or carbonized stone are used for the masking layer and the porous dielectric material port pattern. Generally speaking, 'except the particle plating (electrical chemical Then the substrate body, the dielectric constant can be 1 in the lithography using the CMP of porous ash or debris

Page 5 472328 V. Description of the invention (3) plating; ECP) process, depositing a copper layer in the opening pattern. Subsequently, a chemical-mechanical polishing (CMP) process was performed in Saskatchewan to remove the excess copper metal material 'to define the copper damascene structure at the opening pattern. It is worth noting that, for porous low dielectric constant materials, when they are in a plasma environment, they are easily damaged by ion impact, and the overall structure becomes extremely fragile. Taking the above copper damascene process as an example, when the PECVD process is used to deposit the cover layer, the entire porous dielectric sound is exposed to the plasma environment, so the material structure will be damaged to a considerable degree. As a result, in the subsequent CMP process, the stress may be unevenly applied to the porous dielectric layer, which may cause voids ′ and reduce the process yield. Please refer to the first picture, which shows a photo related to the use of a silicon nitride material as the covering layer. Because when depositing a silicon nitride film layer, a is often introduced with a gas of about 0,03 sccm, and is deposited in an environment with a temperature of about 400 and a frequency of about 600 watts. Therefore, too high power and a large amount of ammonia gas will aggravate the damage to porous low dielectric constant materials. Therefore, as shown in the first figure, the completion of the CMP process to isolate the porous low-dielectric constant material 4 of the steel damascene connection 2 often results in many voids 6 and reduces the yield of the process. s — purpose and summary of the invention:

472328

The present invention = the main purpose is to provide a method of making copper mosaic structures, in which the use of PECVD procedures at low temperatures and low power conditions, using carbon oxides as a masking layer, can be avoided in porous low electrical coefficient materials The purpose of creating void defects in the layer. _ This method. Firstly, the material layer ratio is about 50 to plasma chemistry, which is used as the material layer, and it is exposed to protect the bottom damage. Subsequently, a mosaic substrate is manufactured on the material above the middle layer of the mouth pattern, and a porous gas is formed at a temperature of about ˜70 t and the work (CxHy) z gas is formed, and an oxide layer is etched on the porous material layer to contain a stone reaction. An oxide layer and a porosity to form an opening pattern thereon. Among them, the carbon-containing oxide layer can be damaged on the surface of the CMP process and filled in the sequence to remove the carbon-containing oxide structure in the opening pattern. The invention discloses a method for forming an etch stop layer on a semiconductor substrate on a semiconductor conductive stop layer. Then, in a 150-watt environment, Si vapor deposition was used to form a carbon-containing layer for use as a cover layer. Next, until the etch stop layer was reached, a portion of the porous material layer on the surface of the semiconductor substrate was exposed. Avoid 'depositing the conductive layer with carbon-containing oxidation. Then perform part of the chemical mechanical polishing process on the conductive layer and define the inlay. For detailed descriptions, please refer to the second figure. First, provide a single crystal silicon substrate with <100> crystal orientation. 10 In general, other types of semiconductor materials, such as gallium arsenide, germanium, or sUicon on insulator (S0I) on the insulation layer can be used as this &amp;

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Optional: Conductor substrate 10 is used. In addition, 's' does not cause a special shadow direction due to the special invention of the surface of the semiconductor substrate, and its crystal choice is &lt; 110> or &lt; 111>. Generally, various active components, passive components, peripheral circuits, and the like required for integrated circuits are often defined in advance on the semiconductor substrate 10. In other words, on the surface of the semiconductor substrate 10, there are already various functional layers and material layers. Therefore, an etch stop layer 12 may be formed on the semiconductor substrate 10 first, so as to protect various components or material layers below. Then, a low-k material layer 14 may be deposited on the etch stop layer 12. In the pot, choose materials such as BD, CORAL, SiLK, Flare, HSQ, Nanogl; ss, etc .; _ materials with low dielectric, (K value) to make, and in the preferred embodiment, can be selected and used A polymer or chemical vapor deposition process is used to form a porous material to form the low-dielectric-constant material layer 14 here. Next, a plasma enhanced chemical vapor deposition (PECVD) process can be used to deposit a carbon-doped oxide 16 on the low-dielectric-constant material layer 14 for use as a cover layer. Among them, in an environment where the temperature is about 10 ′ to 70 ° C and the high-frequency power is about 50 to 150 watts, (Si (CxHy) z) and 30 to 6 with a flow rate of about 50 to 80 0 seem 0 0 sccn ^ 5N20 or 0 2 gas, and on the surface of the low dielectric constant material layer 14, a carbon-containing oxide layer 16 having a thickness of about 500 to 1,000 angstroms is deposited. As for 'in the preferred embodiment, it can provide an environment with a temperature of about 17 ° C and a high-frequency power of about 70 watts, and pass in trimethylsiloxane (Si (CH3) 3) and M or A gas to Carry out deposition of carbon-containing oxidizing materials. Bolt of cloth

472328 --- 5. Description of the invention (6) No low-frequency power is applied, but the possible damage of the feed layer 1 4 can be achieved. f. While the deposition process is in progress, the reduction is performed step by step on the low-dielectric system at the bottom. The carbon is used to oxidize the carbon. It is generally used to form a photo-recyclable material. In addition to the remaining materials, please refer to layer 16 and low stop layer 1. 2 'After defining the resist layer and using the photoresist layer as the layer 1 4, the opening pattern can be irradiated with the third dielectric system. The mask pattern is defined by the material and the mask is opened, and the particles removed by the layer are subjected to an etching process on the layer 14 by the traditional lithography technology, until a plurality of opening patterns are in it. At one time, the carbon-containing oxide layer 16 may be first patterned into the photoresist layer. Next, a desired opening pattern is defined for the carbon-containing oxide layer 16 and the low dielectric system. In the figure, the plasma ashing process is performed to clear and break the genus. After the opening pattern procedure, a conductive 'Λ ^ a 6 can be deposited and filled in the above-mentioned plurality of opening patterns. For example, by using a method such as a sputtering process (method 2), chemical vapor deposition method, etc. Ii) or other suitable = process sequence to form a metal material in the opening pattern and form the '18 here. Taking the copper process as an example, a copper seed layer can be formed on the opening diagram: on the wall and the bottom, and then the entire semiconductor substrate 10 is immersed in the sulfuric acid steel side to perform the chemical electricity ore (ECP) reaction, and After forming the steel material required by the household, then, as shown in the fourth figure, the semiconductor substrate 10 can be subjected to a chemical machine 472328.

A mechanical polishing process (CMP) to remove a portion of the conductive layer 18 above the carbon-containing oxide layer 16 and define a damascene structure 20 in the opening pattern. In general, the formed damascene structure 20 can be used not only as a metal connection pattern, but also as a conductive via between dielectric layers or a conductive plug as needed. g. In this CMP process, it is also possible to selectively remove the carbon-containing oxide layer 6 until the upper surface of the low-dielectric-constant material layer 4 comes out. Or, by adjusting the time of the grinding process, the thickness of the carbon-containing oxide layer 16 can be reduced to meet the requirements of the manufacturing process. It is worth knowing that, since in the step of depositing the carbon-containing oxide layer described above, only a few tens of watts of high-frequency power is used, and the low-frequency power is controlled at ^ watts. Therefore, the entire deposition process will not cause serious damage to the porous low-dielectric material below. Once the damage is caused, the low-dielectric-constant film layer will be voided after the CMP process. Furthermore, because in this deposition process, a N2O reaction gas is passed in and the reaction temperature is only about 10 to 70C, it is compared with the M1 used in the conventional deposition of silicon nitride and silicon carbide film layers and the accompanying The high temperature process (about 400 times) will minimize the damage to the low dielectric constant material layer. In this way, in the subsequent chemical-mechanical second-milling process, ‘reduced porosity of porosity and low-dielectric constant material ’s void dimples’ will be achieved to achieve the goal of improving overall process yield. Therefore, in addition, 'it should be particularly pointed out that the use of low temperature / low power deposition of carbon-containing oxide materials' has a dielectric constant of only about 2.8 to 2.9. That is, ^ is more than silicon nitride with a dielectric constant of about 7.0, or silicon carbide of about 4.5 to 5.0.

Page 10 472328 V. Description of the invention (8) 氧化物 ίΐΐ? Obviously, the oxide can further reduce the integrated circuit A parasitic mine ::: title and improve the porosity of the low dielectric system: Second, because the deposition process is in progress At this time, only a lower power consumption of about room temperature is needed. When the method of the present invention is used, the cost of the process can be reduced, and the purpose of saving costs is achieved. Although the present invention is exemplified by the above-mentioned preferred examples, it is not used for the purpose of inventing the spirit of the invention and the entity of the invention ', but only to this embodiment. For example, in the present invention, although a carbon-containing oxide material layer is used in a single embedding process, q is familiar with this:? 2 :: When it is easy to understand the use of carbon-containing oxidizing materials to form Ί: Method ’can also be applied to double inlay or other related

Within the process. ^ ^ / ΊΓ + Modifications made without departing from the spirit and scope of the present invention should all be included in the scope of patent application described below. L

Page 472328 Brief description of the drawings The above detailed description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, of which: The first figure is a cross-sectional view of a semiconductor wafer. According to the conventional technology, void defects may be generated when the mosaic structure is defined in the porous low-dielectric-constant material layer. The second figure is a cross-sectional view of a semiconductor wafer, which shows that the carbon-containing oxide is deposited under high temperature and high power conditions according to the process of the present invention. The third layer is a cross-sectional view of a semiconductor wafer showing a step of depositing a conductive layer in an opening pattern according to the process of the present invention; and the fourth image is a cross-section of a semiconductor wafer Figure showing the steps of defining a mosaic structure using a CMP process according to the present invention.

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Claims (1)

472328 6. Scope of patent application Patent scope: 1. A method of manufacturing a damascene structure on a semiconductor substrate. The method includes at least the following steps: forming a layer of a low dielectric constant material on the semiconductor substrate; In an environment of 10 to 70 t and a power of about 50 to 150 watts, a plasma chemical vapor deposition method is performed to form a carbon-containing oxide layer on the low-dielectric-constant material layer for use as a cover layer. ; The carbon-containing oxide layer and the low-dielectric-constant material layer are engraved to form an opening pattern therein, and a part of the surface of the semiconductor substrate is exposed, wherein the carbon-containing oxide layer can protect the low-dielectric constant below. A material layer to avoid damage during the CMP process; and a conductive damascene structure is formed in the opening pattern. Medium and low dielectric materials mentioned above. 2. The method according to item 1 of the scope of patent application, wherein several material layers are composed of porous low-dielectric coefficient materials, wherein the above-mentioned low-dielectric systems LK, Flare, HSQ, 3. The material of the material layer can be selected from BD, CORAL, Si Na a og 1 ass, or any combination thereof. The above-mentioned gas containing 〇2 was deposited. 4. If the method of the first scope of the patent application is applied, when the carbon oxide layer is used, (Si (CxHy) z) and %% can be passed. 472328 VI. Scope of patent application The carbon oxide layer can be accessed. ((: 113) 3 and ~ 〇 gas. 6. The method according to the above claim 1 item Λ /, wherein the above-mentioned carbon-containing oxide layer has a dielectric constant of 0.8 to 2.9. 7. For example, if the layer of the material with a permittivity of 1 is applied on the semiconductor substrate, the formation of the dielectric layer or the material layer on the semiconductor substrate includes the formation of each M. 8. The ancient layer of the item has a thickness of about 500 to 100 angstroms. The method, in which the above-mentioned carbon-containing oxide 9 · As in the scope of the patent application, before the 1st layer of the dielectric constant material layer, it further includes,,, where the above is formed On the surface of the low substrate so as to stop the layer on the surface of the semiconductor conductor substrate with a engraving. ㈣ 'can protect the half 10. A method of exciting the semiconductor substrate &amp; 5 + 6 _L k • Damscene structure method, the method includes at least the following steps: forming a truncation stop layer on the semiconductor substrate. Forming a porous material layer on the etch stop layer at a temperature of about 1G to 7Gt and power to 12 () watts (Si ( CxHy) z) gas is used to form a carbon-containing oxide layer on the porous material ^ W chemical 1-phase deposition method, and the shape of the raw material layer is used as a cover layer; Page 472 328 The carbon-containing oxide etch stop layer is etched to shape the surface of the semiconductor substrate; the layer and the porous material layer form an opening pattern in it, until it reaches the last name and the exposed portion is filled in the opening / daughter conductive Layer on the surface of the carbon-containing oxide layer; and a part of the conductive layer Q that is subjected to a chemical mechanical polishing process above to remove the above-mentioned porosity of the carbon-containing oxide layer, which is being deposited, as described in 11. The method material range of the item 10 is composed of a low dielectric constant material. Mountain 12. The method according to item 10 of the scope of the patent application, when the carbon oxide layer is contained, and pass in a gas of 0 or 02. Wherein the above 3) 3) and 乂 〇 gas are deposited. • 1 3. According to the method in the patent application No. 10, when the carbon oxide layer is contained, trimethylsilane (si (CH 14. The method in the patent application No. 10, where the oxide layer has about 2. Dielectric coefficient of 8 ~ 2 · 9. Said s carbon 15 · The method of item 10 of the patent application scope, wherein before the dielectric coefficient material layer is on the semiconductor substrate, ^ includes ^ to the low A step of layering a component or a material on the semiconductor substrate. '成 various formulas 472328 Page 16