TW470880B

TW470880B - Device and method for accessing BIOS data

Info

Publication number: TW470880B
Application number: TW87121700A
Authority: TW
Inventors: Shu-Shan Tsai; Li-Jung Huang
Original assignee: Acer Labs Inc
Priority date: 1998-12-24
Filing date: 1998-12-24
Publication date: 2002-01-01

Abstract

The present invention relates to a novel device and system for accessing BIOS data. The present device for accessing BIOS data comprises: a central processor; a first data processor connected to the central processor and a bus with m-bit address line for performing data processing in response to the command of the central processor; a second data processor connected to the bus with m-bit address line by m-bit address line for performing relative low-speed data processing; a BIOS connected to the bus with m-bit address line by n1-bit address line, where n1 is smaller than m, and connected to the second data processor by n2-bit data line.

Description

470880 五、發明說明（1) 發明領域：本發明係關於一種存取基本輸入輸出系統（BI os)資料之裝置及方法，尤指藉由新穎的存取基本輸入輸出系統 (BI OS )資料之方式，可有效地空出資料處理器之必需的接腳數目，並能以較多之位址定出較高之容量。相關習知技術= 參見第1圖，指出習知存取基本輸入輸出系統（BI0S) 資料之裝置的方塊圖，其*CPU(中央處理器）1與北橋2間可進行命令之交換，而北橋2則與PCI(週邊零件連接界面）匯流排5相通，並可與南橋3交換資料，而南橋3則藉由 I SA(工業標準架構）界面6而與基本輸入輸出系統（BI OS) 4 連接以讀取資料。I SA界面6中含有I SA匯流排的位址線 SA[16:0]及X-匯流排的資料線XD[7:0]。當系統開機時， CPU1會透過北橋2、PCI匯流排5、南橋3、I SA界面6來讀取基本輸入輸出系統（BI OS) 4中的程式碼，以作爲系統初始化的執行程式。，系統中之詳細動作請參見第2圖之時間圖所示，在位址相位發出的同時，CPU1送出控制命令使北橋 2執行PCI匯流排命令，在位元組信號線（C/BEJ[ 3:0])發出匯流排命令之後，於資料相位時送出”可進行位元組（Byte Enable)”之讀取信號，然後在ISA界面6中，驅動系統位址線8枓16:0]，資料〇人1人1及〇八7“分別於18人匯流排之位址470880 V. Description of the invention (1) Field of the invention: The present invention relates to a device and method for accessing basic input and output system (BI os) data, especially through novel access to basic input and output system (BI OS) data. This method can effectively vacate the required number of pins of the data processor, and can set a higher capacity with more addresses. Related know-how = Refer to Figure 1 and point out a block diagram of a device that is known to access Basic Input Output System (BI0S) data. Its * CPU (Central Processing Unit) 1 and North Bridge 2 can exchange commands, and North Bridge 2 is connected to the PCI (peripheral component connection interface) bus 5 and can exchange data with South Bridge 3, and South Bridge 3 is connected to the Basic Input Output System (BI OS) 4 through the I SA (Industrial Standard Architecture) interface 6 To read data. The I SA interface 6 contains the address lines SA [16: 0] of the I SA bus and the data lines XD [7: 0] of the X-bus. When the system is turned on, CPU1 reads the code in the Basic Input Output System (BI OS) 4 through Northbridge 2, PCI bus 5, Southbridge 3, and ISA interface 6 as the system's initial execution program. For detailed actions in the system, please refer to the time chart in Figure 2. At the same time as the address phase is issued, CPU1 sends a control command to cause Northbridge 2 to execute the PCI bus command, and the byte signal line (C / BEJ [3 : 0]) After issuing the bus command, send a “Byte Enable” read signal at the data phase, and then drive the system address line 8 枓 16: 0 in the ISA interface 6], Information 0 person 1 person 1 and 08 8 "at the address of the 18 person bus

G \ Pr ogram Fi 1 es\ Pat ent \ Q - 0029. pt d 第 4 頁 470880 五、發明說明（2) 線SA[ 16: 0]之ADDRESS1相位及ADDRESS2相位中進行基本輸入輸出系統（BI OS)之資料讀取，再經由X-匯流排資料線奶[7: 〇]傳送至南橋3。然後再令PCI匯流排之位址資料線 A〇[ 3 1: 0]送出所讀取之資料，並宣告TRDYJ信號以結束讀取周期。依此習知的方式，基本輸入輸出系統（BIOS)資料必須透過上述PCI匯流排的位址資料線AD[ 31:0]、ISA匯流排的位址線SA[16:0]以及X-匯流排資料線XD[7:0]等方可順利地被讀取。習知技術所面臨的問題簡述於後。由於個人電腦之功能越來越繁複，因此在晶片之製作上會有需將更多的功能整合於晶片組中之趨勢。即使裸晶的製造成本沒有增加，但是由於功能的增加必然導致連接腳位的增加，所以使得無法以較便宜的PGA或QFP等等封裝方式爲之，而必須改以較高成本的方式例如BGA爲之。如此一來，使得晶片的製造成本相對地提高許多。此外，由於接腳數目的增多及電腦工作頻率的增加，會使得主機板上繞線之佈線工作相對地變得更加困難。所以如何減少晶片組之接腳數目勢必成爲重要之課題。另外，ISA(工業標準架構）界面已於PC99規格中被排除，但由於爲了讀取傳統基本輸入輸出系統（BI OS)上之資料，必需在南橋中保留二十餘根的ISA匯流排界面接腳與之連接，如此一來顯然會在有限的主機板佈局上形成浪G \ Pr ogram Fi 1 es \ Pat ent \ Q-0029. pt d Page 4 470880 V. Description of the invention (2) The basic input and output system (BI OS) is performed in the ADDRESS1 phase and ADDRESS2 phase of line SA [16: 0] ) To read the data, and then transmit it to the South Bridge 3 via the X-bus data line milk [7: 〇]. Then, the address data line A0 [3 1: 0] of the PCI bus is sent to read the data, and the TRDYJ signal is announced to end the read cycle. In this conventional way, the basic input and output system (BIOS) data must pass through the address data lines AD [31: 0] of the PCI bus, the address lines SA [16: 0] of the ISA bus, and X-bus. The data line XD [7: 0] can be read smoothly. The problems faced by conventional technologies are briefly described below. As the functions of personal computers become more and more complicated, there will be a tendency to integrate more functions into the chipset in the production of chips. Even if the manufacturing cost of the die does not increase, the increase in functions will inevitably lead to an increase in the number of connection pins, which makes it impossible to use cheaper PGA or QFP packaging methods, and it must be changed to a higher cost method such as BGA For it. As a result, the manufacturing cost of the wafer is relatively increased. In addition, due to the increase in the number of pins and the increase in computer operating frequency, it will make the wiring work of the motherboard board relatively more difficult. Therefore, how to reduce the number of pins of a chipset is bound to become an important issue. In addition, the ISA (Industrial Standard Architecture) interface has been excluded from the PC99 specification, but in order to read the data on the traditional basic input output system (BI OS), more than 20 ISA bus interface interfaces must be kept in the South Bridge. Feet connected to it, this will obviously form waves on the limited motherboard layout

C \Program Fi 1 es\Pat ent\ Q-0029. ptd 第 5 頁 470880 五、發明說明（3) 費。而且由於南橋與基本輸入輸出系統（BI OS)之間以I SA 匯流排中之17條位址線來定址，所以其定址能力受到相當的限制，僅僅能定址到128K，特別是對於基本輸入輸出系統（BI OS)所能載入的應用程式會有不必要的限制。發明槪要：有鑑於習知技術之上述問題，本發明之發明人遂而檢討是否可利用PCI匯流排之位址資料線來取代I SA匯流排之位址線，進而發展出利用PCI匯流排之位址資料線 AD[ 31: 0]中的AD[ 16: 0]之I7條位址資料線來取代ISA匯流排之位址線SA[16:0]，以作爲基本輸入輸出系統（BIOS)資料之傳送，如此可省去ISA匯流排的SA[ 16: 0]之17條位址線，因而可在南橋上空出17根接腳。此外，由於PCI匯流排之位址資料線爲32條，遠較I SA 匯流排之位址線爲多，所以利用PCI匯流排之32條位址資料線，可使基本輸入輸出系統（BI OS)能定址到更高的容量，的32次方約爲4G的容量，因此可達到能載入更多作業程式之目的，亦即可進一步將作業系統載入基本輸入輸出系統（BI OS)中，特別適用於無硬碟系統，例如：語言翻譯機、W NDOWS CE之掌上型電腦中。本發明之目的在於利用原有PCI匯流排之位址資料線C \ Program Fi 1 es \ Pat ent \ Q-0029. Ptd page 5 470880 V. Description of the invention (3) Fee. And because the South Bridge and the Basic Input Output System (BI OS) use 17 address lines in the I SA bus for addressing, its addressing capacity is quite limited. It can only address 128K, especially for basic input and output. There can be unnecessary restrictions on the applications that the BI OS can load. Summary of the invention: In view of the above problems of the conventional technology, the inventor of the present invention then reviewed whether the address data line of the PCI bus can be used instead of the address line of the I SA bus, and then developed the use of the PCI bus I [7: 0] of AD [16: 0] in the address data line AD [31: 0] of the address data line replaces the address line SA [16: 0] of the ISA bus as a basic input output system (BIOS ) Data transmission, so that the 17 address lines of SA [16: 0] of the ISA bus can be omitted, so 17 pins can be left on the South Bridge. In addition, since there are 32 address data lines for the PCI bus, which is far more than the address lines of the I SA bus, using the 32 address data lines of the PCI bus enables the basic input and output system (BI OS ) Can be addressed to a higher capacity, the power of 32 is about 4G, so it can achieve the purpose of loading more operating programs, which can further load the operating system into the basic input and output system (BI OS) , Especially suitable for hard diskless systems, such as: language translators, W NDOWS CE handheld computers. The purpose of the present invention is to use the address data line of the original PCI bus.

G \ProgramFi 1 es\Pat ent\ Q-0029. pt d 第 6 頁 470880 五、發明說明（4) 來代替ISA匯流排之位址線，以空出南橋與基本輸入輸出系統（BI OS)間之必要接腳數目，進而解決南橋因功能增加促使接腳數增加，而導致封裝及成本上升之問題。本發明的另一目的在於藉著在PCI匯流排之位址資料線上具有較多定址線之特性，提升原基本輸入輸出系統. (BIOS)之可定址容量，進而可載入更多作業系統程式於基本輸入輸出系統（BI OS)。依據本發明的一個觀點，提供一種存取基本輸入輸出系統（BI OS)資料之裝置，包含：一中央處理器；一第一資料處理器，連接中央處理器與一 πι位元位址資料線之匯流排，可因應中央處理器之指令進行資料處理；一第二資料處理器，以m位元位址資料線與m位元位址資料線之匯流排連接，用於進行較低速的資料處理；一基本輸入輸出系統 (BI OS)，以小於m之nl位元位址資料線與該m位元位址資料線之匯流排相互電連接，且以n2位元資料線與該第二資料處理器連接。依據本發明的另一個觀點，提供一種存取基本輸入輸出系統（BI OS)資料之方法，其中相關的讀取週期包含以下步驟：（A)於PCI位址相位結束後，南橋栓鎖住位址相位； (B)於南橋栓鎖住位址相位後，PCI匯流排之位址資料線推出所需基本輸入輸出系統（BI OS)位址之資料；（C)南橋驅G \ ProgramFi 1 es \ Pat ent \ Q-0029. Pt d p. 6 470880 V. Description of the invention (4) Instead of the address line of the ISA bus, the space between the South Bridge and the Basic Input Output System (BI OS) is vacated. The necessary number of pins further solves the problem of the package and cost increase caused by the increase in the number of pins caused by the increased function of the South Bridge. Another object of the present invention is to improve the addressable capacity of the original basic input and output system (BIOS) by having more address lines on the address data line of the PCI bus, so that more operating system programs can be loaded. For Basic Input Output System (BI OS). According to an aspect of the present invention, a device for accessing basic input and output system (BI OS) data is provided, including: a central processing unit; a first data processing unit connected to the central processing unit and a π-bit address data line; The data bus can be processed according to the instructions of the central processing unit. A second data processor is connected by the bus of the m-bit address data line and the m-bit address data line for low-speed data processing. Data processing; a basic input-output system (BI OS), electrically connecting the buses of the n-bit address data line smaller than m with the m-bit address data line, and the n2-bit data line with the first Two data processor connections. According to another aspect of the present invention, a method for accessing basic input and output system (BI OS) data is provided, wherein the related read cycle includes the following steps: (A) after the PCI address phase ends, the south bridge latch locks the bit Address phase; (B) After the address phase is locked by the South Bridge, the address data line of the PCI bus is launched with the required basic input and output system (BI OS) address information; (C) South Bridge driver

C \ProgramFi 1 es\ Pat ent\ Q - 0029. pt d 第 7 頁 470880 五、發明說明（5) 動記憶體讀取信號、基本輸入輸出系統（BI OS)晶片選擇信號；（D)基本輸入輸出系統（BI OS)將資料傳送至南橋；（E) 南橋推出所得之基本輸入輸出系統（BI OS)內含資·料；（F) 宣告讀取完成信號；及（G)結束讀取週期。依據本發明的另外一個觀點，，提供一種存取基本輸入輸出系統（BI OS)資料之方法，其中相關的寫入週期包含以下步驟：（A)中央處理器執行一寫入指令，透過PCI匯流排將一筆資料寫入並儲存於基本輸入輸出系統（BI 0S)之記憶體；（B)南橋栓鎖住此筆寫入資料；（C)中央處理器對此筆相同資料再執行寫入指令；及（D)將此筆資料寫入並儲存於基本輸入輸出系統（BI OS)的記憶體。依據本發明之優點在於基本輸入輸出系統（BI OS)之資料可在不影響PCI匯流排的正常動作下，經由AD[ 16: 0]來進行位址資料傳送，可達到取代I SA匯流排的SA[ 16: 0]之 17條位址線之目的，使得在南橋上可具體地空出17個接腳，進而降低整個裝置的製造成本。另外，由於PCI匯流排之位址資料線比ISA匯流排之位址線多，故使用本發明時可進而利用到全部的位址資料線，所以可定址到更高之容量並使可直接利用之容量大增。對於語言翻譯機、W NDO^\S CE之掌上型電腦而言，可以存入更多的標準作業應甩程式。C \ ProgramFi 1 es \ Pat ent \ Q-0029. pt d p. 7 470880 V. Description of the invention (5) Memory read signal, basic input output system (BI OS) chip selection signal; (D) basic input The output system (BI OS) transmits data to Nanqiao; (E) The basic input and output system (BI OS) included in the launch of Nanqiao includes information and materials; (F) announces the read completion signal; and (G) ends the read cycle . According to another aspect of the present invention, a method for accessing basic input and output system (BI OS) data is provided, in which the related write cycle includes the following steps: (A) the central processing unit executes a write instruction and converges through PCI Write and store a piece of data in the memory of the basic input output system (BI 0S); (B) the south bridge latch locks the written data; (C) the CPU executes the write command for the same data ; And (D) write and store this data in the memory of the Basic Input Output System (BI OS). The advantage of the present invention is that the data of the Basic Input Output System (BI OS) can be used to transmit address data through AD [16: 0] without affecting the normal operation of the PCI bus, which can replace the I SA bus. The purpose of the 17 address lines of SA [16: 0] is to allow 17 pins to be specifically vacated on the south bridge, thereby reducing the manufacturing cost of the entire device. In addition, because the PCI bus has more address data lines than the ISA bus, all the address data lines can be used when using the present invention, so it can be addressed to a higher capacity and can be used directly The capacity has increased greatly. For language translators, W NDO ^ \ S CE handheld computers, more standard operating applications can be stored.

C \ Program Fi 1 es\ Patent\ Q - 0029. pt d 第 8 頁 470880 五、發明說明.（6) 圖形之簡要敘述：藉由參見以下之附圖連同較佳實施例之詳細敘述，可明顯地看出本發明之其它目的、特徵及優點，其中：第1圖指出依據習知技術之讀取基本輸入輸出系統 (BI OS)資料之裝置的方塊圖；第2圖指出依據習知技術之讀取基本輸入輸出系統 (BI OS)資料的時間圖；第3圖指出依據本發明之存取基本輸入輸出系統 (BI OS)資料之裝置的方塊圖；第4圖指出依據本發明之存取基本輸入輸出系統 (BIOS)資料之方法的讀取動作之時間圖；及第5圖指出依據本發明之存取基本輸入輸出系統 (BI OS)資料之方法的寫入動作之時間圖。主要元件之符號說明： 1中央處理器 2北橋 3南橋 4基本輸入輸出系統（BI os) 5PCI匯流排 61 SA界面 Η中央處理器C \ Program Fi 1 es \ Patent \ Q-0029. pt d Page 8 470880 V. Description of the invention. (6) Brief description of the figure: It can be clearly seen by referring to the following drawings together with the detailed description of the preferred embodiment. Other objects, features, and advantages of the present invention can be clearly seen, in which: FIG. 1 shows a block diagram of a device for reading basic input-output system (BI OS) data according to conventional technology; FIG. 2 shows a block diagram according to conventional technology Time chart for reading basic input output system (BI OS) data; Figure 3 shows a block diagram of a device for accessing basic input output system (BI OS) data according to the present invention; Figure 4 shows access according to the present invention The timing chart of the reading operation of the method of the basic input output system (BIOS) data; and FIG. 5 shows the timing chart of the writing operation of the method of accessing the basic input output system (BI OS) data according to the present invention. Explanation of symbols of main components: 1 Central Processing Unit 2 North Bridge 3 South Bridge 4 Basic Input Output System (BI os) 5 PCI Bus 61 SA Interface Η Central Processing Unit

C \ Pr ogram Fi 1 es\ Pat ent \ Q - 0029. pt d 第 9 頁 470880 五、發明說明（7) I2第一資料處理器 13第二資料處理器 14基本輸入輸出系統（BI OS) 15PCI匯流排較佳實施例之詳細敘述：參見第3圖，指出依據本發明的一個實施例之存取基本輸入輸出系統（BI OS)資料之裝置的方塊圖，其中存取基本輸入輸出系統（BI0S)資料之裝置包含：中央處理器11、第一資料處理器12、第二資料處理器13、基本輸入輸出系統（BIOS)14。第一資料處理器12係連接中央處理器11與m 位元位址資料線之PCI匯流排1 5，可因應中央處理器1 1之指令而進行資料處理。第二資料處理器13係以m位元位址資料線而與m位元位址資料線之PCI匯流排1 5連接，用於進行較低速的資料處理。基本輸入輸出系統（BI OS) 14以小於 m之nl位元位址資料線與m位元位址資料線之PCI匯流排15 連接，且以n2位元資料線與第二資料處理器13連接。依據本實施例之存取基本輸入輸出系統（BI OS)資料之裝置，讀取資料是在m位元位址資料線之匯流排位址相位發出的同時，第二資料處理器栓鎖此位址相位，藉著m位元位址資料線之匯流排推出所需基本輸入輸出系統（BI OS) 位址之資料，第二資料處理器驅動記憶體讀取信號、基本C \ Pr ogram Fi 1 es \ Pat ent \ Q-0029. pt d Page 9 470880 V. Description of the invention (7) I2 first data processor 13 second data processor 14 basic input output system (BI OS) 15PCI Detailed description of the preferred embodiment of the bus: Referring to FIG. 3, a block diagram of a device for accessing basic input output system (BI OS) data according to an embodiment of the present invention is shown, in which the basic input output system (BI0S) is accessed The data device includes: a central processing unit 11, a first data processor 12, a second data processor 13, and a basic input output system (BIOS) 14. The first data processor 12 is a PCI bus 15 connecting the central processing unit 11 and the m-bit address data line, and can perform data processing according to the instructions of the central processing unit 11. The second data processor 13 is connected to the PCI bus 15 of the m-bit address data line by an m-bit address data line, and is used for low-speed data processing. The Basic Input Output System (BI OS) 14 is connected to the PCI bus 15 of the m-bit address data line by an nl-bit address data line smaller than m, and is connected to the second data processor 13 by an n2-bit data line. . According to the device for accessing the basic input output system (BI OS) data in this embodiment, the data is read out while the bus address phase of the m-bit address data line is issued, and the second data processor latches this bit. Address phase, through the bus of the m-bit address data line to launch the required basic input output system (BI OS) address data, the second data processor drives the memory to read the signal, the basic

C \Program Fi 1 es\Pat ent\ Q-0029. pt d 第 10 苜 470880 五、發明說明（8) 輸入輸出系統（BI 〇S)晶片适擇丨g號’然後基本輸入輸出系統（BI OS)可經由η2位元資料線來傳送資料至第二資料處理器，接著第二資料處理器可透過m位元位址資料線而推出所得之基本輸入輸出系統（BI 〇S)內含資料。依據本實施例之存取基本輸入輸出系統（BI〇S)資料之裝置，寫入資料是藉著由中央處理器執行許多次的相同寫入指令，於執行首次寫入指令時以第二資料處理器來栓鎖寫入資料，並於執行非首次寫入指令時，將資料寫入基本輸入輸出系統 (BIOS)之記憶體。依據第3圖所示之配置，基本輸入輸出系統（BI OS)之資料可在不影響PCI匯流排的正常動作下，經由nl位元位址資料線來進行位址資料傳送，如此一來能取代在習知技術中ISA匯流排SA[ 16:0]之17條位址線，同時能在南橋裝置上省去17隻接腳，進而達到封裝容易及降低製造成本的目的。依據本發明的一個較佳實施例，m位元位址資料線之匯流排爲PCI匯流排，第一資料處理器爲北橋，第二資料處理器爲南橋，其中具有m位元位址資料線之PCI匯流排中的m的數目爲32。基本輸入輸出系統（BIOS)以til位元位址資料線與PCI匯流排連接，其中til的數目爲17。基本輸入輸出系統（BI OS)是以ri2位元資料線與南橋連接，其中n2的數目爲8。須注意nl與n2的數目可依實際需要而加以改C \ Program Fi 1 es \ Pat ent \ Q-0029. Pt d 10th Clover 470880 V. Description of the invention (8) Input / output system (BI 〇) chip selection 丨 g number 'and then the basic input and output system (BI OS ) The data can be transmitted to the second data processor via the η2-bit data line, and then the second data processor can launch the basic input-output system (BIOS) containing the data through the m-bit address data line. According to the device for accessing basic input and output system (BIOS) data according to this embodiment, the data is written by the same write instruction executed many times by the central processing unit, and the second data is written when the first write instruction is executed. The processor locks the write data, and writes the data into the memory of the basic input output system (BIOS) when the non-first write command is executed. According to the configuration shown in Figure 3, the data of the Basic Input Output System (BI OS) can be used to transmit address data through the nl-bit address data line without affecting the normal operation of the PCI bus. It replaces the 17 address lines of the ISA bus SA [16: 0] in the conventional technology, and can save 17 pins on the south bridge device, thereby achieving the purpose of easy packaging and reducing manufacturing costs. According to a preferred embodiment of the present invention, the bus of the m-bit address data line is a PCI bus, the first data processor is a north bridge, and the second data processor is a south bridge, which has an m-bit address data line. The number of m in the PCI bus is 32. The basic input output system (BIOS) is connected to the PCI bus with a til bit address data line, where the number of tils is 17. The Basic Input Output System (BI OS) is connected to the South Bridge with a ri2 bit data line, where the number of n2 is eight. It should be noted that the number of nl and n2 can be changed according to actual needs.

C \ Pr ogr am Fi 1 es\ Pat ent \ Q - 0029. pt d 第 11 頁 470880 五、發明說明（9) 變，例如如欲增加定址容量，可將nl由17增加爲32以提高定址容量。參見第4圖與第5圖，分別說明依據本發明的一個實施例之存取基本輸入輸出系統（BI OS)資料之方法中的讀取動作與寫入動作的時間圖。第4圖爲一時間圖，用於說明存取基本輸入輸出系統（BI OS)資料之方法的讀取動作。如第 4圖所示，PCI匯流排的位址資料線AD[ 31:0]係代表PCI位址/資料爲多工位址和資料匯流排。當第一個時脈（第一位址相位）被傳送之時，PCI匯流排的位址資料線3 1: 〇]會包含一個物理位元組位址（32位元），於隨後之時脈（第二位址相位）時，PCI匯流排的位址資料線AD[ 3 1: 0]則包含資料。係由南橋所發出之BIOS(基本輸出入系統）的資料讀取命令。R〇MCSJ係由南橋所發出之BI OS(基本輸出入系統）晶片選取命令。TRDYJ係一信號，表示晶片組資料流相位已完成。當主機開啓之後，於基本輸入輸出系統（BI OS)之讀取周期中，當PCI位址相位（address phase)結束後，PCI匯流排之位址資料線^[31:0]由南橋驅動，此時南橋將位址相位栓鎖後，再由PCI匯流排之位址資料線AD[ 3 1: 0]送出該位址資料，並驅動記憶體讀取信號及基本輸入輸出系統（BIOS)晶片選擇信號ROM：SJ，等待資料由X-匯流排資料線XD[ 7: 0]讀取後，再令PCI匯流排的位址資料線C \ Pr ogr am Fi 1 es \ Pat ent \ Q-0029. pt d Page 11 470880 V. Description of the invention (9) Change, for example, if you want to increase the addressing capacity, you can increase nl from 17 to 32 to increase the addressing capacity . Referring to FIG. 4 and FIG. 5, the timing diagrams of the read operation and the write operation in the method of accessing the basic input output system (BI OS) data according to an embodiment of the present invention are explained, respectively. Fig. 4 is a timing chart for explaining a reading operation of a method for accessing a basic input output system (BI OS) data. As shown in Figure 4, the address data line AD [31: 0] of the PCI bus indicates that the PCI address / data is a multiplexed address and a data bus. When the first clock (first address phase) is transmitted, the address data line 3 of the PCI bus 3 1: 0] will contain a physical byte address (32 bits), at a later time Pulse (second address phase), the address data line AD [3 1: 0] of the PCI bus contains data. It is the BIOS (Basic Input / Output System) data read command issued by Southbridge. ROMCSJ is a BI OS (Basic Input / Output System) chip selection command issued by Southbridge. TRDYJ is a signal indicating that the phase of the chipset data stream is complete. After the host is turned on, in the read cycle of the basic input output system (BI OS), when the PCI address phase is completed, the address data line of the PCI bus ^ [31: 0] is driven by the south bridge. At this time, the South Bridge latches the address phase, and then sends the address data from the address data line AD [3 1: 0] of the PCI bus, and drives the memory to read signals and the basic input and output system (BIOS) chip. Select signal ROM: SJ, wait for data to be read by X-bus data line XD [7: 0], and then make the address data line of PCI bus

C\Pr〇gramFi 1 es\Patent\Q-0029. ptd 第 12 頁 470880 五、發明說明（10) 3 l G]送出所讀取之資料，並宣告目的完成信號TRDYJ 信號，以結束讀取周期，亦即完成讀取動作。第5圖爲一^日寸間圖’用於說明存取基本輸入輸出系統 (BI OS)資料之方法的寫入動作。如第5圖所示，在欲更改基本輸入輸出系統（BI OS)中程式之時，於基本輸入輸出系統（BI OS)之寫入周期中，每一寫入動作需由中央處理器執行兩次寫入指令才算完成。南橋在第1次寫入指令時，栓鎖要寫入之資料，而在第2次寫入指令時，才驅動]、 RONCSJ及X-匯流排資料線χ〇[ 7: 0]，將資料寫入基本輸入輸出系統（BIOS)中，以結束寫入周期。雖然以上已針對本發明之若干實施例加以敘述，須知以上敘述只是用於說明而非限制本發明。在不偏離本發明之精神與範圍下’熟於此技藝者可做成許多不同的修改。因此’本發明之範圍是由以下所附的申請專利範圍來界定。C \ Pr〇gramFi 1 es \ Patent \ Q-0029. Ptd Page 12 470880 V. Description of the invention (10) 3 l G] Send the read data and announce the completion signal TRDYJ for the purpose to end the reading cycle , That is, the reading operation is completed. FIG. 5 is a one-day time chart 'for describing the writing operation of the method of accessing the basic input output system (BI OS) data. As shown in Figure 5, when you want to change the program in the Basic Input Output System (BI OS), during the writing cycle of the Basic Input Output System (BI OS), each writing operation needs to be performed by the central processing unit. The write instruction is considered complete. When Southbridge writes the instruction for the first time, it locks the data to be written, and only drives it when it writes for the second time.], RONCSJ and X-bus data line χ〇 [7: 0] Write to the Basic Input Output System (BIOS) to end the write cycle. Although several embodiments of the present invention have been described above, it should be noted that the above descriptions are only used to illustrate and not limit the present invention. Many variations can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of patent application attached below.

G \ Pr ogr am Fi 1 es\ Pat ent \ Q - 0029. pt d 第 13 頁G \ Pr ogr am Fi 1 es \ Pat ent \ Q-0029. pt d page 13

Claims

470880 VI. Application Patent Scope 1. A device for accessing basic input and output system (BIOS) data, including: a central processing unit; a first data processing unit connecting the central processing unit and an m-bit address data line The data bus can be processed according to the instructions of the central processing unit. A second data processor connects the bus of the m-bit address data line to the bus of the m-bit address data line for lower data processing. High-speed data processing; a basic input-output system (BI 0S), which is connected to the bus of the n-bit address data line smaller than m and the m-bit address data line, and the n2-bit data line is connected to the first Two data processor connections. 2. The device for accessing basic input and output system (BI 0S) data as described in item 1 of the scope of patent application, wherein the data is read after the phase of the bus address of the m-bit address data line is completed. The second data processor latches the address phase, and the bus of the m-bit address data line launches the data of the required basic input output system (BIOS) address. The second data processor drives the memory The read signal, the basic input output system (BI OS) chip selection signal, and then the basic input output system (BI 〇s) sends data to the second data processor through the n2-bit data line, and the second data processor passes the The m-bit address data line introduces the $ data in the Basic Input Output System (BI OS).

C \ ProgramFiles \ Patent \ Q-0029 · ptd Page 14 470880 6. Scope of patent application 3. As described in item 1 of the scope of patent application, the device for accessing basic input and output system (BI OS) data, in which data is written By using the central processing unit to execute the same write instruction many times, the second data processor is used to lock the write data when the first write instruction is executed, and the data is written to when the non-first write instruction is executed. Memory of Basic Input Output System (BIOS). 4. The device for accessing basic input and output system (BI OS) data as described in item 1 of the scope of patent application, wherein the bus of the m-bit address data line is a PCI bus. 5. The device for accessing basic input and output system (BIOS) data as described in item 1 of the scope of patent application, wherein the second data processor is connected to the ISA interface. 6. The device for accessing basic input and output system (BI os) data as described in claims 1, 2, 3, 4, or 5 in which the first data processor is Northbridge and the second data processing The device is the South Bridge. 7. The device for accessing basic input / output system (BIOS) data as described in the scope of patent application No. 1, 2, 3, 4 or 5, wherein m is 32, nl is 17, and n2 is 8. 8. A method for accessing basic input and output system (BI OS) data, characterized in that the related reading cycle includes the following steps:

G \ Program Files'Pat ent \ Q-0029. Ptd 15th Officer 470880 VI. Patent Application Scope (A) After the PCI address phase ends, the South Bridge bolt locks the address phase; (B) The South Bridge bolt locks After the address phase, the address data line of the PCI bus launches the required information of the basic input output system (BI OS) address; (C) the south bridge drive memory read signal and the basic input output system (BIOS) chip selection signal (D) Basic Input Output System (BI OS) transmits data to Nanqiao; (E) Basic Input Output System (BI OS) included in the launch of Southbridge contains data; (F) Announcing the completion of reading; and (G) End the read cycle. 9. A method for accessing basic input and output system (BIOS) data, which is characterized in that the related write cycle includes the following steps: (A) The central processing unit executes a write instruction and writes a piece of data through a PCI bus The memory stored in the Basic Input Output System (BI OS); (B) the Southbridge latches the written data; (c) the CPU executes the write instruction for the same data; and (D) the The pen data is written and stored in the memory of the basic input output system (BI OS).

C \ ProgramFi 1 es \ Patent \ Q-0029. Ptd page 16