TW469543B - Manufacture method of interconnect - Google Patents

Manufacture method of interconnect Download PDF

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TW469543B
TW469543B TW89128177A TW89128177A TW469543B TW 469543 B TW469543 B TW 469543B TW 89128177 A TW89128177 A TW 89128177A TW 89128177 A TW89128177 A TW 89128177A TW 469543 B TW469543 B TW 469543B
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patent application
semiconductor substrate
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TW89128177A
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Chung-Shi Liu
Shau-Lin Shue
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Taiwan Semiconductor Mfg
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Abstract

This invention provides a manufacture method of interconnect, which includes following steps: (a) a substrate is provided and has a metal contact on its surface; (b) A fluorine silicon glass (FSG) layer, a undoped silicon glass (USG) layer and a silicon-oxy-nitride (SiOxNy) layer are formed on the substrate; (c) the SiON layer, USG layer and FSG layer at the pre-determined area are removed through a dry etching process; (d) a barrier layer covering the bottom and side wall of the trench is formed on the substrate; (e) a copper layer is formed on the substrate to fill the trench; and (f) a chemical mechanical polish (CMP) process is carried out to remove the copper layer, the barrier layer and the SiON layer so that the copper layer has the same surface level as that of the USG layer.

Description

469543 五、發明說明α) 本發明係有關於一種内連線的製作方法，特別有關於 一種防止化學機械研磨製裎產生缺陷之内連線的製作方 法。 在半導體製程中，二氣化矽（s i 〇2)與氮化矽（s “队）材 質是最主要的介電材料’但由於Si 〇2具有較低之介電常數 k(約為4·卜，因此在内連線（interconnect)之間的内 金屬介電層（inter-metal dielectrics, IMD)係主要使用 Si Ο?材質’用來作為導線之間的隔離材質。然而，隨著半 導體元件之微小化而使内連線之間隔距離縮短，會導致内 連線之間的電谷值增加’因此必須改換具有更低介電常數 k之介電材料’來降低電容值並縮短RC之延遲時間，進而 改善電性表現。為了解決這個問題，目前採用氟矽玻璃 (fluorine silicon glass，FSG)作為 IMD 材質，並搭配使 用銅（Cii)金屬作為内連線材質，而成為一種Cu/FSG之内連 線結構。 請參考第1A至1 F圖，其顯示習知内連線之製作方法的 剖面示意圖。如第1A圖所示，一半導體基底10包含有一金 屬接觸窗（contact)12 ’係曝露於半導體基底10之表面。 如第1B圖所示’習知製作方法係先於半導體基底1〇表面上 沉積一 FSG層16 ’厚度約為4〇〇〇~20 000 A，再於FSG層16表 面上形成一氮氧化矽（Silicon_〇xy_nitride，層 18 ’係用來作為一抗反射塗佈層（anH_refiective coat ing’ ARC)，然後，如第ic圖所示，利用微影與蝕刻469543 V. Description of the invention α) The present invention relates to a method for manufacturing an interconnector, and more particularly to a method for manufacturing an interconnector to prevent defects caused by chemical mechanical polishing. In the semiconductor manufacturing process, silicon dioxide (si 〇2) and silicon nitride (s "team) materials are the most important dielectric materials', but because Si 〇2 has a lower dielectric constant k (about 4 · Bu, therefore, inter-metal dielectrics (IMD) between interconnects are mainly made of SiO? Material as the isolation material between the wires. However, with the semiconductor components The miniaturization will shorten the distance between the interconnects, which will cause the electrical valley between the interconnects to increase. Therefore, it is necessary to change the dielectric material with a lower dielectric constant k to reduce the capacitance value and shorten the RC delay. In order to solve this problem, fluorine silicon glass (FSG) is currently used as the IMD material, and copper (Cii) metal is used as the interconnect material to become a type of Cu / FSG. Interconnection structure. Please refer to Figures 1A to 1F, which show a schematic cross-sectional view of a conventional method for manufacturing interconnects. As shown in Figure 1A, a semiconductor substrate 10 includes a metal contact 12 ('contact exposure'). Yu Semiconductor The surface of the bottom 10. As shown in FIG. 1B, a conventional manufacturing method is to first deposit an FSG layer 16 on the surface of the semiconductor substrate 10 'and the thickness is about 4,000 to 20,000 A, and then on the surface of the FSG layer 16. A silicon nitride oxide (Silicon_〇xy_nitride, layer 18 'is used as an anti-reflection coating (anH_refiective coat ing' ARC), and then, as shown in Figure ic, using lithography and etching

製程定義形成一渠溝2〇，使其貫穿氮氧化矽層18以及FSGThe process definition defines a trench 20 that runs through the silicon oxynitride layer 18 and the FSG

0503-58557^ptd 第5頁 46 9543 五、發明說明（2) 層16，直至使金屬接觸窗12之表面曝露出來。其後，如第 1D圖所示’於半導體基底10表面覆蓋一阻指層22，並使其 覆蓋住渠溝2〇之侧壁與底部。阻擋層22係由TaN或Ta材質 所構成，其目的之一是用來阻止後續沉積之金屬進入FSG 層16或半導體基底1〇内部’其目的之二是用來增加後續沉 積之金屬與FSG層16或半導體基底1〇的附著能力。接著， 如第1E圖所示’利同電化學沉積方法，於半導體基底丨〇表 面上電鍍一Cu金屬層24，並使其填滿渠溝2〇。最後，如第 1F圖所示’利用化學機械研磨（chemicai mechanical polishing，CMP)方法’將半導體基底ίο表面上之cu金屬 層24、阻擋層22以及氮氧化矽層18去除，直至使⑼金屬層 24之表面面度與FSG層16之表面高度切齊。 然而’ CMP製程所使用之研漿（slurry)含有水分，而 且於CMP清洗化學環境中會使半導體基底1〇曝露在空氣或 水中’這均會使不穩定之F與Cu發生反應，進而侵害FSG層 16表面之Si-F鍵結。如此一來，以(；層16表面上會形成0503-58557 ^ ptd Page 5 46 9543 V. Description of the Invention (2) Layer 16 until the surface of the metal contact window 12 is exposed. Thereafter, as shown in FIG. 1D, a surface of the semiconductor substrate 10 is covered with a finger barrier layer 22, and it covers the sidewall and the bottom of the trench 20. The barrier layer 22 is made of TaN or Ta material. One of the purposes is to prevent the subsequently deposited metal from entering the FSG layer 16 or the semiconductor substrate 10. The other purpose is to increase the subsequently deposited metal and FSG layer. 16 or semiconductor substrate 10. Next, as shown in FIG. 1E, using the same electrochemical deposition method, a Cu metal layer 24 is electroplated on the surface of the semiconductor substrate and the trench 20 is filled. Finally, as shown in FIG. 1F, the 'cuicai mechanical polishing (CMP) method' is used to remove the cu metal layer 24, the barrier layer 22, and the silicon oxynitride layer 18 on the surface of the semiconductor substrate until the rhenium metal layer is removed. The surface degree of 24 is aligned with the surface height of the FSG layer 16. However, 'slurry used in the CMP process contains moisture, and the semiconductor substrate will be exposed to air or water in the CMP cleaning chemical environment'. This will cause unstable F to react with Cu, thereby damaging FSG. Si-F bonding on the surface of layer 16. As a result, (; layer 16 will form on the surface

Si-OH鍵結’而成為如第11?圖所示之山丘狀（hiU〇ck)缺陷 26 ’將會導致後續沉積之介電層自FSG層16剝落，或是在 後續沉積之介電層/FSG層丨6之介面間形成泡狀物 (bubbles)。 有鐘於此’本發明則提出一種内連線的製作方法，係 於FSG層與氮氧化矽層丨8之間提供—未摻雜矽玻璃 (undoped silicon giass，USG)層，可以有效解決上述之 問題。Si-OH bond 'and become a hill-like (hiUoc) defect 26 as shown in Fig. 11? Will cause the subsequently deposited dielectric layer to peel off from the FSG layer 16 or the subsequently deposited dielectric layer Bubbles are formed between the interfaces of the layer / FSG layer 6. There is a bell here 'The present invention proposes a method for manufacturing an interconnect, which is provided between the FSG layer and the silicon oxynitride layer-an undoped silicon giass (USG) layer, which can effectively solve the above Problem.

0503· 5855TUV.pt d 第6頁 46 954 3 - - 五、發明說明（3) 圖式簡單說明 第1A至1F圖顯示習知内連線之製作方法的剖面示意 圖。 第2A至2F圖顯示本發明第一實施例之内連線的製作方 法的剖面示意圖。 第3A至3C圖顯示本發明第二實施例之内連線的製作方 法的剖面示意圖。 [符號說明] 金屬接觸窗〜32 USG層〜36 渠溝〜40、48 Cu金屬層〜44 半導體基底、30 F S G層〜3 4 氮氧化矽層~ 3 8 阻擋層〜42 氮化矽層〜46 第一實施例 請參閱第2A至2F圖，其顯示本發明第一實施例之内連 線的製作方法的剖面示意圖^本發明第一實施例係提供一 種製作具有單一刻紋（single damascene)之内連線的方 法。如第2A圖所示，一半導體基底30包含有一金屬接觸窗 32，係曝露於半導體基底30之表面。如第2B圖所示，先於 半導體基底30表面上沉積一FSG層34，厚度約為 3000〜18000Α ’再於FSG層34表面上形成一未摻雜石夕玻璃 (undoped silicon glass，USG)層36，厚度約為 1 0 00〜2000 A。隨後於USG層36表面上形成一氣氡化石夕 (silicon-oxy-nitride, SiOxNy)層 38，係用來作為一抗0503 · 5855TUV.pt d p. 6 46 954 3--V. Description of the invention (3) Brief description of drawings Figures 1A to 1F show schematic cross-sectional views of a conventional method for making internal interconnections. Figures 2A to 2F are schematic cross-sectional views showing a method for fabricating an interconnect in the first embodiment of the present invention. 3A to 3C are schematic cross-sectional views showing a method for fabricating an interconnector according to a second embodiment of the present invention. [Symbol description] Metal contact window ~ 32 USG layer ~ 36 trench ~ 40, 48 Cu metal layer ~ 44 semiconductor substrate, 30 FSG layer ~ 3 4 silicon oxynitride layer ~ 3 8 barrier layer ~ 42 silicon nitride layer ~ 46 First Embodiment Please refer to FIGS. 2A to 2F, which are schematic cross-sectional views showing a method for manufacturing an interconnect in the first embodiment of the present invention. ^ The first embodiment of the present invention provides a method for manufacturing a single damascene Interconnection method. As shown in FIG. 2A, a semiconductor substrate 30 includes a metal contact window 32 exposed on the surface of the semiconductor substrate 30. As shown in FIG. 2B, an FSG layer 34 is deposited on the surface of the semiconductor substrate 30 to a thickness of about 3000 to 18000 A ', and then an undoped silicon glass (USG) layer is formed on the surface of the FSG layer 34. 36. The thickness is about 100 ~ 2000 A. Subsequently, a silicon-oxy-nitride (SiOxNy) layer 38 is formed on the surface of the USG layer 36, which is used as a primary antibody.

0503-5855Tff.ptd 第7頁 469543 五、發明說明（4) 反射塗佈層（anti-reflective coating, ARC)。然後，如 第2C圖所示，利用微影與蝕刻製程定義形成一渠溝40，使 其貫穿氮氧化矽層38、USG層36以及FSG層34，直至使金屬 接觸窗32之表面曝露出來。其後，如第2D圖所示，於半導 體基底30表面覆蓋一阻擋層42，並使其覆蓋住渠溝40之側 壁與底部。阻擋層42係由TiN、TaN或Ta材質所構成，是用 來阻止後續沉積之金屬進入FSG層36或半導體基底30内 部’並且能增加後續沉積之金屬與FSG層36或半導體基底 30的附著能力。接著，如第2E圖所示，利用電化學沉積方 法’於半導體基底30表面上電鍍一 Cu金屬層44，並使其填 滿渠溝40。最後，如第2F圖所示，利用化學機械研磨 (chemical mechanical polishing，CMP)方法，將半導體 基底30表面上之Cu金屬層44、阻擋層42以及氮氧化矽層38 去除，直至使Cu金屬層44之表面高度與USG層36之表面高 度切齊。 由於本發明方法在FSG層34表面上覆蓋USG層36，以 FSG/USG結構作為IMD，因此在對Cu金屬層44進行CMP製程 時’不會與FSG層34接觸，可以有效避免FSG層34表面之不 穩定的？與{：11發生反應，進而防止形成習知山丘狀缺陷。 如此一來，可以減緩後續沉積之IMD層之剝落現象，以確 保内連線之製程品質。 第二實施例 請參閱第3A至3C圖，其顯示本發明第二實施例之内連 線的製作方法的剖面示意圖。本發明第二實施例係提供一0503-5855Tff.ptd Page 7 469543 V. Description of the invention (4) Anti-reflective coating (ARC). Then, as shown in FIG. 2C, a trench 40 is formed by using a lithography and etching process definition, and penetrates the silicon oxynitride layer 38, the USG layer 36, and the FSG layer 34 until the surface of the metal contact window 32 is exposed. Thereafter, as shown in FIG. 2D, a surface of the semiconductor substrate 30 is covered with a barrier layer 42 so as to cover the side walls and the bottom of the trench 40. The barrier layer 42 is made of TiN, TaN or Ta material, and is used to prevent the subsequently deposited metal from entering the FSG layer 36 or the semiconductor substrate 30 'and to increase the adhesion of the subsequently deposited metal to the FSG layer 36 or the semiconductor substrate 30 . Next, as shown in FIG. 2E, a Cu metal layer 44 is electroplated on the surface of the semiconductor substrate 30 using the electrochemical deposition method 'to fill the trench 40. Finally, as shown in FIG. 2F, the chemical metal polishing (CMP) method is used to remove the Cu metal layer 44, the barrier layer 42, and the silicon oxynitride layer 38 on the surface of the semiconductor substrate 30 until the Cu metal layer is removed. The surface height of 44 is aligned with the surface height of USG layer 36. Since the method of the present invention covers the USG layer 36 on the surface of the FSG layer 34, and uses the FSG / USG structure as the IMD, the Cu metal layer 44 is not in contact with the FSG layer 34 during the CMP process, and the surface of the FSG layer 34 can be effectively avoided Unstable? Reacts with {: 11 to prevent the formation of conventional hill-like defects. In this way, the spalling phenomenon of the subsequently deposited IMD layer can be slowed down to ensure the quality of the interconnection process. Second Embodiment Please refer to FIGS. 3A to 3C, which are schematic cross-sectional views showing a method for manufacturing an interconnect in a second embodiment of the present invention. The second embodiment of the present invention provides a

0503-5855W.ptd 第8頁 469543 五、發明說明（5) 種製作具有雙重刻紋（dual damascene)之内連線的方法 如第3A圖所示，半導體基底30包含有金屬接觸窗32，— i 化矽層46係覆蓋住半導體基底30與金屬接觸窗32表面，1 FSG層34係覆蓋住氮化矽層46，USG層36係覆蓋住FSG層 34，以及氮氧化矽層38係覆蓋住USG層36。利用微影與钱 刻製程可定義形成一具有雙重刻紋輪廓之渠溝48，使 '其4 穿氮氧化矽層38、USG層36、FSG層34以及氮化石夕層46 了貝 至使金屬接觸窗32之表面曝露出來。其後，將氮氧化石夕直 38去除之後’於半導體基底30表面形成阻擋層42，以使$ 覆蓋住渠溝48之側壁與底部。接著，如第3B圖所示，利用 電化學沉積方法’於半導體基底30表面上電鍍^金屬層 44 ’並使其填滿渠溝48。最後，如第3C圖所示，利用化學 機械研磨（chemical mechanical p〇lishing，CMp)方法， 將半導體基底30表面上之Cu金屬層44與阻擋層42去除，直 至使Cu金屬層44之表面高度與USG層36之表面高度切齊。 雖然本發明已以一較佳實施例揭露如上，麸其並非用 以限定本發明，任何熟習此技藝者，在不脫離;^發明之精 神和範圍内’當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。0503-5855W.ptd Page 8 469543 V. Description of the invention (5) A method for making interconnects with dual damascene As shown in FIG. 3A, the semiconductor substrate 30 includes a metal contact window 32, — The siliconized layer 46 covers the surface of the semiconductor substrate 30 and the metal contact window 32, 1 the FSG layer 34 covers the silicon nitride layer 46, the USG layer 36 covers the FSG layer 34, and the silicon oxynitride layer 38 covers USG layer 36. The lithography and money engraving process can be used to define a trench 48 with a double engraved profile, so that its 4 penetrates the silicon oxynitride layer 38, the USG layer 36, the FSG layer 34, and the nitride nitride layer 46. The surface of the contact window 32 is exposed. Thereafter, after removing the oxynitride stone 38, a barrier layer 42 is formed on the surface of the semiconductor substrate 30 so that the sidewalls and the bottom of the trench 48 are covered. Next, as shown in FIG. 3B, the surface of the semiconductor substrate 30 is electroplated with a metal layer 44 'using an electrochemical deposition method' to fill the trenches 48. Finally, as shown in FIG. 3C, the Cu metal layer 44 and the barrier layer 42 on the surface of the semiconductor substrate 30 are removed by chemical mechanical polishing (CMp) method until the surface height of the Cu metal layer 44 is increased. It is highly aligned with the surface of the USG layer 36. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art will not depart from it; ^ within the spirit and scope of the invention, there should be some changes and retouching, so The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

469543 六、申請專利範圍 1. 一種内連線的製作方法，包括下列步驟： (a) 提供一半導體基底，其表面上包含有一金屬接觸 窗； (b) 於該半導體基底表面形成一氟矽玻璃（fluorine silicon glass, FSG)層，一未摻雜矽玻璃（und〇ped silicon glass, USG)層以及一氮氧化矽 (silicon-oxy-nitride，SiOxNy)層； (〇將預定區域之該5丨(^層、該1^0層以及該？36層去 除，以形成一可使該金屬接觸窗表面曝露出來之渠溝； (d) 於該半導體基底表面上形成一阻障層，以覆蓋住 該渠溝之底部與側壁； (e) 於該半導體基底表面上形成一銅（Cu)禽屬層，並 使其填滿該渠溝；以及 (f) 將該半導體基底表面上之該銅（Cu)金屬層、該阻 障層與該Si ON層去除，直至使該Cu金屬層之表面高度與該 USG層之表面高度切齊。 2. 如申請專利範圍第1項所述之製作方法，其中該渠 溝之輪廓係為單一刻紋（single damascene)。 3. 如申請專利範圍第1項所述之製作方法，其中該FSG 層之厚度為3000〜1 8000 A。 4. 如申請專利範圍第1項所述之製作方法，其中該USG 層之厚度為1 0 00〜200 0 A。 5 ·如申請專利範圍第1項所述之製作方法，其中該阻 障層係為群組Ta、TaN、TiN之〆種材質所構成。469543 VI. Scope of patent application 1. A method for manufacturing interconnects, including the following steps: (a) providing a semiconductor substrate including a metal contact window on the surface; (b) forming a fluorosilicon glass on the surface of the semiconductor substrate (Fluorine silicon glass (FSG) layer, an undoped silicon glass (USG) layer, and a silicon-oxy-nitride (SiOxNy) layer; (^ Layer, the 1 ^ 0 layer, and the? 36 layer are removed to form a trench that can expose the surface of the metal contact window; (d) forming a barrier layer on the surface of the semiconductor substrate to cover The bottom and sidewalls of the trench; (e) forming a copper (Cu) bird layer on the surface of the semiconductor substrate and filling the trench; and (f) the copper on the surface of the semiconductor substrate ( Cu) metal layer, the barrier layer and the Si ON layer are removed until the surface height of the Cu metal layer is aligned with the surface height of the USG layer. 2. The manufacturing method as described in item 1 of the scope of the patent application, The outline of the trench is a single engraving (single d amascene). 3. The manufacturing method described in item 1 of the patent application scope, wherein the thickness of the FSG layer is 3000 ~ 1 8000 A. 4. The manufacturing method described in item 1 of the patent application scope, wherein the USG layer The thickness is 1000 ~ 200 0 A. 5 · The manufacturing method as described in item 1 of the scope of patent application, wherein the barrier layer is made of a group of materials of groups Ta, TaN, and TiN. 469543 六、申請專利範圍 6. 如申請專利範圍第1項所述之製作方法，另包含一 步驟（g):於該半導體基底表面上形成一介電層’以覆蓋 住該銅（Cu)金屬層與該USG層之平坦表面上。。 7. —種内連線的製作方法，包括下列步驟： (a) 提供一半導體基底，其表面上包含有一金屬接觸 窗以及一氮化矽層係覆蓋住該半導體基底與該金屬接觸窗 之表面； (b) 於該半導體基底表面形成一氟矽玻璃（fluorine silicon glass, FSG)層，一未摻雜石夕玻璃（undoped silicon glass, USG)層以及一氮氧化矽 (silicon-oxy-nitride， SiOxNy)層； (c) 將預定區域之該Si ON層、該USG層、該FSG層以及 該氮化矽層去除，以形成一可使該金屬接觸窗表面曝露出 來之渠溝； (d) 將該Si〇N層去除； (e) 於該半導體基底表面上形成一阻障層，以覆蓋住 該渠溝之底部與側壁； (〇於該半導體基底表面上形成一銅（CU)金屬層，並 使其填滿該渠溝；以及 Cg)將該半導體基底表面上之該銅（Cu)金屬層與該阻 障層去除’直至使該Cu金屬層之表面高度與該USG層之表 面高度切齊。 8. 如申請專利範圍第7項所述之製作方法，其中該渠 溝之輪廓係為雙重刻紋（dual damascene)。469543 6. Scope of patent application 6. The manufacturing method described in item 1 of the scope of patent application, further comprising a step (g): forming a dielectric layer on the surface of the semiconductor substrate to cover the copper (Cu) metal Layer and the USG layer on a flat surface. . 7. — A method for making an interconnect including the following steps: (a) providing a semiconductor substrate, the surface of which includes a metal contact window and a silicon nitride layer covering the surface of the semiconductor substrate and the metal contact window (B) forming a fluorine silicon glass (FSG) layer, an undoped silicon glass (USG) layer, and a silicon-oxy-nitride, on the surface of the semiconductor substrate; SiOxNy) layer; (c) removing the Si ON layer, the USG layer, the FSG layer, and the silicon nitride layer in a predetermined area to form a trench that can expose the surface of the metal contact window; (d) Removing the SiON layer; (e) forming a barrier layer on the surface of the semiconductor substrate to cover the bottom and sidewalls of the trench; (0) forming a copper (CU) metal layer on the surface of the semiconductor substrate And make it fill the trench; and Cg) remove the copper (Cu) metal layer and the barrier layer on the surface of the semiconductor substrate until the surface height of the Cu metal layer and the surface height of the USG layer are removed Qi Qi. 8. The manufacturing method as described in item 7 of the scope of patent application, wherein the outline of the trench is a dual damascene. 469543 六，申請專利範圍 9.如申請專利範圍第7項所述之製作方法，其中該FSG 層之厚度為3000〜1 8000 A。 1 0.如申請專利範圍第7項所述之製作方法，其中該 USG層之厚度為1 000〜2000 A。 11.如申請專利範圍第7項所述之製作方法，其中該阻 障層係為群組Ta、TaN、T i N之一種材質所構成。 1 2.如申請專利範圍第7項所述之製作方法’另包含一 步驟（h):於該半導體基底表面上形成一介電層’以覆蓋 住該銅（Cu)金屬層與該USG層之平坦表面上。 13· —種内連線結構，包括有： 一半導體基底，其表面上包含有一金屬接觸窗； 一氟矽玻璃（fluorine silicon glass，FSG)層係覆 蓋於該半導體基底表面上； 一未摻雜矽玻璃（undoped silicon glass, USG)層係 覆蓋於該FSG層表面上； 一渠溝係貫穿該USG層與該FSG層’以使該金屬接觸窗 之表面曝露出來； 一阻障層係覆蓋於該渠溝之底部與側壁；以及 一銅（Cu)金屬層係填滿該渠溝，其中該Cu金屬層之表 面高度與該USG層之表面高度切齊。 1 4 _如申請專利範圍第1 3項所述之内連線結構，其中 該渠溝之輪廓係為單一刻紋（single damascene)。 1 5.如申請專利範圍第1 3項所述之内連線結構，其中 該渠溝之輪廓係為雙重刻紋（dua 1 damascene)。469543 VI. Application for patent scope 9. The manufacturing method as described in item 7 of the scope of patent application, wherein the thickness of the FSG layer is 3000 ~ 1 8000 A. 10. The manufacturing method as described in item 7 of the scope of patent application, wherein the thickness of the USG layer is 1 000 to 2000 A. 11. The manufacturing method as described in item 7 of the scope of the patent application, wherein the barrier layer is made of one material of the group Ta, TaN, T i N. 1 2. The manufacturing method described in item 7 of the scope of patent application 'another step (h): forming a dielectric layer on the surface of the semiconductor substrate' to cover the copper (Cu) metal layer and the USG layer On a flat surface. 13. · A kind of interconnect structure includes: a semiconductor substrate, the surface of which includes a metal contact window; a fluorine silicon glass (FSG) layer covers the surface of the semiconductor substrate; an undoped An unoped silicon glass (USG) layer covers the surface of the FSG layer; a trench runs through the USG layer and the FSG layer to expose the surface of the metal contact window; a barrier layer covers the The bottom and sidewalls of the trench and a copper (Cu) metal layer fill the trench, wherein the surface height of the Cu metal layer is aligned with the surface height of the USG layer. 1 4 _ The interconnect structure described in item 13 of the scope of patent application, wherein the outline of the trench is a single damascene. 1 5. The interconnecting structure as described in item 13 of the scope of the patent application, wherein the outline of the trench is dua 1 damascene. 16 95 4 3 六、申請專利範圍 1 6 ·如申請專利範圍第1 3項所述之内連線結構，其中 該FSG層之厚度為3000〜18000 A。 1 7 ·如申請專利範圍第1 3項所述之内連線結構，其中 該USG層之厚度為1 0 0 0〜2 000 A。 1 8 ·如申請專利範圍第1 3項所述之内連線結構，其中 該阻障層係為群組Ta、TaN、TiN之一種材質所構成。 1 9 ·如申請專利範圍第1 3項所述之内連線結構，另包 含有一介電層，係形成於該Cu金屬層與該USG層之平坦表 面上。16 95 4 3 VI. Scope of patent application 16 · The interconnect structure described in item 13 of the scope of patent application, wherein the thickness of the FSG layer is 3000 ~ 18000 A. 17 · The interconnect structure described in item 13 of the scope of patent application, wherein the thickness of the USG layer is 100 to 2000 A. 18 · The interconnect structure as described in item 13 of the scope of patent application, wherein the barrier layer is made of a material of group Ta, TaN, TiN. 19 · The interconnect structure described in item 13 of the scope of the patent application, which additionally includes a dielectric layer, is formed on the flat surfaces of the Cu metal layer and the USG layer. 0503.5855TW.ptd 第13頁0503.5855TW.ptd Page 13
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