TW475238B - Semiconductor manufacture process to prevent diffusion of fluorine atom - Google Patents

Abstract

This invention provides semiconductor manufacture process to prevent diffusion of fluorine atom of fluorinated silicate glass, which primarily deposits silicon rich oxide layer above and beneath the fluorinated silicon glass to function as barrier layer. According to the process of the present invention, using silicon rich oxide layer as barrier layer can effectively block the diffusion of fluorine atoms. Therefore, the use of low dielectric constant of fluorinated silicate glass can enhance the device performance by reducing the interconnect parasitic capacitance and RC delay, and also the attack of copper interconnect by fluorine atom can be prevented. Moreover, reliability of damascene copper process is increased as the silicon rich oxide layer can prevent the diffusion of copper atoms.

Description

475238 V. Description of the invention (1) [Field of the invention] The present invention relates to semiconductor process technology, and in particular, to the use of SiO2 oxide layer as a barrier layer, in order to avoid #fluorite sphere glass layer (FSG). The diffusion of fluorine atoms leads to the process of recording and bubbling metal wires. [Background of the Invention] With the increasing precision and complexity of integrated circuits, in order to be able to make sufficient metal interconnections on the surface of a finite chip, most of them are currently adopted; the three-dimensional structure of the connection to complete the connection of various components, And start with ^

The inter-dielectric layer (I MD) is used as a dielectric material to isolate each metal interconnect. Materials traditionally used as intermetal dielectric layers include: plasma silicon oxide (PE-OX), borophosphosilicate glass (BPSG), phosphosilicate glass (psG coated glass (S0G), etc.). With the development of the reduction of the size of components and the need to increase the operation speed, metals with low resistance constants have been gradually used as the material shifting of metal interconnects; = aluminum metal process technology 'in which the copper metal is embedded damascene) interconnect technology can not only reduce the size of interconnects: the problem of difficult copper metal etching is resolved ', so it has become the main trend of the line. Limenlian On the other hand, the development of component size reduction is not only emerging, but not only the use of lead technology of high-conductor copper materials in the library is in the ascendant, in order to be effective ;! V line parasitic capacitance and component _ delay 'Many processes have gradually changed to 475238 V. Description of the invention (2) ^ A dielectric material layer with a low dielectric constant (10wk), instead of general dielectric materials As a metal interlayer dielectric layer (MD). Recently, fluorine-doped silica glass (FSG, dielectric constant about 3.5) formed by high-density plasma chemical vapor deposition (HDPCVD) method has become an important material for making low-k dielectric metal interlayer dielectric layers. For one, it can be used alone or coexisting with undoped silica glass (USG) but in a larger amount to reduce the dielectric constant. However, after grinding or high-temperature tempering, the fluorine atoms in the fluorite-doped glass easily diffuse and attack metallic copper, especially after chemical mechanical polishing (CMP), the surface portion of the fluoro-doped silica glass layer is dampened ( m〇istured) and the generation of hydrofluoric acid ^^^ caused the copper wire rust and bubbling (corrosion and bubbling), which affects the properties of the element. Therefore, in order to make the application of fluorine-doped silica glass in the inlay copper process more perfect, it is necessary to seek improvement on the issue of fluorine atom diffusion. [Summary of the Invention] As the clock is here, the main purpose of the present invention is to provide a semiconductor process and a process for preventing the diffusion of fluorine atoms of fluorine-doped sand glass in order to solve the above-mentioned problems. In order to achieve the above-mentioned object, the method of the present invention provides a silicon-rich oxide layer alone above and below the fluorine-doped shattered glass. As a barrier layer to prevent the diffusion of fluorine atoms, the principle is to use ^ reference Dangling bonds in the oxide layer are used to capture the diffused fluorine atoms and achieve the effect of ^ & barrier.

Page 5 475238 V. Description of the invention (3) According to one type of bear of the present invention, the oxide layer of Lu Xieyu is used as a barrier layer: its glass layer is covered with a fluorosilicone glass layer on a semiconductor substrate ^ (V 'Dagger tongue. (A) Deposition on the glass layer; υυν deposited on the stone-rich oxidized layer on the upper surface to prevent the darkening of the chaotic atom · /

) In a silicon-rich oxide layer and a fluorine-doped silicon glass layer, a metal layer is deposited on the substrate and the artificial opening is filled. (D) The metal layer. θ Yazhen enters the above opening; and (e) smoothes the silicon-rich oxide layer according to another form of the present invention as a barrier layer, and deposits a silicon-rich oxide layer and a fluorine-doped silicon glass-rich oxide-rich oxide system It is used to prevent the metal layer from being deposited on the fluorite and glass-rich oxidized substrate and to fill the upper layer. The main steps under the fluorine-doped silicon breaking glass layer include: (a) a sequential glass layer on a semiconductor substrate, in which a barrier layer for diffusion of upper fluorine atoms; (b) an opening is defined in the layer; ( c) the openings described above; and (d) flattening the gold according to another form of the present invention, at the same time, a fragment-rich hafnium layer is provided as a barrier layer above and below the fluorine-doped silica glass layer, and its main steps include : (A) A first silicon-rich oxide layer, a fluorine-doped silicon glass layer, and a second silicon-rich oxide layer are sequentially deposited on a semiconductor substrate, wherein the first silicon-rich oxide layer and the second silicon-rich oxide layer serve as prevention A barrier layer for diffusion of fluorine atoms; (b) an opening is defined in the first rich stone oxide layer, the fluorine-doped stone glass layer, and the first rich stone oxide layer; (c) a metal layer is deposited on the substrate Fill in the opening, and (d) smooth the metal layer. In the present invention, a suitable stone-rich oxidized layer is one having a refractive index (r I) greater than 1.46, in particular, an electrode formed by using chemical polymerization to enhance chemical vapor deposition

475238 V. Description of the invention (4) Plasma silicon oxide layer (PEEx), such as PE-TEOS oxide layer of silicon. According to the invention, the above-mentioned rich oxide is used as a barrier layer, so in addition to using low dielectrics, robbing the parasitic capacitance between metal wires and the diffusion of fluorine atoms to attack the corrosion and blistering of copper wires (coorrosiori), In addition to the diffusion of this dream, the reliability of the post-type copper process can still be effectively prevented. In order to make the above-mentioned and obviousness of the present invention, the following detailed descriptions are given as follows: PE-SlH4 oxide layer or fucheng't use fluorite-doped silicon glass field to reduce stone-oxide, oxide layer (S i II can effectively block the diffusion of fluorine atoms, law-k)-low gold, but improve component properties , And can prevent and avoid the generation of hydrofluoric acid and lead wires and bubbling). 1 In addition, other purposes, features, and advantages of the oxide-rich oxide layer in addition to copper atoms that can block fluorine atoms can be more clearly described in the embodiment, and will be described in detail with the accompanying drawings [Simplified description of the drawings] Figures 12 and 4 are a series of cross-sectional views for illustrating a semiconductor process in which a silicon-rich oxide layer is used to prevent the diffusion of fluorine atoms in a preferred embodiment of the present invention. Fig. 5 (a) is a cross-sectional view for explaining another preferred embodiment of the present invention for a semiconductor process for preventing the diffusion of fluorine atoms with a rich oxide layer. ... Figure 6 is a cross-sectional view for explaining a further preferred embodiment of the present invention for a semiconductor manufacturing process using a rich oxide layer to prevent the diffusion of fluorine atoms. [Symbol description] 10 ~ semiconductor substrate;

475238 V. Description of the invention (5) 1 2 ~ fluorosilicone glass layer; 1 4 ~ silicon-rich oxide layer; 16 ~ photoresist; 18 ~ wire groove; 20 ~ metal copper; 2 ~ copper wire. [Embodiment] This embodiment is applied to the copper metal interconnection process of the mosaic structure according to the above method. For convenience, the following description uses only a single mosaic process as an example, but it should be understood that those skilled in the art can also apply On a dual damascene process. Please refer to Figs. 1 to 4, which are sectional views for explaining a preferred embodiment of the present invention. The manufacturing process of the present invention is applicable to a semiconductor substrate 10, such as a stone wafer, on which any two semiconductor elements, such as M 0 S transistors, resistors, logic elements, etc. can be formed, but to simplify the diagram here The formula is expressed only by the flat substrate 10. In the description of Υ, the term "substrate" refers to the t-pieces that have been formed on the semiconductor wafer and the various coatings on the wafer; the term "substrate surface" refers to the exposure of semiconductor wafers. The uppermost layer of the wafer, such as the surface of Shixi wafer, the marginal layer of Huiyi, metal wires, etc. As shown in Fig. 1, a fluorite-doped silica layer (FSG) 12 is deposited on the semiconductor substrate as an intermetal dielectric layer (IMD). For example, a high-density plasma chemical vapor deposition (HDPCVD) method can be used to deposit a gas layer ^ glass layer (FSG) 12. Next, on the above-mentioned doped Shixi glass layer (p $ Q) /

Page 8 475238 V. Description of the invention (6) --- A silicon-rich oxide layer 14 is formed on the barrier layer to prevent the diffusion of fluorine atoms. The above-mentioned silicon-rich oxide layer used as a barrier layer can be deposited by plasma chemical vapor deposition (PECVD) at a temperature lower than 400, for example, TE0s is the main reactant. The deposited PE_TE0s, or PE-Si Η # deposited by SlH4 as the main reactant, and by increasing the flow of TE0s or 8 丨 1 in the raw material gas, a silicon-rich oxide layer is formed. According to the present invention, in order to achieve an ideal barrier effect, the thickness of the silicon-rich oxide layer 4 is preferably greater than 50, A, and more preferably 500 to 丨 0 0 A. As shown in FIG. 2, a conventional trench imaging and etching procedure is used to define a wire trench 8 in the rich oxidized layer 14 and the fluorine-doped silica glass layer 2. First in _

After coating a photoresist layer 16 on the surface of the substrate, a lithography process is used to define a wire groove pattern in the photoresist, and then the reactive ion etching (RI E) is used to perform non-isotropic meal engraving. The pattern of the wire trench is sequentially transferred from the photoresist layer to the bottom-rich oxide layer 4 and the fluorine-doped silica glass layer 2 to obtain the result not shown in FIG. 2.

As shown in FIG. 3, a copper metal layer 20 is deposited on the surface of the substrate and fills the above-mentioned wire grooves 18. Before depositing the copper metal layer, a conformal barrier layer (not shown) can be deposited on the substrate to help the subsequent metal adhesion and prevent its diffusion. For copper, suitable barrier layer materials include: tantalum (Ta), tantalum nitride (TaN), nitrided town (WN) ', and titanium nitride (τn) commonly used in the art. Copper metal can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating (ECD). For example, an ionized metal plasma (IMP) can be used to form a seed layer of 3 00 ~ 1 500 A.

^ 75238 V. Description of the invention (7) Copper electroconductivity is formed on the seed layer by electroplating. The lower rod is inserted ... w, after the ten-arm electrical arm, 150 ~ 4 00 = two-force thermal sequence 'to reduce metallic copper. Resistance value. ), The above substrate is chemically and mechanically polished with ΓΛV (CMP 2 2 inlaid on: extra silicon on the silicon oxide layer 14 4) to obtain the uniform structure of the dielectric layer of the copper wire. In the above, During the process of thermal tempering and chemical mechanical polishing, due to the effect of the county floating bonds (bonds) in the silicon-rich oxide layer 14, the copper wire 22 can be prevented from being attacked by the fluorine atom to affect the components. In addition, since the silicon-rich oxide layer can also block the diffusion of copper atoms, covering it on the fluorosilica glass layer 12 can also prevent the residual metallic copper after chemical mechanical polishing from diffusing into the fluorosilica glass layer from above. FIG. 5 shows a semiconductor process in which a silicon-rich oxide layer is used to prevent the diffusion of gas atoms in another preferred embodiment of the present invention. According to another preferred embodiment of the present invention, the aforementioned silicon-rich oxide layer 14 can also be disposed under the fluorosilica glass layer 12, that is, a silicon-rich oxide is formed before the fluorosilica glass layer is deposited. Layer 'to prevent fluorine atoms from diffusing into the underlying semiconductor element. After a similar mosaic copper process as described above, the mosaic structure shown in Figure 5 can be obtained. FIG. 6 shows a semiconductor process in which another preferred embodiment of the present invention uses a silicon-rich oxide layer to prevent the diffusion of fluorine atoms. According to yet another preferred embodiment of the present invention, the aforementioned silicon-rich oxide layer 14 can also be disposed above and below the fluorosilica glass layer 12 to block the diffusion of fluorine atoms. After the similar inlay and loose copper process as described above, the inlay structure shown in Fig. 6 can be obtained.

Page 10 475238 V. Description of the invention (8) To further prove that the silicon-rich oxide layer of the present invention can actually block the diffusion of gas atoms and copper atoms, please refer to the following experimental data: Fluorine atom diffusion experiment

First, a high density plasma chemical vapor deposition method (HDPCVD) was used to deposit a fluorine-doped silica glass layer (fluorine content of about 10%) on the Shixi wafer, and then the chemical vapor deposition method was enhanced by plasma. (PECVD ^ deposits a variety of dielectric layers with a thickness of 100A, including the reflectivity} silicon-rich oxide layer. After the dielectric layer is deposited, most of the samples are tempered at 4 ° C. 2 Hours, and finally the secondary ion mass spectrometer (s I MS) was used to observe the diffusion of fluorine atoms. The results are shown in Table 1.

Si-rich P £ 〇X

PEOX PEOX — ^^ _ SiON_ [RI1.MJ ___ PUgQS _ [RLL461 TRI 1 Fire Yes Yes Yes Yes Yes No

It can be seen from Table 1 that 31 ^ 1, rich silicon 81 (^ and 8101〇 sentences are excellent fluorine rhenium: diffusion barrier layer, but its dielectric constant is too high (about 7 ~ 8) and is not suitable: use Original = IMD layer. In comparison, the silicon-rich silicon oxide layer (RI = 151) is also the same 2. It has a good diffusion barrier effect and has a general dielectric constant (about 4 extensions), which is very suitable for use in In the IMD layer, it acts as a barrier to prevent the diffusion of fluorine atoms. In addition, the general PE-TEOS and PEOX have too poor barrier effects, so they are not used as diffusion barriers. 475238 V. Description of the invention (9) --- a · Copper atom diffusion test was performed on another batch of silicon wafers. An oxide layer was formed by electro-enhanced chemical vapor deposition, and then a copper metal layer with a thickness of 丨 600 Å was deposited. Finally, various dielectric layers were deposited. Includes a silicon-rich oxide layer with a reflectivity of 1.51. After the deposition of the dielectric layer is complete, all samples are tempered at 4,000 t for 2 hours, and finally copper atoms are observed with a secondary ion mass spectrometer (S 丨 MS) In the case of diffusion, the results are shown in Table 2. Table 2

Si-rich PEOX SiN SiON SiON [Ri 1.M1 Diffusion degree 65λ 9〇A ιοοΑ ------- ΐδ〇Α As can be seen from Table 2, the silicon-rich oxide layer can also block the diffusion of copper atoms, so Covering the silicon-rich oxide layer on the fluorosilica glass layer can prevent the copper atoms from diffusing into the fluorine glass layer from above after CMP.

To sum up, according to the semiconductor process of the present invention using a silicon-rich oxide layer to prevent the diffusion of fluorine atoms, since the silicon-rich oxide layer is used as a barrier layer, the diffusion of fluorine atoms can be effectively blocked. Oxygen-doped glass with a dielectric constant (low -k) can reduce the parasitic capacitance and RC delay between metal wires to improve the properties of the device, and can prevent the diffusion of fluorine atoms to attack copper wires. In addition, the silicon-rich oxide layer used in the present invention can still prevent the diffusion of copper atoms and further improve the reliability of the damascene copper process. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to

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Claims (1)

1 · —1 j II. Including the following steps: a semi-conductive silicon oxide layer to prevent the diffusion of fluorine atoms— a fluorite glass layer on a semiconductor substrate; atomic diffusion: a chemical layer on the fluorite-doped glass layer, As the = S sand oxide layer and the aerated stone glass layer, a metal layer is deposited on the soil bottom and filled in the opening; the metal layer is smoothed. Fu Shixi 2 is the semiconductor process described in item 1 of the scope of the patent application, and the padding layer is formed by the plasma enhanced chemical vapor deposition method. The silicon oxide layer is a silicon-rich pE-S% oxide layer. Ί 4 · Semiconductor process as described in item 2 of the scope of patent application = Tian Shixi oxide layer is a silicon-rich PE-TEOS oxide layer. g 5. The half-way process as described in item 1, 2, 3, or 4 of the scope of the patent application, wherein the silicon-rich oxide layer has a refractive index greater than 1.46. g 6 · Semiconductor manufacturing process as described in item 5 of the scope of the patent application. Although the oxide layer has a refractive index of about i · 53. 7 • The semiconductor process as described in item 1 of the scope of the patent application. The metal layer is a copper metal layer. 8. The semiconductor manufacturing process as described in item 1 of the patent application. The opening includes an interconnecting trench. 9 · The semiconductor process as described in item 1 of the patent application. The opening includes a via window. System procedures, to prevent the opening of fluorine; Where ‘where the conductor system, where the, where the, where the, which where Said --- room number 8811680R VI. Patent application scope ____ Say ϋ 2 · Semiconductor manufacturing as described in the first patent application scope ^ The process of blasting Shi Xiboli, one of them. The $ layer is formed by a two-density plasma chemical vapor deposition method: the process 1 1 · A silicon-rich oxide layer to prevent fluorine atoms includes the following steps: A diffused semiconductor is sequentially deposited on a substrate, in which an upper barrier layer is formed ; Although the silicon oxide layer and a fluorine-doped silica glass layer are described in the half-fragment-rich oxide layer as preventing the diffusion of fluorine atoms, the fluorite glass layer and the silicon-rich oxide layer are determined as follows: & · Feather opening, deposition on the substrate-a metal layer and filling in the above-mentioned flattened metal layer. And the semiconductor process described in item n of the scope of the patent application, the "field stone oxide layer is formed by the use of plasma enhanced chemical vapor deposition method ^ 13. The semiconductor process described in the scope of the patent application, item 12, The silicon oxide layer is a silicon-rich PE-SiH4 oxide layer. 4. The semiconductor process as described in item 12 of the patent application scope, wherein the stone-rich oxide layer is a silicon-rich PE-TE0S oxide layer. / 5 · Semiconductor manufacturing as described in item 11, 12, 13, or 14 of the patent application scope, wherein the silicon-rich oxide layer is a refractive index greater than 1.46. 16. · Semiconductor manufacturing process as described in item 15 of the patent application scope Among them, the oxidized-rich layer is a refractive index of about 1.5 3. 1 7 · The semiconductor process as described in item 11 of the scope of patent application, wherein the metal layer is a copper metal layer. 1 8 · as in the scope of patent application丨 丨 The semiconductor process described in the above item, wherein 0503.4879TWl; Esmond.ptc 6 Application scope of patent The open 0 .. L includes an interconnecting trench ^ " n ^ ^ ^ ^ t t One of the semiconductor processes described in the fluorine-doped hafnium glass item. The drinking layer is formed by the local density electropolymerization chemical vapor deposition method. There are two kinds of two rich: oxide layer ... atomic diffusion of the semiconductor second oxygen:: layer pot-doped with wonderful glass layer, the second rich rich stone The oxide layer is composed of the first rich stone oxide layer and the second, θ 糸 as a barrier layer to prevent the diffusion of fluorine atoms; ΐΐ: Γ: an oxide layer, an aerated glass layer, and a rich oxygen on the substrate Depositing a metal layer and filling the opening; and smoothing the metal layer. The 2 ^ · semiconductor manufacturing process as described in item 21 of the scope of the patent application, wherein [A- and the second rich stone oxide layer are formed by using a plasma enhanced chemical vapor deposition method. • The semiconductor process as described in item 22 of the scope of patent application, wherein the first and second silicon-rich oxide layers are silicon-rich pE-SiH4 oxide layers. 24. The semiconductor process according to item 22 of the scope of application, wherein the first and second silicon-rich oxide layers are silicon-rich PE-TEOS oxide layers. 25. The semiconducting system described in item 21, 22, 23, or 24 of the scope of patent application, wherein the first and second silicon-rich oxide layers have a refractive index greater than 丨 · 46 or 0. s 26. The semiconductor process according to item 25 of the scope of patent application, wherein the first and second silicon-rich oxide layers have a refractive index of about 1.53. ^ 27. The semiconductor process according to item 21 of the scope of patent application, wherein the metal layer is a steel metal layer. ^ 28. The semiconductor process according to item 21 of the patent application scope, wherein the opening includes an interconnect line trench. • 29. The semiconductor process as described in item 21 of the patent application scope, wherein the opening includes a via window. 30. As described in item 21 of the scope of patent application, where: the fluorine-doped silica glass layer is formed by high-density plasma chemical vapor deposition