TW468237B - Improving method for peeling issue in the integrated circuit processing - Google Patents

Abstract

A method for forming integrated circuit is disclosed which can improve the peeling issue in the integrated circuit processing. The peeling issue often occurs at the integrated circuit area near the periphery region. The method for forming the integrated circuit first provides: a substrate on which has a high packing density region and a low packing density region and the high packing density region is adjacent to the low packing density region; and, forming a pattern layer on the low packing density region; then, forming a dielectric on the high packing density region and the pattern layer; finally, planarizing the dielectric.

Description

46 823 7 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing integrated circuits, and particularly to the peeling phenomenon caused by capacitor polycrystalline silicon exposed after planarization. 5-2 Invention Background: Generally, the manufacturing process of integrated circuits includes the process of four polycrystalline silicon layers and some metal interconnection processes. Of course, before this, the process of all components in the substrate must be completed. The so-called first polycrystalline silicon layer (poiyq) is mainly the gate conductive layer, which is the first polycrystalline silicon layer and the second polycrystalline silicon layer ( P〇ly_2) refers to the integrated circuit. Bit lines' are usually formed on the first polycrystalline silicon layer (poly-1), and the extension direction of this bit line is perpendicular to the gate β In order to achieve the effect of isolation 'at least one dielectric layer exists between the two polycrystalline stones. As for the third polycrystalline silicon layer, as shown in the first figure, it mainly refers to the semiconductor I & aa / lower eiectrode 102, which forms two poly, the second dielectric On the dielectric layer 101 above the electrical layer, this figure omits the first and the first " sand layer 'and the internal components of the substrate 100, only the relevant parts are shown

'46 82 3 7 5 'Invention Description (2)-: The above-mentioned polycrystalline silicon lower electrode 10 is in contact with the substrate 100, and in order to increase the surface area and charge storage capacity, the lower electrode portion has been developed Various shapes' such as a cylindrical shape, a hollow cylindrical shape, and the like. After the third dielectric layer is formed, a dielectric layer is formed thereon. This dielectric layer is used to separate two electrodes in a capacitor, and then a fourth polycrystalline silicon layer is formed ( p〇ly_4) 104 is used as an upper electrode on this dielectric layer 103. The above steps are the main steps for making capacitor electrodes in a conventional integrated circuit. In the case of forming multiple interconnects (_11; Bu 1 "611111: 61_ (: 〇111 ^ (: 1; 3)), a dielectric layer 5 is formed above the upper electrode to isolate it. Then, the dielectric layer 105 is planarized by a conventional process, so that the difficulty of the multiple interconnect process can be reduced. Referring to the second figure, when chemical mechanical polishing (CMP) is applied, After the dielectric layer 105 is planarized, the polycrystalline silicon layer (102 or ι04) of the capacitor electrode is often exposed due to excessive grinding in the integrated circuit area beside the peripheral region. In the next metal process, the titanium (Ti) material used as a glue layer will be attached to the exposed polycrystalline silicon, which will not only cause the short circuit of multiple interconnected parts and capacitors; The titanium material on polycrystalline silicon is prone to peeling, and the peeled titanium particles easily cause troubles in the post-reading process, that is, the metal layer at the edge of the peripheral region is prone to defects. °

d6B237 V. Explanation of the invention (3) For the above reasons, ‘in order to avoid peeling issues’, it is necessary to develop a method for forming integrated circuits to improve the quality of semiconductor products. 5-3 Purpose and Summary of the Invention: In the above background of the invention, there are many shortcomings in the traditional integrated circuit manufacturing process. The purpose of the present invention is to improve the capacitor exposing phenomenon after the planarization process. Another object of the present invention is to prevent the problem of peeling during the metallization process.

According to the above-mentioned object, the present invention provides a method for fabricating an integrated circuit. In this method, a substrate is first provided with -part- and -second parts thereon; and a first dielectric is formed. Layer on the first part and β on the second part Then, define a first conductor layer on the second dielectric layer of the first part as the capacitor lower electrode of this integrated circuit; form a second dielectric layer on the first On the conductor layer; a second conductor layer is formed on the second dielectric layer to serve as the capacitor upper electrode of the integrated circuit. Next, a second dielectric layer is formed on the second conductor layer and the first-dielectric drawer of the second part is formed into a fourth dielectric layer on the third dielectric layer; and then a photoresist is formed on the j-th layer.

46 8237 5. Description of the invention (4) On the dielectric layer, a patterned area has been formed in the photoresist layer above the second part; then the third and fourth dielectric layers above the second part are etched and then removed Photoresist layer. A fifth dielectric layer is formed on the fourth dielectric layer. Finally, the fifth dielectric layer is removed until the fourth dielectric layer is exposed. 5-4 Schematic description: The first diagram shows the junction surface of the capacitor in the edge area and the adjacent scribe line in the traditional integrated circuit. The second figure is a cross-sectional view showing the exposed capacitors after the planarization process of the conventional integrated circuit. The third to seventh figures are cross-sectional views showing the process flow of the integrated circuit proposed by the present invention. Representative symbols of the main parts: 10 substrates 11 dielectric layer 12 conductor layer 13 dielectric layer 14 conductor layer 15 dielectric layer 16 dielectric layer 17 photoresist layer

Page 7 46 823 7 V. Description of the invention (5) 18 Dielectric layer 100 101 102 103 104 105 Substrate dielectric layer conductor layer dielectric layer conductor layer dielectric layer 5-5 Detailed description of the invention: An embodiment can improve the peeling problem in the integrated circuit manufacturing process. Refer to the components of the element, such as the gate, in advance. It also forms the top surface of the contact window of the dielectric and non-specific device, which extends from the bottom three. First, a bottom formation is provided, but it will not be redundant here. Bit lines and dielectric layers are omitted. Therefore, connect the lower layer 11 'such as an oxide; then etch (anisotropic hole (contact holes) to the top surface of the bottom # 10, and use other components on the top 10), all of which are described in semiconductors, others are formed on semiconductors and so on. The step directly related to the present invention is to form a capacitor by using a program such as lithography (etch) on the substrate 10, and the dielectric layer 11 described by the dielectric layer 11 for the contact window hole is used for isolation.

Page 8 468237 V. Description of the invention (6) Deposit a conductive layer 12 such as polycrystalline silicon on the dielectric layer 11 and fill the contact window hole; then define the conductive layer 12 as a capacitor by lithography and truncation or other traditional procedures The round-shaped lower electrode 12 ′ and a hemi-spherical grain silicon (HSG silicon) structure are also formed thereon, and a part of the conductor layer 12 located in the peripheral region is also etched and removed; then A thin dielectric layer 13 such as an oxide or silicon nitride is deposited on the conductive layer 12; then another conductive layer 14 such as polycrystalline silicon is deposited, and the integrated circuit The capacitor is completed, in which the conductor layer 14 is used as an electrode on the capacitor. The above mainly describes the main steps in the fabrication of capacitors for integrated circuits in the semiconductor process. All the procedures are traditional and standard integrated circuit procedures, and the capacitors described above are less active than the peripheral regiron or other The surface is much higher, about 5,000 to 5,000 angstroms, and where there is a large difference in height, a single south-level dielectric layer is really impossible, and Even after flattening, it easily leads to the disadvantages described in the background of the invention. Therefore, the present invention provides a dummy layer structure formed in a peripheral regio or low active area. The height of this dummy layer is similar to that of a capacitor, so that it is formed. When a dielectric layer is used, the height difference between the high-positivity area and the low-positivity area is not much different. When planarized by the chemical mechanical polishing method, it can have a good effect, and can avoid the peeling problem that is easy to occur in subsequent processes. issue). The more detailed content is described below.

46 8237 V. Description of the invention (7) The aforementioned process ’The next step is to isolate the capacitor so that it cannot affect the metal process of multi-] _ evei erconnects. As shown in the fourth figure, a dielectric layer 15 such as an oxide is deposited on the conductive layer 14 and the dielectric layer 11 of the scribe line. This dielectric layer 5 will be used as a dummy layer; Deposit another dielectric layer 16 on the dielectric layer 15. This dielectric layer 16 is made of silicon nitride or any material with a high selectivity ratio; then a photoresist layer 17 is formed on the dielectric. On the layer 6, a pattern similar to the lower electrode of the capacitor has been formed above the scribe line or the low accumulation area. Opposite to this, the photoresist layer 17 is located in the part of the capacitor area or the high accumulation area. Without any pattern, and completely covering this area ^ After the dielectric layer 15 and the dielectric layer 16 are etched, the photoresist layer 17 is removed, and the resulting structure is shown in the fifth figure, in which all capacitors will be -Layer 15 is isolated; on the other hand, this dielectric layer 15 is located above the cutting path bis 1 and is etched into many cylindrical models (cylindrical dummies) # fractal like capacitors below the electrode. Because of this model layer, cutting Road '^., The south degree difference of the adjacent Leiguqi area has been reduced by y', and it is not even high Degree difference. 7 / again left. Also, the dielectric layer 16 that is deposited on the dielectric layer 15 has a thin protothema ^ The planarization process described below is from μ? Β 6 The termination layer in J is shown in the sixth figure, and a dielectric layer 18 such as a halide is deposited on the dielectric layer j and fills the gap between the models on the model layer 15 above. Θ on

46 823 7 V. Description of the invention (8) Referring to the seventh figure, the dielectric layer 18 is planarized by chemical mechanical polishing (CMP) until the dielectric having a high selection ratio is planarized. Until the electrical layer 16 is exposed, the dielectric layer 16 serves as a stop layer for the CMP process, and has a thickness of about 200 to 3000 angstroms. The above are merely preferred embodiments of the present invention and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

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Claims (1)

4 6 82 3 7 VI. Scope of patent application 1. A method for forming an integrated circuit, including at least: a substrate provided with a high accumulation area and a low accumulation area, and a high accumulation area and the low The accumulation regions are adjacent; a model layer is formed on the low accumulation region; a dielectric layer is formed on the high accumulation region and the model layer; and the dielectric layer is planarized. 2. The method according to item 1 of the patent application range, wherein the above-mentioned high accumulation area includes at least a capacitor, and the capacitor is located at an edge of the high accumulation area and the low accumulation area. 3. The method according to item 1 of the patent application range, wherein the above-mentioned low accumulation area includes a scribe line on the wafer. 4. For the method of the first item in the scope of patent application, wherein the line density of the high accumulation area is higher than the line density of the low accumulation area. 5. The method according to item 1 of the patent application scope, wherein the above model layer contains at least an oxide. 6. The method according to item 1 of the scope of patent application, wherein the model layer mentioned above includes at least nitride nitride. 7 · The method of claim 1 in which the above dielectric layer is at least Page 12 468237 Page 13 ^ β 82 3 7 6. Scope of Patent Application At least polycrystalline silicon is included. 11. The method of claim 9 in which the above-mentioned second dielectric layer contains at least an oxide. 1 2. The method according to item 9 of the scope of patent application, wherein the second dielectric layer includes at least silicon nitride. 1 3. The method according to item 9 of the scope of patent application, wherein the second conductive layer includes at least polycrystalline silicon. 14. The method according to item 9 of the scope of patent application, wherein the third dielectric layer described above includes at least an oxide. 15. The method as claimed in claim 9 wherein the fourth dielectric layer includes at least silicon nitride. 16. The method according to item 9 of the scope of patent application, wherein the third dielectric layer and the fourth dielectric layer are etched by an anisotropic etching method. 1 7. The method according to item 9 of the scope of patent application, wherein the fifth dielectric layer described above contains at least an oxide. 1 8. The method according to item 9 of the scope of patent application, wherein the fifth dielectric layer described above Page 14 46823 7 VI. Patent application scope It is removed by chemical mechanical polishing (CMP). Page 15