TW465191B - Phase-locked loop and device for reading and/or writing information from/onto a record carrier - Google Patents

Abstract

A phase-locked loop comprising: a controllable oscillator (1) for supplying an output signal (So) having a frequency which is dependent on a control signal (Sc); feedback means (2) for supplying a feedback signal (Sh) having a frequency which is proportional to the frequency of the output signal (So); first error signal-generating means (3) for generating a first error signal (Se) which is a measure of an average difference in phase between the feedback signal (Se) and a reference signal (Sref); second error signal-generating means (4) for receiving the first error signal (Se) and generating a second error signal (Sa), comprising A/D conversion means (4a) for converting the first error signal (Se) into a digital signal (Sd), digital memory means (4b) for memorizing the digital signal (Sd), and D/A conversion means (4c) for converting the digital signal (Sd) into the second error signal (Sa). The phase-locked loop has a first operational state in which the digital signal (Sd) memorized in the digital memory means is dependent on the reference signal (Sref), and a second operational state in which the digital signal (Sd) is independent of the reference signal (Sref). In addition, the phase-locked loop comprises switching means (9) for selecting the control signal (Sc) from the first error signal (Se) and the second error signal (Sa). In the first operational state, the first error signal (Se) is the control signal (Sc), and in the second operational state, the second error signal (Sa) is the control signal (Sc).

Description

4651 b V. Description of the invention (1) The present invention relates to a phase-locked loop, which includes-a controllable vibrator using t 乂 to provide an output signal with a fixed frequency according to a control signal,-a method for providing a A feedback device that is proportional to a feedback signal outputting a signal frequency, a first error signal generating device for generating a first error signal, the signal being a measured value of a phase difference mean between the feedback signal and a reference signal; and A second error signal generating device for receiving a first error signal and generating a second error signal, which includes a (!) Conversion device for converting the first error signal into a digital signal, and a digital memory for memorizing the digital signal Device, and a D / A conversion device that converts a digital signal into a second error signal; the phase-locked loop has a first operating state, where the digital signal stored in the digital memory device is determined by the reference signal and has a second Operation status, where the digital signal is not related to the reference signal. The invention also relates to a device for reading information from and / or embedding information into a record carrier, which device is provided with a phase-locked circuit as described above. For example, this type of phase-locked loop, referred to as PLL, is described in US 5, 028, 885. 'The well-known phase-locked loop can be used in digital telephone systems to reproduce another clock signal from the received input signal. The round-in signal is used as a reference signal. And it is better to continue to generate the clock signal even when there is no parameter :, and the clock signal _ can correspond to the reference signal break as much as possible. Clock signal immediately before the signal. In the known PLL, the first error signal of the phase detector is converted into

4 65ί 91 V. Description of the invention (2) Corresponding digital signal. The second error signal, which is the control signal of the controllable oscillator, is generated by the digital signal through the D / A conversion device and the low-pass filter. If there is no reference signal, it remains at the final value of the digital signal. It is advantageous to maintain the digital signal value with the oscillator's control signal unchanged, even when the reference signal has been interrupted for a long time. However, the known PLL has the disadvantage that the frequency of the output signal is unstable. This can be seen by referring to FIG. In this circle, a represents a curve indicating the reference signal frequency ffef. The b curve is the frequency of the feedback signal. It is assumed that the reference signal has a fixed frequency, and the frequency of the feedback signal has an initial value L, and the initial value is lower than the reference signal frequency a. However, the following description also applies when the initial value of the feedback signal is higher than the reference signal frequency β Due to the frequency difference between the reference signal and the reference signal, a phase difference exists between the two signals. In Fig. 1, the first error signal (shown by c) generated by the first error signal generating device represents the phase difference. In Fig. 1, d indicates a digital signal value generated by the A / D conversion device in response to the first error signal. Initially, the value is dl. Once the first error signal exceeds the preset value ct at time t1, the digital signal assumes the next digital value d2. The low-pass filter makes the frequency of the second error signal ′ and then the feedback signal b gradually increase. The second error signal is used as a controllable oscillator control signal. During the time period of 1: 2 at the time of arrival, the frequency of the feedback signal b is kept lower than the frequency of the reference signal ', so that the phase difference performance is increased. After time t2, the frequency of the feedback signal b will be higher than the frequency of the reference signal, so that the phase difference starts to decrease. At time t3, the phase difference will reach a level below the threshold value ct, which makes the number

; S5191 5. Description of the invention (3) The bit signal is assumed to be dl. Therefore, the frequency of the feedback signal b starts to decrease again. Because the frequency of the feedback signal is still higher than the frequency of the reference signal, the phase difference will continue to decrease until time 14 ^ to time 14, and the phase difference will start to increase again, so that the digital error signal will be assumed to be d2 at time 15. From this moment on, the phase-locked loop performs the state change process at time t1 to t5 as described above. From this, it is obvious that the output signal of the known phase-locked loop is not stable, but its frequency is changed periodically. The object of the present invention is to provide a phase-locked loop that does not produce output signal variation, even when the reference signal has been interrupted for a long time, and wherein the A / D conversion device does not cause any change in the output signal. According to the invention, the feature of the phase-locked loop also includes a phase-locked loop including a selection device to select the oscillator control signal by the first error signal and the second error signal. In the first operating state, the first error signal is the control Signal, and in the second operation state, the second error signal is the control signal. In the first operation state of the phase-locked circuit in accordance with the present invention, the analog error signal is converted into a digital signal by an A / D conversion device. The digital signal is stored in the digital memory device. "The digital signal is converted to the second error signal by the D / A conversion device." Under the second operation state, selecting the device will make the oscillator control signal correspond to the second error signal. β Because the phase-locked loop calibration is stored as a digital signal, the phase-locked loop calibration can be avoided. In the first operating state of the PLL, selecting the device causes the controllable oscillator control signal to correspond to the first error signal. Then, it is provided as a controllable oscillator control signal without being affected by the A / D conversion device β so as to avoid periodic changes in the phase-locked loop calibration.

Page 9 4 651 91 V. Description of the invention ⑷-A better example of a phase-locked loop in accordance with the present invention. A digital memory device can be regarded as consisting of an up-down counter, and an A / D conversion device can be regarded as including a comparison. And the up / down counter; the D / A conversion device is considered to include a comparator having a first input to receive a first error signal, a comparator having a second input to receive a second error signal, and a comparator coupled to the up / down counter The output of the input part 'wherein the up-down counter is also coupled to the turn-in part of the D / A conversion device, and the output of the D / A conversion device is provided as a second error message. This embodiment has the advantage that the comparator is sufficient for the A / D conversion device. Another advantage is that the digital signal is biased towards the second signal during the conversation, and it will hardly affect the second error signal. When there is a possibility of biasing to the second error signal, the comparator will generate a difference of 2: causing the up and down counter to start calibration to assume that the count value corresponding to the second a false signal will at least roughly match the first error Signal. The above and other features of the present invention can be specifically explained and explained below. “Tian Bu * Zhao Guan ’s example is clearly shown in the circular illustration: the different S ′ brother is a diagram showing a variety of phase-locked loop signals that do not conform to the principles of the present invention. FIG. 2 is a diagram showing a conforming example. Partial diagram, = 4 is the variation of various signals in this example, Figure 5 is another partial diagram of the example shown in Figure 2, and Figure 6 is a diagram that does not conform to the present invention; Principles, phase-locked loop application diagram of a device for reading information from a record carrier and writing information to the record carrier.

Page 10 465ί9ί 5. Description of the invention (5) The phase-locked loop shown in FIG. 2 includes a controllable oscillator 1 for providing an output signal So with a fixed frequency according to the control signal Sc. The pll also includes a feedback signal generating device 2 for providing a feedback signal sh having a frequency proportional to the output signal So frequency. The PLL further includes a first error signal generating device 3 for generating a first error signal Se. The signal is a measured value of the average phase difference between the feedback signal and the reference signal. The frequency of the feedback signal is, for example, 1/5 or 1/30 of the frequency of the output signal So, but it may also be the same as the frequency of the output signal So. When the same, the device I may be controlled by the vibrator 1 and the first error signal generating device. The input terminals of 3 are directly connected. The first error signal generating device includes a loop 3a and a loop 3b in this example. The loop 3a is used to calculate the signal Se '′, which is an instantaneous phase difference measurement value between the reference signal and the feedback signal. The loop 3-7 generates the first error signal Se ′ accordingly, where the error signal is the average phase difference measurement value between the feedback signal Sh and the reference signal Sref. The PLL further includes a second error signal generating device 4 for receiving a first error signal Se and generating a second error signal Sa. The second error signal generating device 4 includes an A / D conversion device 用来 for converting the first error signal se into a digital signal Sd, a digital memory device 4b, and a D / A conversion device 4c. The A / D conversion device 43 is used to convert the first error signal Se into a digital signal Sd '; the digital memory device 4b is used to store the digital signal Sd, and the D / A conversion device 4c is used to convert the digital signal Sd into an analog second error signal Sa. The phase-locked loop has a first operation state, in which the digital signal Sd stored in the digital memory device 4b depends on the reference signal Sref. And the phase-locked loop has a second operating state, wherein the digital signal Sd is related to the reference

4 6519 1 V. Description of the invention (6) Signal Sre / has nothing to do. The selection of the first operation state and the second operation state is determined by the state signal st. In this embodiment, the status signal st is generated by the test circuit 8 and the circuit detects whether a valid reference signal Sref is present to determine it. When the detection circuit 8 detects the occurrence of a valid reference signal Sref, the circuit shown in FIG. 1 will be set to the first operation state. In this state, the digital memory device 4b continuously memorizes the instantaneous value of the signal sd. The instantaneous value of the signal Sd is related to the instantaneous value of the reference signal Sref. For example, the digital memory device 4b is implemented as a "Sample-and-Hold" register, and in the first operation state, the register will be clocked at each built-in clock The signal Sd is sampled here. However, when the extraction circuit does not detect a valid reference signal Sref, the digital memory device 4b will maintain the final memory value of the signal Sd. The pll is in the second operation state, where the value of Sd has nothing to do with the reference signal sref. As for other specific embodiments consistent with the present invention, the state of the PLL is determined by the external status signal. The phase-locked loop according to the present invention also includes a control signal for selecting the control signal from the first error signal Se and the second error signal Sa. Sc 的 应用 装置 9。 Sc selection device 9. In this example, the phase-locked loop is in the first operation state, where the control signal Sc is the first error signal Se. In the second operation state, the control signal § (: is the second error signal Sa. In this example, the selection device 9 is also controlled by the status signal st. Figure 3 shows an example of the second error signal generating device: In this example, the digital The memory device 4b is composed of an up-down counter. The A / D conversion device is composed of a comparator 41, an up-down counter 42, and a D / A conversion device 43. The comparator 41 has a first input to receive a first error signal ge, And second

Page 12 465191 V. Description of the invention (7) Input to receive the second error signal Sa. The comparator 41 has an output coupled to the upper and lower input portions of the counter 42. The up-down counter 42 further has an input section to receive the clock signal C1 ′. The clock signal may be, for example, a reference signal Sref, but may also be provided by a separate clock signal generator. The up-down counter 42 also has an output portion coupled to the input terminal of the D / A conversion device 43. The output of the A conversion device 43 is provided as a second error signal. The operations of the elements shown in FIG. 3 can be explained with reference to FIG. The vertical solid line indicates the period of the clock signal C1. The comparator compares the first error signal se with the second error signal Sa 'and provides a difference signal s 在 at its output. The difference signal is a measurement of the difference between their analog signals (Se-Sa). In each clock pulse of the clock signal C1, the up-down counter 42 is incremented or decremented according to the polarity of the difference signal%. If the difference signal% is negative, the counter will assume the next lower value 'and if it is positive, the counter will assume the next higher value β. In the example, the up / down counter has a three-terminal upper and lower input terminal. In this embodiment, when the difference signal is higher than a preset positive value, the up-down counter is incremented. However, when the difference signal is lower than a preset negative value, the up-down counter is decremented, and when the difference signal is maintained at these Between preset values, the up-down counter remains unchanged. The up-down counter 42 provides a digital signal 5 (which is not shown in Fig. 4) representing its count value). In response to this, the D / A conversion device 43 generates a signal Sa having its corresponding analog value. In the example of FIG. 4, the value of the signal S a at time '10 is substantially equal to the error signal Se. In subsequent clock pulses of the clock signal C1, the up-down counter 42 is alternately set to the latest higher value corresponding to the second error signal Sa

Page 13 4β5 | 9ΐ V. Description of the invention (8) The count value of S1 "and the count value corresponding to the nearest lower value S1 '. The change of the second error signal Sa is unavoidable. This is due to the switching device 9 The first error signal Se is selected as the control signal sc to control the oscillator. At time U ', the first error signal is increased to Se2. The difference signal S5 is increased from Se1 S1' to S2-S1 " ^ Up and down counter 42 The count value gradually increases accordingly until the second error signal sa becomes S2 at time t2, which is the value closest to Se and higher than the value of Se. During the period from t2 to t3, the up and down counters 42 alternately Set the count value to correspond to the higher value S2 closest to the Se value, and the count value corresponding to the nearest lower value S2 'of the second error signal. At time t3' the first error signal is decremented Se3 »since After this moment, the second error signal Sa is decrementing 'until it becomes the lower value 33 closest to Se3,' after which the signal value is alternately set to S3 " and S3. For an example of selecting device 9, refer to Fig. 5. This figure It also shows circuit 3a, circuit 3b and ratio in more detail. Comparator 41. The loop 3a has a control element 31, which responds to the feedback signal Sh and the reference signal Sr ef, and generates signals Sup and Sdown to the current sources 32 and 33. When the feedback signal sh has a positive relative to the reference signal Sref When there is a phase difference, the current source 33 will be activated by the signal ° sd0wn in a certain period. When there is a negative phase difference, the 'current source 32 will be activated by the signal Sup in the same period. Therefore, the signal Se is The current represented by the measured value of the instantaneous phase difference "If there is no valid reference signal Sref, the status signal St will bring the control unit to 3 and ^ 〇 " signals do not start the current source

4 0519t V. Description of the invention (9)-The voltage represented by the measured value of the average phase difference. The selection device 9 has a first semiconductor element 91, a second semiconductor element 92, a second semiconductor element 93, and a current mirror (jjjrror) g4. The current mirror 94 can generate currents 12 and 13 equal to the current ii, The second error signal Sa is formed by the current i 1. When a valid reference signal sref is received, the state signal St makes the first semiconductor element 91 non-conductive. The voltage at the control electrode 92a of the second semiconductor element 92 is determined by the error signal Se generated by the circuit 3b. If there is no valid reference signal sref ', the state signal St will make the first semiconductor element 91 conductive, and the current sources 3 2 and 3 3 of the loop 3 a will be set to the off state. In this state, the voltage at the control electrode 92a of the semiconductor element 92 is determined by the electrical calendar Sa 'of the main electrode 93b of the third semiconductor element 93. The voltage Sa is a measured value of the current i2, and therefore it is also a measured value of the second error signal Sa composed of the current i1. The signal sc generated by the second semiconductor element 92 is thus related to the second error signal Sa in this state. The comparator 41 includes a half conducting element 4 4, a difference amplifier 45 and a voltage source 46. The current mirror 94 becomes part of the switching device 9 and the comparator 41. The function of the semiconductor element 44 is to serve as a current source of the current i 4 which generates a measurement value of the first error signal Se. The current mirror 94 generates a current i3 which is equal to the current i1 constituting the second error signal Sa. If i4 is greater than i3, a voltage greater than Vdd / 2 is generated at the non-converting input terminal of the difference amplifier. The difference amplifier then produces a positive difference signal. If i4 is smaller than i3, the voltage ′ at the non-converting input terminal of the differential amplifier 45 will be smaller than Vdd / 2 so that the negative amplifier generates a negative differential signal ^.

Page 15 465191 V. Description of the Invention (S) Figure S shows a phase-locked loop permanent application in accordance with the present invention for writing information to the optical record carrier 201 and reading information from the optically required record carrier 201. The reference numbers of the elements corresponding to the elements in FIG. 2 are increased by 100, respectively. For example, record carrier 201 is a record carrier that can be written a second time but can be read multiple times. On the other hand, a record carrier can also be, for example, a record carrier that can be repeatedly read and written and has an information layer with an amorphous structure material. The information layer can be continuously heated and cooled locally to transform it into a crystalline structure. Such materials are, for example, alloys of Te (tellurium), Se (smash), and Sb (antimony). For research on this alloy, please refer to G. Bouwhuis, J. Braat, A. Huyser, J. pasman, G. van Rosmalen and K. Schouhamer Iminink 'Adam

Hilger Ltd., Bristol 1985, "Principles of Optical

Disc Systems "B pages 219 to 225. In addition, the record carrier can be, for example, a magneto-optical type. The record carrier has an information layer made of magnetic material. The information layer can be locally heated by using a laser beam and a magnetic field. Above the Curie temperature to affect the magnetism. The device shown in the figure includes a phase-locked loop 101-104 for receiving the reference signal Sr ef in the first operation state and generating the output signal So from the reference signal S ref. In a specific example, the reference signal Sref is also a clock signal, especially a clock signal synchronized with the information to be written. The phase locked loop 101-104 includes an error signal generating device 103 for generating an error signal Se, of which The error signal Se is a measured value of the average phase difference between the reference signal Sref and the feedback signal Sh. The phase-locked loop 104 and 104 also include a signal for receiving the error signal Se and generating an oscillation control signal Sc related to the error signal Se Control signal generating device 104. The oscillator 101 can be controlled to provide an output signal So in response to the shock ΪΒΠ ·! 465191 V. Description of the invention (11) Control signal No. Sc. The feedback signal generating device 102 generates a feedback signal Sh in response to the output signal So. In the specific example shown in the figure, the feedback signal generating device 102 is composed of a frequency divider β. The device includes a control unit 207 for In the operating state, a pulsed conductor control signal Str is generated in response to the information signal S info and the output signal So. This control unit also uses the feedback signal Sh. For the content of the control unit 207, the application number PN in the reference file of this document Detailed description is available in 17.249. The pulse control signal can also refer to the description in the previous reference file file number PN 1 6. 325. The information signal Sinfo is generated by the input signal Sin. By using an error correction coding device 208 is used for error correction coding. Using the signal thus obtained, the information signal can be generated by the channel coding device 209 through channel coding. The channel coding device 209 can be, for example, a channel coding device like EFM, EFM +. In the first operation In the state, the transmitter 210 responds to the transmitter control signal Str 'and the information on the record carrier 201 The entity in layer 202 generates a detectable pattern. The device has a second operation state for reading information from the record carrier 201. The record carrier 201 may be a record carrier written by the device in the first operation state ' Or the record carrier has, for example, an information layer like a different method and a different device (such as a pressing method). The device further includes a transmitter 21 to generate a response to a physically measurable pattern in the record carrier in the second operation state. The reading signal Sis ◊ The transmitter 21 for generating the reading signal includes a wireless power supply 211. The device also includes a power supply device 20, which can provide power to

465191 V. Description of the invention (12) Wireless power supply 211. The power supply 207 is composed of a control unit 207. The control signal generating device 104 includes a memory device 142, which can memorize a memory value related to the error signal Se in the first operation state. In the second operation state, the 'control signal generating device 20 4 generates an oscillator control signal Sc in response to the memory value. In the second operation state, the phase-locked loop can control the output signal So of the oscillator 101 to cause high-frequency modulation of the power supplied by the power supply 207. In the example shown in the figure, the device is used to read and write data from and to the disk-shaped memory carrier 201. To this end, the device has a motor 213 to rotate the memory carrier 1 'and a driving device 214 to drive the motor 213. The orbital position of the guide 210 is determined by the servo system 215. The servo system 215 and the driving device 214 are controlled by a microprocessor 216. The motor 213, the drive unit 214, the servo system 215, and the microprocessor 216 are all conventional types. The device also includes a control unit 217 controlled by a microprocessor 216. The control unit 217 receives the Senss signal from one or more sensors, and responds to adjust the parameters of the control unit 207 through the serial bus 218. With these parameters, the power provided to the wireless power supply 211 is not affected by the aging and / or heat generation of the wireless power supply 211. At the same time, the power supplied to the wireless power supply can also be adjusted according to the state of the memory carrier 201, so that, for example, when the signal of the memory carrier 201 is present, the write signal can be recorded in a reliable manner. In the specific example shown in the figure, the device has a switch 281. The user can operate the switch 281 so that the device can be set to the first or second operation state. In the second operation state, the value of the information signal Sinfo can be maintained until the device is set to the first operation state again. in

Page 18 465191 V. Description of the Invention (Ϊ3) Other invited embodiments 褢 This device is used to read or write data to different types of memory carriers such as cassettes. In the specific example shown in the figure, the transmitter 2 10 is used to insert information into the record carrier and / or lock to read information from the record carrier. Alternatively, other transmitters can be used for reading and writing. People specific examples. The familiarity with this technology is also relevant to the application of various changes in the scope of innovation. The invention combines new features and innovative features.

Claims (1)

465191 VI. Scope of patent application 1. A phase-locked loop including-a controllable oscillator (1) for providing an output signal (s〇) with a fixed frequency in accordance with the control signal (Sc),-a for providing Feedback device (2) with feedback signal (Sh) proportional to output signal (So) frequency,-a first error signal generating device (3) for generating a first error signal (Se), the signal is a feedback signal The measured value of the average phase difference between the (sh) and the reference signal (Sref), a second error signal generating device for receiving the first error signal (Se) and generating the second error signal (Sa) (4), which includes an A / D conversion device (4a) for converting the first error signal (Se) into a digital signal (Sd), and a digital memory device (a) for remembering the digital signal (sd) ( 4 b), and a d / a conversion device (4c) for converting a digital signal (Sd) into a second error signal (Sa). The phase-locked loop has a first operation state, in which the digital signal (Sd) stored in the digital memory device depends on the reference signal (Sref), and has a second operation state, wherein the digital signal (Sd) is related to The reference signal (Sref) is irrelevant, and is characterized in that the phase-locked loop includes a switching device (g), so that the control signal (Sc) is selected by the first error signal (Se) and the second error signal (Sa). In one operation state, the first error signal (s0 is the control signal (Sc), and in the second operation state, it is the second error signal: (Se) is the control signal (sc) »2 · If requested The phase-locked loop of item 1 of the patent is characterized in that the digital memory device (4b) is composed of an up-down counter (42), and the analog / digital conversion device Ua) is composed of a comparator (41) and an up-down counter (42) ) And number 4 6St91 丨 丨 VI. Patent application range-composed of bit / analog conversion device (43), the comparator has a first input (+) to receive the first error signal (Se), and a second input to receive The second error signal (Sa), the comparator (41) has an output coupled to the upper and lower input portions of the counter (42). The up and down counter (42) also has a digital / analog conversion device (43 ) The output part of the input end, the digital / analog conversion. The output of the device (43) is provided as the second error signal (Sa). 3. If the phase-locked loop of item 1 or 2 of the patent application park is characterized, it is characterized by receiving a reference signal Sref and a detection device (8) 'the status signal St is used to indicate the phase-lock The circuit is in the first or second operating state. 4. A device for reading information from and / or writing information to an optical record carrier, including a phase-locked loop (100-104) such as the scope of patent applications 1 to 3, and the device includes The control unit (207) generates a pulse-shaped control signal (Str) in response to the information signal (Sinfo) and the output signal (So) of the phase-locked loop in the first operation state. The control signal (Str) is converted into an optically detectable pattern to the record carrier (201) in the operating state, and the transmitter (21) includes a wireless power source (211) to respond to the record carrier in the second operating state ( The optically detectable pattern on 2001) generates a read signal (Sis), and in the second operation state, the output signal So of the phase-locked loop will cause the supply of wireless power (2 11) to pass through. Modulated electricity. 5. The device according to item 4 of the scope of patent application is characterized in that the device also includes an error correction coding device (208) and / or a channel coding device (209), P.21 465191 VI. Patent Application Fan Yuan In order to generate information signal ⑻nf through error correction coding and / or bottle. ^ Channel coding by input signal ⑽) 6. If the device in the scope of patent application No. 4 'is characterized in that the device also includes an error correction coding device (231) and / or a channel coding device (^^) in order to pass errors Correct the encoding and / or channel encoding, and generate the output signal (Sout) by reading the signal (Sls). 0 Lion 2221PTT Page 22