WO2000039930A1

WO2000039930A1 - Phase-locked loop and device for reading and/or writing information from/onto a record carrier

Info

Publication number: WO2000039930A1
Application number: PCT/EP1999/010062
Authority: WO
Inventors: Albert H. J. Immink; Eise C. Dijkmans; Johannes A. T. M. Van Den Homberg
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 1998-12-24
Filing date: 1999-12-14
Publication date: 2000-07-06
Also published as: TW465191B

Abstract

A phase-locked loop comprising: a controllable oscillator (1) for supplying an output signal (So) having a frequency which is dependent on a control signal (Sc), feedback means (2) for supplying a feedback signal (Sh) having a frequency which is proportional to the frequency of the output signal (So), first error signal-generating means (3) for generating a first error signal (Se) which is a measure of an average difference in phase between the feedback signal (Se) and a reference signal (Sref), second error signal-generating means (4) for receiving the first error signal (Se) and generating a second error signal (Sa), comprising A/D conversion means (4a) for converting the first error signal (Se) into a digital signal (Sd), digital memory means (4b) for memorizing the digital signal (Sd), and D/A conversion means (4c) for converting the digital signal (Sd) into the second error signal (Sa). The phase-locked loop has a first operational state in which the digital signal (Sd) memorized in the digital memory means is dependent on the reference signal (Sref), and a second operational state in which the digital signal (Sd) is independent of the reference signal (Sref). In addition, the phase-locked loop comprises switching means (9) for selecting the control signal (Sc) from the first error signal (Se) and the second error signal (Sa). In the first operational state, the first error signal (Se) is the control signal (Sc), and in the second operational state, the second error signal (Sa) is the control signal (Sc).

Description

Phase-locked loop and device for reading and/or writing information from/onto a record carrier.

The invention relates to a phase-locked loop comprising a controllable oscillator for supplying an output signal having a frequency which is dependent on a control signal, feedback means for supplying a feedback signal having a frequency which is proportional to the frequency of the output signal, first error signal-generating means for generating a first error signal which is a measure of an average difference in phase between the feedback signal and a reference signal, second error signal-generating means for receiving the first error signal and generating a second error signal, comprising A/D conversion means for converting the first error signal into a digital signal, digital memory means for memorizing the digital signal, and D/A conversion means for converting the digital signal into the second error signal, the phase-locked loop having a first operational state in which the signal memorized in the digital memory means is dependent on the reference signal, and a second operational state in which the signal memorized in the digital memory means is independent of the reference signal. The invention also relates to a device for writing and/or reading information from/onto a record carrier, which device is provided with such a phase-locked loop.

A phase-locked loop of this type, hereinafter also referred to as PLL, is known from US 5,028,885. The known phase-locked loop may be used in digital telephony systems for regenerating a clock signal from a received input signal which functions as a reference signal. It is desirable to continue generating a clock signal, even when there is no reference signal, which clock signal corresponds as much as possible to the clock signal generated at an instant just before the reference signal drops out. In the known PLL, a first error signal of the phase detector is therefore converted into a corresponding digital signal in an A/D converter. A second error signal, which functions as a control signal for the controllable oscillator, is generated from the digital signal, consecutively by means of a D/A converter and a low-pass filter. In the absence of a reference signal, the last value of the digital signal is maintained. Maintaining the digital signal has the advantage that the control signal of the oscillator does not vary, even when the reference signal has been absent for a long time. However, the known PLL has the drawback that the frequency of the output signal is not stable. This is elucidated with reference to Fig. 1. In this Figure, "a" is a curve indicating the frequency f_ref of the reference signal. Curve "b" indicates the frequency of the feedback signal. The reference signal is assumed to have a constant frequency, and the frequency of the feedback signal has an initial frequency f, which is lower than the frequency of the reference signal. However, the descπption below also applies to the case where the frequency of the feedback signal is initially higher. Due to the frequency difference between the reference signal and the feedback signal, there is also a phase difference between these signals. The first error signal (indicated by c) in Fig. 1, generated by the error signal-generating means, is an indication of the phase difference. In Fig. 1, "d" indicates the value of the digital signal which is generated in response to the first error signal by means of the A D converter. Initially, this signal has the value dl. As soon as the first error signal exceeds a predetermined value ct at an instant tl, the digital signal assumes the next digital value d2. The low-pass filter causes the second error signal, and hence the frequency of the feedback signal b, to increase gradually, which second error signal functions as a control signal of the controllable oscillator. In the period until instant t2, the frequency of the feedback signal b remains smaller than that of the reference signal, so that the phase difference still increases. After instant t2, the frequency of the feedback signal is larger than that of the reference signal, so that the phase difference c will decrease. At instant t3, the phase difference has decreased to such an extent that it will be smaller than the threshold value ct, so that the digital signal assumes the value dl As a result. the frequency of the feedback signal b will decrease again. Since the frequency of the feedback signal is still larger than the frequency of the reference signal, the phase difference continues to decrease until instant t4 After instant t4. the phase difference c will increase again so that the digital error signal again assumes the value d2 at instant t5. From that instant, the phase-locked loop undergoes the same changes of state as in the peπod from t l to t5. It appears therefrom that the output signal of the known phase-locked loop is not stable but that its frequency v anes periodically

It is an object of the invention to provide a phase-locked loop which does not have a variation of the output signal, even when a reference signal is absent for a long time, and in which the A D converter does not cause any instabilities of the output signal. According to the invention, the phase-locked loop is therefore characteπzed in that the phase-locked loop also compπses selection means for selecting the control signal of the oscillator from the first error signal and the second error signal, the control signal being the first error signal in the first operational state and the second error signal in the second operational state. In the first operational state of the phase-locked loop according to the invention, the analog error signal is converted into a digital signal by the A/D conversion means. This digital signal is memoπzed by digital memory means. The digital signal is converted into a second error signal by the D/A conversion means. In the second operational state, the selection means cause the control signal of the oscillator to correspond to the second error signal. Since the adjustment of the phase-locked loop is memoπzed as a digital signal, a vaπation of the PLL adjustment is avoided. In the first operational state of the PLL, the selection means cause the control signal of the controllable oscillator to correspond to the first error signal. The control signal of the controllable oscillator is then supplied without mtervenience of the A/D converter. A peπodical vaπation of the frequency of the controllable oscillator is thereby avoided

An attractive embodiment of the PLL according to the invention is characteπzed in that the digital memory means are constituted by an up/down counter and the A D con\ ersιon means are constituted by a comparator, the up/down counter and the D/A conversion means, the comparator having a first input for receiving the first error signal and a second input for receiving the second error signal, and an output which is coupled to an up/dow n input of the counter, said up/down counter also having an output w hich is coupled to an input of the D/A converter, the output of the D/A converter supplying the second eπor signal This embodiment has the advantage that a comparator is sufficient for the A/D convener Another adv antage is that deviations in the conversion of the digital signal into the second error signal hardly have any consequences for the precision of the second error signal When there is a πsk of a deviation in the second error signal, the comparator generates a difference signal w hich causes the adjustment of the up/down counter to assume such a count that the corresponding second error signal at least substantially corresponds to the first error signal

These and other aspects of the invention are apparent from and will be elucidated w ith reference to the embodiments descπbed hereinafter In the drawings Fig. 1 shows diagrammatically the vaπation of several signals in a phase-locked loop not according to the invention,

Fig. 2 shows diagrammatically an embodiment of a phase-locked loop according to the invention,

Fig. 3 shows a part of this embodiment,

Fig. 4 shows the vaπation of several signals in this embodiment.

Fig. 5 shows another part of the embodiment shown in Fig. 2,

Fig. 6 shows the use of the phase-locked loop according to the invention in a device for wπting and reading information onto/from a record earner.

The phase-locked loop shown in Fig 2 compπses a controllable oscillator 1 for supplying an output signal So having a frequency which is dependent on a control signal Sc. The PLL also compπses feedback signal-generating means 2 for generating a feedback signal Sh having a frequency which is proportional to the frequency of the output signal So. The PLL further compπses first error signal-generating means 3 for generating a first error signal Se which is a measure of an average difference in phase between the feedback signal and a reference signal. The frequency of the feedback signal is, for example, 1/5 to 1/30 of the output signal So but may be alternatively identical to the frequency of the output signal So. In that case, the means I may be constituted by a direct connection between an output of the controllable oscillator 1 and an input of the first error signal-generating means 3 The first eπor signal-generating means compπse a circuit 3a and a circuit 3b in this case. The circuit 3a calculates a signal Se' which is a measure of an instantaneous difference in phase between the reference signal and the feedback signal The circuit 3b generates the first error signal Se therefrom, w hich error signal is a measure of an av erage difference in phase between the feedback signal Sh and the reference signal Sref

The PLL further compnses second error signal-generating means 4 for receiv ing the first analog error signal Se and for generating a second analog signal Sa. The second error signal-generating means 4 compπse A D conversion means 4a, digital memory means 4b and D/A conversion means 4c. The A D conversion means 4a conveπ the analog first eπor signal Se into a digital signal Sd. The digital memorv means 4b memonze the digital signal Sd The D/A conversion means 4c convert the digital signal Sd into the analog second eπor signal Sa The phase-locked loop has a first operational state in which the signal Sd memoπzed in the digital memory means 4b is dependent on the reference signal Sref. The PLL also has a second operational state in which the signal Sd memoπzed in the digital memory means 4b is not dependent on the reference signal Sref. The choice between the first 5 and the second operational state is determined by a state signal St. In the embodiment shown, the state signal St is generated by a detection circuit 8 which detects the presence or absence of a valid reference signal Sref When the detection circuit 8 detects the presence of a valid reference signal, the circuit shown in Fig 1 assumes the first operational state. In this state, the digital memory means 4b always memoπze the instantaneous value of the signal Sd. The

10 instantaneous value of Sd depends on the instantaneous value of the reference signal Sref. The digital memory means 4b are implemented, for example, as a sample-and-hold register which samples the signal Sd in the first operational state upon each clock pulse of the internal clock. When the detection circuit detects the absence of a valid reference signal Sref, the digital memory means 4b retain the last memoπzed value of Sd. The PLL is then in a second state in

15 w hich the value Sd is independent of the reference signal Sref. In another embodiment according to the invention, the state of the PLL is determined by an external state signal. The phase-locked loop according to the invention also compnses selection means 9 for selecting the control signal Sc of the oscillator 1 from the first error signal Se and the second eπor signal Sa In the Figure, the phase-locked loop is in the first operational state () in which the control signal Sc is the first error signal Se In the second operational state, the control signal is the second error signal Sa In this case, the selection means 9 are also controlled by ihe state signal St

An embodiment of the second eπor signal-generating means is shown in Fig. 3 In this embodiment, the digital memory means 42 are constituted by an up/down counter. The " \/I) conv ersion means are constituted by a comparator 41 , the up/down counter 42 and the I⁾' \ onv ersion means 43 The comparator has a first input for receiving the first eπor signal Sc and a se ond input for receiving the second error signal Sa The comparator 41 has an output hich is coupled to an up/dow n input u/d of the counter 42 The up/down counter 42 has a f urther input lor receiv ing a clock signal Cl which may be. for example, the reference

^;< > signal Sref hut may be alternatively supplied by a separate clock signal generator The up/dow n counter 42 also has an output w hich is coupled to an input of the D/A converter 43 The output of the D/A converter 43 supplies the second eπor signal.

The operation of the means shown in Fig 3 is elucidated with reference to Fig 4 The vertical solid lines indicate the peπods of the clock signal Cl The comparator compares the first error signal Se with the second error signal Sa and supplies a difference signal S_δ at its output, which difference signal is a measure of the difference (S_e-S_a) of these analog signals.

Upon each clock pulse of the clock signal Cl, the count of the up/down counter 42 increases or decreases, dependent on the polaπty of the difference signal S_δ- At a negative value of the difference signal S_δ, the count assumes a next lower value, and at a non-negative value, it assumes a next higher value. In one embodiment, the up/down counter has a tnvalent up/down input. In this embodiment, the count increases when the difference signal is larger than a predetermined positive value, and decreases when the difference signal is smaller than a predetermined negative value, and the count remains equal when the difference signal lies between these predetermined values. The up/down counter 42 supplies a digital signal S (not shown in Fig. 4) representing the count. In response thereto, the D/A converter 43 generates a signal S_a having a corresponding analog value.

In the example of Fig. 4, the value of the signal Sa at instant tO is substantially equal to the error signal Se. At consecutive clock pulses of the clock signal Cl, the up/down counter 42 alternately assumes a count which corresponds to the nearest higher value SI" and a count which corresponds to the nearest lower value ST of the second error signal Sa. The vaπation in the second eπor signal Sa is not objectionable because the switching means 9 select the first error signal Se as the control signal Sc for the controllable oscillator 1. At instant tl, the value of the first error signal increases to Se2. The value of the difference signal Sδ then increases from Se 1 -S 1 ' to S2-S 1 ". The count of the up/down counter subsequently increases stepwise until, at instant t2, the second eπor signal Sa has assumed a value S2" which is nearest to the v alue of Se and is higher than the value of Se. In the interval t2 to t3, the up/down counter 42 alternately assumes a count which coπesponds to the higher value S2' nearest to the value Se and a count which corresponds to the nearest lower value S2' of the second error signal At instant t3 the first eπor signal decreases to a value Se3. After that instant, the value of the second error signal Sa decreases until it has reached the lower value S3^' nearest to the value Se3. whereafter the value of the signal alternately assumes the value S3" and the value S3'.

An embodiment of the s itching means 9 is shown in Fig. 5. This Figure also shows in greater detail the circuit 3a. the circuit 3b and the comparator 41. The circuit 3a has a control unit 31 which, in response to the feedback signal Sh and the reference signal Sref, generates signals Sup and Sdovvn for the cuπent sources 32 and 33. When the feedback signal Sh has a positive phase difference with respect to the reference signal Sref, current source 33 is activated with the signal Sdown duπng a time interval. At a negative phase difference, current source 32 is activated with the signal Sup duπng an equally long time interval. The signal Se' is therefore a current which is a measure of the instantaneous difference in phase. In the absence of a valid reference signal Sref, the state signal St bπngs the control unit to a state in which the signals Sup and Sdown both deactivate the current sources. The circuit 3b with capacitive elements 34, 36 and resistive element 35 constitutes a filter for generating an error signal Se from this signal Se' This signal Se is therefore a voltage which is a measure of the average phase difference.

The switching means 9 are provided with a first semiconductor element 91, a second semiconductor element 92 and a third semiconductor element 93, and a cuπent mirror 94. The current mirror 94 generates currents ι2 and ι3 which are equal to a current ll constituting the second error signal Sa. When a valid reference signal Sref is being received, the state signal St renders the first semiconductor element 91 non-conducting The voltage at control electrode 92a of the second semiconductor element 92 is then determined by the error signal Se which is generated with the circuit 3b. In the absence of a valid reference signal Sref, the state signal St renders the first semiconductor element 91 conducting, and both current sources 32, 33 of the circuit 3a are deactivated. In this state, the voltage at the control electrode 92a of semiconductor element 92 is determined by the voltage Sa' at the main electrode 93b of the third semiconductor element 93 This voltage Sa' is a measure of the cuπent ι2 and hence a measure of the second error signal Sa constituted by cuπent l l. The signal Sc generated with the second semiconductor element 92 is therefore dependent on the second error signal Sa in this state The comparator 41 compπses a semiconductor element 44, a differential amplifier 45 and a voltage source 46 The current mirror 94 forms part of both the sw itching means 9 and the comparator 41 The semiconductor element 44 functions as a cuπent source generating a current ι4 which is a measure of the first error signal Se The cuπent mirror 94 generates a current ι3 which is equal to the current 11 constituting the second eπor signal Sa If ι4 is larger than ι3, a voltage which is larger than Vdd/2 is produced at the non-inv erting input of the differential amplifier The differential amplifier then generates a positiv e difference signal S§ At a value of ι4, which is smaller than ι3, the voltage at the non- lnveπing input of the differential amplifier 45 will be smaller than Vdd/2. so that the differential amplifier 45 generates a negative difference signal S

Fig. 6 shows an application of a phase-locked loop according to the invention in a dev ice for writing information onto an optical record earner 201 and reading information from an optical record earner 201 Components corresponding to those in Fig 2 have a reference numeral raised by 100 The record earner 201 is, for example, of the type which is wπtable only once, for example, a record earner of the ablative type. Alternatively, the record earner may be of a type which is rewπtable, for example, a record earner provided with an information layer of a mateπal having an amorphous structure which can be locally converted into a crystalline structure by consecutively heating and cooling the information layer. Such a mateπal is, for example, an alloy of Te, Se and Sb. A survey of such mateπals is given in "Pπnciples of Optical Disc Systems" by G. Bouwhuis, J Braat, A Huyser, J. Pasman, G. van Rosmalen and K Schouhamer Immink, Adam Hilger Ltd., Bπstol 1985, pp. 219-225. The record earner may be alternatively of, for example, the magneto-optical type. The record earners are provided with an information layer of a magnetizable mateπal. The magnetization is influenced by locally heating the information layer above the Cune temperature, for example, by means of a laser beam and by simultaneously applying a magnetic field. The device shown compπses a phase-locked loop 101-104 for receiving a reference signal Sref in the first operational state and for generating an output signal So from the reference signal Sref. In the embodiment shown, the reference signal Sref is also a clock signal, namely a clock signal which is synchronous with the information to be wπtten. The phase-locked loop 101- 104 compnses error signal-generating means 103 for generating an error signal Se which is a measure of an average difference in phase between the reference signal Sref and a feedback signal Sh The phase-locked loop 101-104 also compnses control signal-generating means 104 for receiving the error signal Se and generating an oscillator control signal Sc which is dependent on the error signal Se A controllable oscillator 101 supplies the output signal So in response to the oscillator control signal Sc Feedback signal-generating means 102 generate the feedback signal Sh in response to the output signal So In the embodiment show n, the feedback signal-generating means 102 are constituted by a frequency divider.

The dev ice compnses a control unit 207 for generating, in the first operational state, a pulsed transducer control signal Str in response to an information signal Sinfo and the output signal So The control unit also uses the feedback signal Sh The contiol unit 207 is descnbed in greater detail in the simultaneously filed application PHN 17 249 which is herein incorporated by reference The generation of a pulsed control signal is also descnbed in the previously filed application PHN 16.325 which is herein also incorporated by reference. The information signal Sinfo is generated from an input signal Sin An error coπection encoding is applied with the aid of the error correction encoding means 208 From the signal thus obtained, the information signal is subsequently generated by means of channel encoding w ith channel encoding means 209 The channel encoding means 209 are, for example. EFM or EFM+ channel encoding means In the first operational state, a transducer 210 generates physically detectable patterns in the information layer 202 of the record earner 201 in response to the transducer control signal Str.

The device has a second operational state for reading information from a record earner 201. The record earner 201 may be a record earner wπtten, in a first operational state, by means of the device but may be alternatively a record earner provided with an information layer in a different way. for example, in a different device, for example, a device in which the information layer is obtained by pressing. The device further compnses a transducer 210 for generating, in the second operational state, a read signal Sis in response to physically detectable patterns in the record earner. The transducer 210 for generating the read signal compπses a radiation source 211. The device also compnses a power supply 207 which supplies the radiation source 211 with an electπc power. The power supply 207 is constituted by the control unit 207 The control signal-generating means 104 compnse memory means 142 for memoπz g, in the first operational state, a memory value which is dependent on the error signal Se. In the second operational state, the control signal-generating means 204 generate the oscillator control signal Sc in response to the memoπzed memory value. In the second operational state, the output signal So of the controllable oscillator 101 of the phase- locked loop causes a high-frequency modulation in the electπc power supplied by the power supply 207 In the embodiment shown, the device is intended for reading and wnting information from/onto a disc-shaped record earner 201 To this end, the device has a motor 213 for rotating the record earner 1 , and a dπve unit 214 for dπving the motor 213. The radial position of the transducer 210 is determined by a servosystem 215. The servosystem 215 and the dπve unit 214 are controlled by a microprocessor 216. The motor 213, the dπve unit 214, the servosystem 215 and the microprocessor 216 are of a conventional type The device also compπses a control unit 217 controlled by the microprocessor 216 The control unit 217 receives signals Ssens from one or more sensors and, in response thereto, adapts parameters of the control unit 207 via a seπal bus 218 With these parameters, the supplied radiation power of the radiation source 21 1 is not influenced by ageing and/or heating of the radiation source 21 1. It is also possible to adapt the power supplied to the radiation source to the state of the record earner 201 so that, for example, also in the presence of fingerpnnts on the record earner 201 , the wπte signal can be recorded in a reliable manner. In the embodiment shown, the device has a switch 281 A user can operate this switch 281 so that the device assumes either the first or the second operational state In the second operational state, the value of the information signal Sinfo is maintained until the device again assumes the first operational state. In another embodiment, the device is intended for reading and wπting information from/onto a record earner of a different shape, for example, a tape-shaped record earner.

In the embodiment shown, the transducer 210 is used both for wπting information onto the record earner and for reading information from the record earner. Alternatively, different transducers may be used for reading and wπting information.

The invention is not limited to the embodiments descnbed hereinbefore. Many vanations within the scope of the appendant claims can be conceived by those skilled in the art. The invention also relates to each and every novel characteπstic feature and to each and every novel combination of charactenstic features.

Claims

CLAIMS:

1. A phase-locked loop compπsing a controllable oscillator (1) for supplying an output signal (So) having a frequency which is dependent on a control signal (Sc), feedback means (2) for supplying a feedback signal (Sh) having a frequency 5 hich is proportional to the frequency of the output signal (So), first error signal-generating means (3) for generating a first error signal (Se) which is a measure of an average difference in phase between the feedback signal (Se) and a reference signal (Sref), second error signal-generating means (4) for receiving the first error signal (Se) 10 and generating a second error signal (Sa), compπsing A D conversion means (4a) for converting the first error signal (Se) into a digital signal (Sd), digital memory means (4b) for memoπzing the digital signal (Sd), and D/A conversion means (4c) for converting the digital signal (Sd) into the second error signal (Sa), the phase-locked loop having a first operational state in which the signal (Sd) memoπzed in I the digital memory means (4b) is dependent on the reference signal (Sref), and a second operational state in w hich the signal (Sd) memoπzed in the digital memory means (4b) is independent of the reference signal (Sref). characteπzed in that the phase-locked loop also compπses selection means (9) for selecting the control signal ( Sc ) of the oscillator from the first error signal (Se) and the second error signal l l ( Sa l. the control signal (Sc) being the first error signal (Se) in the first operational state and the se on error signal (Sa) in the second operational state.

2 Λ phase-locked loop as claimed in claim 1 , characteπzed in that the digital memory means (4b ) are constituted by an up/down counter (42), and in that the A/D conversion means (4a) are constituted by a comparator (41 ), the up/dovvnconverter (42) and the D/Λ conv ersion means (43), the comparator (41 ) having a first input (+) for receiving the f irst cπor ignal (Se) and a second input (-) for receiving the second error signal (Sa), and an output w hich is coupled to an up/dow n input of the counter (42), said up/down counter (42) also having an output which is coupled to an input of the D/A converter (43), the output of the D/A converter (43) supplying the second error signal (Sa).

3. A phase-locked loop as claimed in claim 1 or 2, charactenzed by detection means (8) for receiving the reference signal (Sref) and generating a state signal (St) which indicates whether the phase-locked loop is in its first or its second operational state.

4. A device for reading and/or wπting information from/onto an optical record earner, compπsing a phase-locked loop (101-104) as claimed in any one of claims 1 to 3, which device compnses a control unit (207) for generating, in the first operational state, a pulsed control signal (Str) in response to an information signal (Str) and the output signal (SO) of the phase-locked loop, a transducer (210) for converting, in the first operational state, the control signal (Str) into optically detectable patterns on the record earner (201), a transducer (210) compπsing a radiation source (21 1) for generating, in the second operational state, a read signal (Sis) in response to optically detectable patterns on the record earner (201), while in the second operational state, the phase-locked loop causes the radiation source (211) to be supplied with a modulated electnc power.

5. A device as claimed in claim 4, characteπzed in that said device also compnses eπor coπection encoding means (208) and/or channel encoding means (209) for generating the information signal (Sinfo) from an input signal (Sin) by means of error coπection encoding and/or channel encoding

6 A dev ice as claimed in claim 4, characteπzed in that said device also compπses eπor coπection decoding means (231 ) and/or channel decoding means (230) for generating an output signal (Sout) from the read signal (Sis) by means of eπor coπection decoding and/or channel decoding