TW465093B - Manufacturing method of vertical metal-insulator-metal capacitor - Google Patents

Abstract

A manufacturing method of vertical metal-insulator-metal (MIM) capacitor is disclosed, which is suitable for the integrated manufacturing of memory devices and logic devices. Since there is a good processing environment during processing the logic circuits for the embedded DRAM process. It can match with the low temperature process (less than 450 DEG C), and reduce the height aspect ratio of the contact in the logic region.

Description

46 50 9 V. Description of the invention (1) The present invention relates to a semiconductor manufacturing method, and more particularly to a vertical metal-insulator-metal (MIM) capacitor manufacturing method used in semiconductor integrated circuits. For the capacitors used, Dakeey will use polysilicon capacitors formed by the structure of polysilicon-insulator-polycrystalline silicon; the structure of polya silicon-insulator-metalized polycrystalline silicon (or metal) will form the so-called μ ^ $ capacitor; or a metal-insulator-metal capacitor is formed by a metal-insulator-metal structure. Conventional MEMS or MEMS capacitors are all planarized to be compatible with the CMOS process, which simplifies the integration of the process. As far as MIM capacitors are concerned, there are also MIM capacitors [i_2] in 3D that have been widely used in advanced 1) 1 ^ 丨 1 manufacturing. The general characteristics of this 30- «11 ^ 1 capacitor are: small size, cylindrical or crown, use of high-k dielectric, and the use of complex Produced by the DR AM process. However, most of the above 3D-MIM capacitors are formed under the first layer of metal interconnects; as the front-end layer and the back-end layer will not match in process conditions Therefore, it is difficult to integrate both the DRA M and the logic circuit in process integration. It also causes serious height difference problems for both DRAM and logic circuits; for a contact structure, its height-to-opening ratio (height aspect ratio) increases. Recently, researches on embedded DRAM (that is, combining DRAM and logic circuits on the same chip) [3_4] have suggested that DRAM capacitors be placed in the second layer metal interconnect (metal-2) and the first layer metal Between the wires (metal-1). However, due to the thickness of the insulating layer between Hi e t a 1-1 and me t a 1-2

0503-5813TWF-3td Page 4 465093 V. Description of the invention (2) Can not be changed too much 'will make the capacitance value of the capacitor formed in the continuous process not change too much. Figure 1 shows a schematic cross-sectional structure of a conventional embedded DRAM. In the figure, the "Logic" indicates a region where a logic circuit is formed, and the "Memory" indicates a region where a dram memory is formed. Referring to FIG. 1, a plurality of memory elements (for example, M1, μ 2) and a plurality of logic elements (for example, LI, L2) are formed on the substrate 10;-the first insulating layer 11 covers the above-mentioned memory elements (Ml'M2) And logic elements (LI, L2). A contact plug (piUg) 12 is formed in the above-mentioned insulating layer 1 丨 to form electrical contact with the above-mentioned memory elements (M1, M2), and serves as a node contact of the dRAM storage capacitor. A first polycrystalline silicon layer (not shown) is usually formed on the above-mentioned insulating layer 11 in the memory area to constitute the internal connection of the memory. The second insulating layer 13 is further formed on the first insulating layer 11 and the contact plug 12. An opening area (for defining a storage capacitor) is formed in the second insulating layer 13 to expose the contact plug 2. A first (polycrystalline silicon) electrode layer 14 is formed in the above-mentioned opening area; a dielectric layer 15 (for example, a 0N0 layer) is formed on the first electrode layer 14, and then a second (polycrystalline silicon) electrode layer 16 is formed. It is formed on the dielectric layer 15 as shown in FIG. 1. The first electrode layer 14, the dielectric layer 15, and the second electrode layer 16 constitute a storage capacitor for a DRAM. Since the formation temperature of the above-mentioned dielectric layer (0N0 layer) 15 is more than 700 t; therefore, the metal process part of the Log i c part must be performed after the storage capacitor is completed.

0503-5813TWF-? Td Page 5 46509ο 5. Description of the invention ⑶ * * After completion of the MIMO part process', then a flattened third insulating layer 17 is formed on the above-mentioned second insulating layer 14 and the above-mentioned second electrode layer 16 . To perform the plug and interconnection process for the Logic part, the contact hole (ContaCt) 18 must be excavated in the third insulating layer 17 H edge layer 1 3 and the first-insulating layer 12, such as The area 'shown by the dotted line in the figure' can then be used to make electrical contact with the components in the Logic area during subsequent metallization processes. However, the contact holes 18 formed in this way will inevitably have an extremely high aspect ratio, which will affect the yield for the process control. In addition, the depth of the storage capacitor is limited by the thickness of the second insulating layer 3, which will reduce the capacitance of the storage capacitor and its adjustability. The completed article has a synopsis :: two books: the purpose is to propose-a kind of vertical metal-the second Du Xi effect person manufacturing method ^ ^, suitable for memory components and logic manufacturing, embedded DRAM (also That is, on the DRAM and logic circuits) process, it can be good when processing logic circuits. * At the same time, it can cooperate with the lower temperature (less than 450 t) process, and reduce the height of the contact hole in the LOglc area_opening ratio. Clothing Λ Purpose ’The first-type vertical metal insulator-metal capacitor manufacturing method proposed by the present invention includes the following steps metal ~

Ua) provides a semiconductor substrate; wherein, a semiconductor device and at least a logic device are on the top, a first semiconductor device and a logic device are formed on top, and a composite layer is formed on the upper ground and the top cover.辻 ί: ί A connection structure is formed in the above-insulative ~ the insulation should be the above, the memory element constitutes an electrical connection: and the connection structure Η 0503-5813TWF-ptd page 6

4650, Five 'invention description (4) The corresponding parts formed in the above-mentioned composite layer and the first insulation layer constitute an electrical connection and are exposed at the above-mentioned composite layer; j :; the logical element Π b) forming the second The insulating layer is on the composite layer; (1 c) the second insulating layer is etched to expose the composite layer above the structure; the operation is to use the second insulating layer as a first mask to etch The above region exposes the first connection structure ′ and is formed in the composite layer: (2) forming a first metal layer on the first connection structure, a sidewall of the upper region, and the second insulation layer; 幵 ( 10 removing the first metal layer formed on the second insulating layer and the upper end portion of the side wall; t, remaining in the above; the surface of the first metal layer on the wall and the surface of the composite layer are separated; (Ig) forming a dielectric layer on the first metal layer and the upper end portion of the upper side wall; < (lh) forming a second metal layer on the dielectric layer, and describing the opening area ; Wherein the above-mentioned subordinate layer formed on the above-mentioned opening region, The dielectric layer and the vertical MIM capacitor of the above-mentioned first metal layer structure. ^ -Hidden body To achieve the above-mentioned object, the second method for manufacturing a vertical insulator-metal capacitor proposed by the present invention includes the following: Step Straight metal (2a) provides a semiconductor substrate; wherein the base-less-memory element and at least one logic element 'a first insulating layer cover ^

(2g) forming a dielectric layer on the upper end portion of the first metal layer and the sidewall of the opening region; (2h) forming a first metal layer on the dielectric layer and filling the opening region; wherein, The second metal layer, the dielectric layer, and the first metal layer formed in the opening region constitute a vertical MIM capacitor of the memory element.

0503-5813TVF-pta Page 8 46 50 ^ V. Description of the invention (6) Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes preferred embodiments, In conjunction with the accompanying drawings, detailed descriptions are as follows: FIG. 1 is a schematic diagram showing a partial cross-sectional structure of an embedded DRAM; FIGs. 2a to 2g are cross-sectional views showing a flow of a first embodiment of the method of the present invention; and FIG. Figures a to 3g are cross-sectional views showing the flow of the second embodiment of the method of the present invention. Explanation of symbols: 10 ~ substrate; M1-M2 ~ memory element; U-L2 ~ logic element; 11 ~ first insulating layer; 12 ~ contact plug; 13 ~ second insulating layer; 14 ~ first Electrode layer; 15 to dielectric layer; 16 to second electrode layer; 17 to third insulating layer; 18 to contact hole; 20 to semiconductor substrate; MIM-MD2 to memory element; LD and LD2 logic element; 2 1 ~ first insulation layer; 2 2 ~ composite layer; 2 2a • ~ first intermediate insulation layer; 22b ~ second intermediate insulation layer; 23 ~ first connection structure; 24 ~ second connection structure; 2.4a ~ First contact plug; 24b to second contact plug; 25 to second insulating layer; 26 to first metal layer; 27 to photoresist; 28 to dielectric layer; 29 to second metal layer; 0P to open area 30 ~ semiconductor substrate; 3 first insulation layer; 32 ~ composite layer; 32a ~ first intermediate insulation layer; 32b ~ second intermediate insulation layer;

8503-551 3117 ·:, !! Page 9 4650g3 V. Description of the invention (7) ---- 3 3-¾ Coin ~ Connection structure: 33 丨 ~ Part 1; 3 32 ~ Part 1; 2-a ~ 3 \ —conductive plug; 34 ~ second connection structure; 3 4 3 \ Chudi first contact plug; 34b ~ second contact plug; 3 5 \ Le Er insulation layer; 36 ~ first metal layer; 37 ~ Photoresist: 38 ~ dielectric layer; 39 ~ second metal layer. Example: Figures 2a to 2g are cross-sectional views showing the flow of the first embodiment of the method of the present invention. In the figure, the "labeled Logic means the area where the logic circuit is formed (for example, composed of several MOS transistors)". Those who indicate Memory indicate the area where the DRAM memory is formed. First, referring to FIG. 2a, a semiconductor substrate 20 is provided; at least one memory element MD1 and at least one logic element LD1 are formed on the above-mentioned substrate 20;-the first-insulator 21 covers the memory element MD1 and the logic element LD1 — The composite layer 22 is formed on the first insulating layer 21 described above. Wherein, the composite layer 22 is composed of one to multiple layers of insulators (for example, teOS, IMD, etc.); in this embodiment, the composite layer 22 is composed of the first intermediate insulating layer 22a and the second intermediate layer. A two-layer structure composed of an insulating layer 22b. At least one first connection structure 23 is formed in the first insulation 21 and forms an electrical connection with the corresponding memory element MD1. In this embodiment, it is two contact plugs with conductivity (contact plug ). At least one second connection structure 24 is formed in the composite layer 22 and the first insulating layer 21 'and is electrically connected to the corresponding logic element LD1, and is exposed outside the composite layer 22. Wherein, the above-mentioned second connection structure

0503_5B13TWFpid Page 465093 V. Description of the Invention (8) 24 'Contains a first contact plug 24a formed in the above-mentioned first insulating layer; a first metal wiring layer metal-1 forms the above-mentioned first contact plug 24a And above the first insulation layer 21: a second contact plug 24b is formed in the first intermediate insulation layer 22a; a second metal wiring layer metM_2 forms the first contact plug 24b and the first intermediate insulation Layer 22a;

And, a second contact plug 2 4 c is formed after G in the second intermediate insulating layer 2 2 b ′, and a second insulating layer 25 is formed on the composite layer 22 first. Among them, the above-mentioned second insulating layer 25 is, for example, a thin oxide layer having a thickness of 2000 to 500 A. Next, 'etch the above-mentioned second insulating layer 25 and the composite layer 22 with a lithographic process definition until the above-mentioned first connection structure is exposed, and an open α region oop is formed in the above-mentioned composite layer'; as shown in FIG. Η. Remove The result of the photoresist layer after PR is shown in FIG. 2c. The above-mentioned opening area 0P is formed to define a storage capacitor required for the DRAM memory element MD1. A first metal layer 26 is formed on the first connection structure 23, The side wall of the above-mentioned opening region 0P and the above-mentioned second insulating layer 25; the result is not shown in Fig. 2d. Among them, the first metal layer 26 is selected from: Ti, TiN, Ti / TiN, TaN, w, WN One of them has a thickness of 200 to 500 A, and is formed, for example, by using a chemical vapor deposition method or a sputtering method at a temperature of less than 450 ° T. Next, a spin-on photoresist is first formed. 27 is coated on the first metal layer 26 'or a bottom anti-reflective layer (BARC) is formed on the first

Page 11 50 9 3 V. Description of the invention (9)-Above the metal layer 26 (both fill the above-mentioned opening area oop). Then, the photoresist 27 or the bottom reflective layer is etched, so that the resist layer 27 or the bottom reflective layer remains in the opening area oop. Among them, the spin-coated photoresist can be used to partially expose the coated photoresist 27 and then develop it. After the j-shirt, there is a part of the photoresist remaining in the above-mentioned opening area 0P. " Spin coating type photoresist 27 is used. Then, using the remaining photoresist 27 as a second mask, the above-mentioned metal layer 26 is etched to remove the second insulating layer 25 formed thereon, and the area is 0P The first metal layer ⑼ at the upper end portion of the side wall is as shown in FIG. E. Among them, the first metal layer 26 remaining on the side wall of the opening area OP is spaced from the surface of the second insulating layer 25—specially ( (Approximately 20 00 to 3000 A). ^ After removing the second mask, a dielectric layer 28 is formed on the metal layer 26 and the upper end portion of the sidewall of the opening region 0 {>. The dielectric layer 28 It is formed of a material with a high dielectric constant: for example, Ta2 05 with a thickness of 60 to 150 A. Because the Ta2a layer is formed, the sound is not equal to =, and the two metal layers will not affect the foregoing steps. (Eg: ΐ first connection structure). A second metal layer 29 is further formed on the dielectric layer 28, Moreover, the layer 29 is selected from: Ti, TiN, Ti / TiN, TaN, w, _, which is the genus, and the thickness is 2 0 ~ 5 0 0 A, for example, using chemical vapor deposition method, sputtering The method is formed at a temperature of less than 4 50 ec. It should be noted that the storage capacitor of the above-mentioned memory element 01 is formed by ①

Page 12 46509: Five 'invention description (ίο) ^ The above-mentioned second metal layer 29 in the above-mentioned opening area OP (as the electrode layer 1 above the storage capacitor; (^ -616 (; 1; 1'〇 {16 ), 0 of the above-mentioned dielectric layer 28, and 0 of the first metal layer 26 (as the bottom-electrode layer bottom-electrode of the storage capacitor) within the above-mentioned opening area 0P. In addition, 'the above-mentioned second metal layer 2 is formed 2 After 9th, chemical mechanical polishing (CMP) is used for planarization. 'The second metal layer 29, the dielectric layer 28, and the second insulating layer 25' located outside the opening area oop are removed to expose the second connection. Structure 24. A metallization process is performed to form the necessary third metal connection layer metah3 according to the application requirements; the result is shown in Figure 2§. Second embodiment: Figures 3a to 3f show the present invention Sectional flow chart of the second embodiment of the method. In the figure, 'Locic' indicates the area where the logic circuit is formed (for example, 'formed by a number of MOS transistors), and memory' indicates the area where the DRAM memory is formed. Area. Referring to FIG. 3a ', a semiconductor substrate 30 is first provided; The substrate 30 is formed with at least-a memory element MD2 and at least one logic element LD2:-a first insulating edge layer 31 covers the above-mentioned memory element MD2 and the logic element 1D2;-a composite layer 32 is formed on the above-mentioned first insulating layer The above 31. Among them, the above-mentioned composite layer 32 is composed of-to multiple layers of insulation (for example, TEOS, IMD, etc.); in this embodiment, the above-mentioned composite layer 32 is composed of the first intermediate insulation layer 32a and the second A double-layer structure composed of an intermediate insulating layer 3 2b. At least one first connection structure 33 has a first portion 33 and a second portion

D533-5B13TWF-1T Page 13 4b 93 V. Description of the invention (11) 3 32 'are formed in the above-mentioned first insulating layer 31 and the above-mentioned composite layer 32, respectively, and form electrical connection with the corresponding memory element MD 2 Sexual connection. In this embodiment, the first part 3 3! ′ Is two contact plugs with conductivity. The above-mentioned second portion ′ is composed of at least one conductive connection layer and conductive plugs which are sequentially and staggeredly formed on the above-mentioned first portion 3 3 ,; in this embodiment, the above-mentioned second portion 332 includes two Metal wiring layers (metal-1, metal-2) and two conductive plugs (339 a, 3 32 b), as shown in Figure 3a. At least one second connection structure 34 is formed in the composite layer 32 and the first insulation 31, and is electrically connected to the corresponding logic element LD2, and is exposed outside the composite layer 32. The second connection structure 34 includes a first contact plug 34a formed in the first insulating layer 31, and a first metal connection layer roe tal-1 forms the first contact plug 34a and the first contact plug 34a. Over two insulating layers 31; a second contact plug 34b is formed on the first

The second part 3 32 of the connection structure 33 is shown in the above-mentioned first connection structure 33 3c in the mouth area 0? '. Form the above-mentioned open area 0P,

Page 14 46 SO 93 V. Description of the invention (12) In order to define the storage capacitor required for DRAM memory element jjD2. Among them, the “removing the second part 3 32” of the first connecting structure 33 is completed by using a ZA 02 solution and using a mixed solution of CH3COOH / HNO3 / H3po4 / M. The H2O2 solution is used to remove the conductive plugs 33a a and 3 3211 in the second part 33s (both are composed of tungsten metal w, for example). ° The mixture of CH3COOH./HN03/H3P〇4/h2〇 The ratio, for example, 5: 5: 85: 5 is used to remove the second part 3 (the metal connection layer (metai-1, meta 2) in 32). Then, the first metal layer 36 is formed on the first -The first portion 33! Of the connection structure 33, the side wall 'second intermediate insulating layer 32b of the above-mentioned open area oop, and the above-mentioned second insulating layer 35: the result is shown in Fig. 3d. Among them, the above-mentioned first metal layer The 36 series is selected from: Ti, Ti N, Ti / TiN, TaN, W, ft N, and the thickness is 2,000 to 5,000 people. For example, using a chemical vapor deposition method, or a drop: bell method at temperature Less than 45 °. (: Formed under the conditions. Then, 'Spin_on' photoresist 37 is first coated on the first metal layer 36, or a bottom anti-reflective layer (BARC) is formed on the above Above the first metal layer 36 (both fill the above-mentioned opening area 0p). Then, the photoresist 37 or the bottom reflective layer is etched back to make the above-mentioned opening area. p Residual photoresist layer 37 or anti-reflection layer at the bottom is left. Among them, the use of a spin resistance of 3m can also partially expose the coated photoresist 37: light and shadow, and remain in the open area 0P after development. Some ^ In this embodiment, a spin-coating photoresist 37 is used. ° Then, using the remaining photoresist 37 as a mask, the above -36th is etched to remove the second insulating layer 25 formed above. Upper and lower layers

Page 15 4 6 5 Ο 9 3 V. Description of the invention (13) The interlayer insulating layer 32b and the upper end part of the side wall of the above-mentioned open area OP belong to the layer 36, and the result is shown in Fig. 3e. Among them, the first metal layer 36 of the 逄 f ° blade on the wall of the opening 与 and the composite space u have a specific interval d2 (about 200 0 to 3000 A). & ~~ After the above mask is removed ', a dielectric layer 38 is then formed on the upper-general layer 36 and the upper end portion of the sidewall of the above-mentioned open area OP. The metal dielectric layer 38 is formed of TagO5 or BST with a thickness of 60 to 150 A on the middle 'layer formed of a material having a high dielectric constant. Since the formation of D 3205 layer is less than 450 t ′, each metal layer of the foregoing step is not affected. At this temperature, a second metal layer 39 is further formed on the dielectric layer 38, and the above-mentioned opening area OP is formed. The result is shown in Fig. 3f. Among them, the μ, +. Filling layer 39 is selected from: Ti, TiN, Ti / TiN, TaN, W, WN, which is a thickness of 2 0 ~ 5 0, such as using chemical vapor deposition The sputtering method is formed at a temperature of less than 450 r. 'Or note that the storage capacitor of the memory element MD2 is composed of ① the second metal layer 39 (as the top-electrode of the capacitor above the capacitor layer) formed in the opening area 0P, and ② the dielectric layer. The first metal layer 36 (as the storage capacitor 3 | and the electrode layer bottom-electrode) in the above-mentioned opening area OP is composed of three. After the formation of the second metal layer 39, planarization is further performed using a chemical polishing method (CMP) to remove the second metal layer 39, the dielectric layer 38, and the second metal layer located outside the opening region oop. The insulating layer 35 exposes the second connection structure 34. The metallization process is then performed, and the necessary third metal connection layer meta 3 is formed according to the application; the result is as shown in Figure 3g.

〇503-5313TW? -P: d p. 16 ^ 65093 5. Description of the invention (14) It can be seen from the examples that the advantages of applying the method of the present invention include the following points: The formation of vertical MIM capacitors in the in-line DRAM is a low temperature (less than 450 C) process. Therefore, the thermal cycle when the capacitor is formed does not cause adverse effects on the contact plugs, metal connection layers, transistors, etc. in the previously formed logic elements, which can improve the yield. Because the contact plugs and metal connection layers in the logic components are formed before the MU1 valley trough, the contact holes will not have a great height-to-opening ratio. MIM! The depth of the storage capacitor is not limited to the two layers of metal-2, so the capacitance of the capacitor can be adjusted by changing the number and thickness of the composite layers. Although the present invention has been disclosed as above with two preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. References: [1] S.Kamiyama, J. Drynan, Y.Takaishi, and K.Koyama, M Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder

0503-5813TWF.ptd page 17 465093 V. Description of the invention (15) storage-node for 0.12 um-scale embedded DRAM ", Symposium on VLSI Technology, paper # 4A-4, p. 39-40, 1999.

[2] K. Kim, et. A 1., " A DRAM technology using MIM BST capacitor for 0.15 DRAM generation and beyond ", Symposium on VLS ί Technology, paper # 4A-1, p. 33-34, 1 999 .

[3] P.W. Diodato, et al, " Merged DRAM-LOGIC in the Year 2001 ", IEEE Transaction (1998).

[4] C.Y. Sun, et al, " Low Temperature Fully Planarized Capacitor-After-Metal-1-Process (CAMP) for Manufacturable Gigabit Scale Embedded DRAM Technologies ".

C5〇3-5S13T ¥ f p.18

Claims (1)

465093 方法. Method, suitable for providing memory element memory element; at least the above is recorded in the above-mentioned constituent electrical formation and logic element, a first connection junction memory element composite layer is connected, and the second insulation layer is exposed to the vertical Type metal-insulator-gold is used for memory element and logic element-semiconductor substrate: wherein the upper part and at least one logic element, a one-to-one composite layer structure is formed on the upper part to form an electrical connection; and in the first insulating layer The integrated manufacturing of the above-mentioned composite MIM capacitor manufacturing component includes: forming at least __ a first insulating layer covered on the substrate and a mystery formed in the first insulating layer and the first insulating layer, And corresponding to the first and first connection structure shapes and corresponding to the above-mentioned logic element layer; above;… define the second insulation layer and the composite layer above until the first connection structure is exposed and the above Forming an opening region in the composite layer; forming a first metal layer on the first connection structure, a side wall of the opening region, and the second insulating layer; A first metal layer on the second insulating layer and an upper end portion of the side wall of the opening area; wherein the first metal layer remaining on the side wall of the opening area and the surface of the composite layer are at a specific distance; An electric layer is formed on the first metal layer and the upper end portion of the sidewall of the opening region; a second metal layer is formed on the dielectric layer and fills the opening region; wherein the above is formed in the opening region The second metal layer, the dielectric layer, and the first metal layer constitute the vertical MIM capacitor of the shame body element. 2. The manufacturing method described in item 1 of the scope of patent application, wherein the above 465093 VI. Patent Application Park The second insulating layer is a thin oxide layer with a thickness of 200 ~ 500 A. 3. The manufacturing method as described in item 1 of the scope of patent application, wherein the metals' used in the first and second metal layers are all formed at a temperature of less than 450 ° C. 4 · The manufacturing method as described in item 1 of the scope of patent application, wherein the first and second metal layers are selected from: Ti, TiN, Ti / TiN 'TaN' W, WN 'and the thickness is 2 0 0 ~ 500 A. 5. The manufacturing method according to item 1 of the scope of patent application, wherein the first and second metal layers are formed using a chemical vapor deposition method or a base plating method. 6. The manufacturing method according to item 1 of the scope of patent application, wherein removing part of the first metal layer includes the following steps: forming a second mask on the first metal layer in the opening area, and exposing the second mask on the first metal layer; On the second insulating layer and on the first metal layer of the open end of the opening region; removing the first gold exposed from the second mask; removing the second mask ^ 'and 7_ 如For the manufacturing method described in the scope of the patent application, the formation of the second masking layer is to first form a photoresist layer, or a bottom protection layer, on the above first metal layer, and fill the opening area; Layer on the resist layer or the bottom reflective layer, and the photomask in the opening area j. The second cover of the war is the manufacturing method described in item 6 of the h-lead range above, and the complex cover is first formed with a photoresist layer on the above-mentioned "medium" cargo layer. 4 6 5〇 Scope of the patent application and fill in V ·, 4 ·, and the above-mentioned opening area; and then partially expose the photoresist layer to form the above-mentioned second mask in the -na opening area on μna '. 9. The manufacturing method as described in item 1 of the scope of patent application, with a 疋 interval of 2000 ~ 3000 A. Digong 10 · The manufacturing method described in item 1 of the scope of patent application, the electric layer is formed of a material with a high dielectric constant. The manufacturing method described in item 10 of the scope of patent application " electric layer The system is T a2 05 'and the thickness is 60 ~ 150 A. Form H, the manufacturing method described in item 1 of the scope of the patent application 'wherein' after the " first metal layer " is further flattened by chemical mechanical polishing method i to remove the second metal located outside the opening area Layer, dielectric and second insulation layer 'to expose the second connection structure. 1 ^ 13. The manufacturing method described in item 1 of the scope of patent application Yilang composite layer is composed of one to multiple layers of insulation. 14. The manufacturing method described in item 1 of the scope of patent application where the first connection structure is a conductive plug. 15. —The manufacture of a vertical metal-insulator „metal (MIM) capacitor is suitable for the integrated manufacturing of memory elements and logic elements, including: ^ providing a semiconductor substrate; wherein at least one of the above substrates is formed = The body element and at least one logic element, a first insulating layer, the body element and the logic element'-composite layer are formed on the first insulation element ^, and the at least one first-connection structure has first and second portions ^ / / The knife is formed in the first insulating layer and the composite layer to form an electrical connection with the memory element; at least one second connection structure has one of the upper, the upper, the upper, and the upper. 0503-5813IWF ptd Page 21 465093 VI. Patent application scope In the above composite layer and the first ~ insulating layer, an electrical connection is formed with the corresponding logic element and exposed outside the above composite layer; forming a second insulating layer on the above On the composite layer; the second insulating layer is engraved to describe the second part of the first connection structure; the second part of the first connection structure is removed, and an open area is formed in the composite layer; The first part of the first connection structure is exposed; a first metal layer is formed on the first part of the first connection structure, a side wall of the opening region, and the second insulation layer; and the first insulation layer is removed from the second insulation structure. And the first metal layer on the upper end portion of the side wall of the opening region; wherein the first metal layer remaining on the side wall of the opening region and the surface of the composite layer are at a specific distance; forming a dielectric layer on the first metal Layer 'and the upper end portion of the side wall of the above-mentioned opening area; forming a first metal layer on the above-mentioned dielectric layer' and filling the above-mentioned opening area; , The second metal layer is formed on the region of the opening on said dielectric layer, and said first metal layer above the MIM capacitor vertical type of memory device. I6. As described in item b of the scope of patent application. The product is manufactured by one manufacturer, wherein the second insulating layer is a samarium oxide layer having a thickness of 20 to 500 A. 1 7. The manufacturing method of Qiqifang described in Item 5 of the scope of patent application, wherein the metal used in the first and second metal layers ", " Formed at ° C. 1 8.As described in item 5 of the scope of patent application 05 03-5ei3TWF-ptii No. 22 guest ^ 650 ^-6. Scope of patent application Ti / TiN The above-mentioned first and second metal layer systems are selected from: Ti, TiN TaN, w, one of which has a thickness of 200 ~ 500 a. 19_ The manufacturing method according to item 15 of the scope of patent application, wherein the first and second metal layers are formed using a chemical vapor deposition method or a sputtering method. 20 · The manufacturing method according to item 15 of the scope of patent application, wherein removing a part of the first metal layer includes the following steps: forming a mask on the first metal layer in the opening area and exposing it A first metal layer formed on the second insulating layer and an upper end portion of a side wall of the opening region; removing the first metal layer exposed outside the mask; and removing the mask. 21. The manufacturing method according to item 20 of the scope of the patent application, wherein the formation of the masking layer is to first form a photoresist layer or a bottom anti-reflective layer on the first metal layer and fill the opening area. ; Etch back the photoresist layer or the bottom anti-reflective layer, and form the mask in the opening area. 2 2. The manufacturing method as described in item 20 of the scope of the patent application, wherein the above-mentioned mask is produced by forming a photoresist layer on the first metal layer and filling the opening area; The layer is partially exposed, and the mask is formed in the opening area after development. 2 3. The manufacturing method according to item 15 of the scope of the patent application, wherein the specific interval is 2000 to 3000 A. 24. The manufacturing method according to item 15 of the scope of patent application, wherein the dielectric layer is formed of a material having a high dielectric constant. 0503-5813TW? Ptd Page 23 4 6 5 0 6. Scope of patent application 2 5 * The manufacturing method described in item 24 of the scope of patent application, wherein the dielectric layer is Ta205 and the thickness is 60 to 150 A. 2 6. The manufacturing method as described in item 15 of the scope of the patent application, wherein / after the formation of the second metal layer, a chemical mechanical polishing method is used for planarization to remove the second metal located outside the opening area Layer, dielectric | layer 'and first insulating layer to expose the above-mentioned first connection structure. 2 7. The manufacturing method according to item 15 of the scope of the patent application, wherein the composite layer is composed of one to multiple layers of insulators. 2 8. The manufacturing method according to item 15 of the scope of patent application, wherein the first part of the first connection structure is a conductive plug. 29. The manufacturing method according to item 15 of the scope of patent application, wherein the second part of the first connection structure is formed by at least one conductive layer and conductive plugs in a staggered order in the first connection structure. Constituted on the first part. 30. The manufacturing method as described in item 29 of the scope of the patent application, wherein removing the second part of the first connection structure is using an H2O2 solution, and the composition is used in combination with CICOOH / HNOs / HsPO〆1120. Complete with liquid. 0503-58I3T ^^ ptd Page 24