TW464975B - Method and apparatus for compensating non-uniform wafer processing in plasma processing chamber - Google Patents
Method and apparatus for compensating non-uniform wafer processing in plasma processing chamber Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/205—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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Abstract
Description
4 6 4 9 7 υ 五、發明說明（1) 發明背景 發明之領域 本發明係一種電漿處理室中之不均勻晶圓處理的補償 方法與設備’更明確地說’此方法與設備可改進半導體電 漿處理系統中電聚處理的晶圓均勻度。 相關技術之描述 半導體處理系統係用來處理積體電路製造中的半導體 晶圓，例如’半導體的電漿製程通常會用於蚀刻、氧化、 化學乱相沈積[chemical vapor deposition(CVD)]等製 程’這些半導體的電漿製程基本上係藉由電漿處理系統達 成’且通常皆包含一電漿處理室以提供一可控制的設定環 境。 傳統的電聚處理室往往包含靜電爽具（electrostatic chuck)來固定待處理的晶圓（亦即矽晶圓或基板），靜電夾 具利用靜電力將晶圓夾至夾具上，通常可將其分成單極與 雙極靜電夾具兩類’單極靜電夾具具有單極、而雙極靜電 夾具則具有雙極’靜電夹具係廣為人知的習用技術且已有 大1的討論’例如’由Francois Guyot與他人共有之美國 專利 5,789. 904號、標題為「High Power Electrostatic Chuck Contact」’ J〇nes et al.之美國專利f請案 08/624,988 號、.標題為「Dynamic Feedback Electrostatic Wafer Chuck」 ，Kubly et al.之美國專 利5，793，192 號、標題為「Method and Apparatus for4 6 4 9 7 υ 5. Description of the invention (1) Background of the invention The present invention relates to a method and equipment for compensating for uneven wafer processing in a plasma processing chamber, 'more specifically,' this method and equipment can be improved Wafer uniformity for electropolymerization processing in a semiconductor plasma processing system. Description of related technologies Semiconductor processing systems are used to process semiconductor wafers in integrated circuit manufacturing. For example, the semiconductor plasma process is usually used for processes such as etching, oxidation, and chemical vapor deposition (CVD). 'The plasma processing of these semiconductors is basically achieved by a plasma processing system' and usually includes a plasma processing chamber to provide a controllable setting environment. Traditional electropolymerization processing chambers often include electrostatic chucks to hold wafers to be processed (ie, silicon wafers or substrates). Electrostatic clamps use electrostatic forces to clamp wafers to the clamps, which can usually be divided into There are two types of unipolar and bipolar electrostatic clamps: 'unipolar electrostatic clamps have unipolar and bipolar electrostatic clamps have bipolar' electrostatic clamps are well-known conventional techniques and have been discussed in large numbers. For example, by Francois Guyot and others Co-owned U.S. Patent No. 5,789.904, U.S. Patent No. 08 / 624,988, titled "High Power Electrostatic Chuck Contact" 'Jones et al., And "Dynamic Feedback Electrostatic Wafer Chuck", Kubly et al. US Patent No. 5,793,192, entitled "Method and Apparatus for
第5頁 4 6 4，：_______ . 五、發明說明（2)Page 5 4 6 4: _______. V. Description of the Invention (2)
Clamping and Declamping a Semiconductor Wafer in a Wafer Processing System」，這些前案揭露皆在此作為 參考。 圖1所示之橫剖面圖係一央住晶圓丨〇 2之靜電夾具範例 [exempUry electrostatic chuck(ESC)]，靜電夾具 1〇〇 包含介電層106與Π0、及一層電極1〇8，電極108配置在介 電層106與110之間，並被設為一雙極esc配置中之一對極 子108A與108B，其間並具有一絕緣層。 極子108A與108B分別被連接至一電源丨12之正負端 子’所以，極子108A為正偏壓、極子i〇8B則為負偏壓，極 子108A與108B的偏壓電位會在介電層1〇6與11〇毗鄰之表面 區域感應出電荷，例如，極子108A上之介電層106的底表 面區域116上會感應出負電荷，另一方面*相對於底表面 區域116、介電層106的上表面區域118則感應出正電荷， 類似地，配置於極子108B上之介電層1〇6的底表面區域12〇 上會感應出正電荷，而負電荷則產生於介電層1 〇 6之相對 頂表面區域122。 介電層106之頂表面區域Π8與122的正負電荷依次會 沿著晶圓102之底表面區域124與126感應出電荷，在介電 層106與晶圓102之間所感應出的電位會產生一靜電力，此 靜電力即讓晶圓1 0 2被靜電夾具夾住，在晶圓1 〇 2被夾住的 情況下、氣體電漿源被釋放進一待電漿處理晶圓上之—電 漿區域128，這些諸如姓刻、氣相沈積、賤鑛等之電漿處 理將進行到蝕刻或沈積達到所要的程度為止。Clamping and Declamping a Semiconductor Wafer in a Wafer Processing System ", these previous case disclosures are here for reference. The cross-sectional view shown in FIG. 1 is an example of an electrostatic clamp [exempUry electrostatic chuck (ESC)] of a central wafer. The electrostatic clamp 100 includes a dielectric layer 106 and Π0, and an electrode 108. The electrode 108 is disposed between the dielectric layers 106 and 110 and is set as a pair of poles 108A and 108B in a bipolar esc configuration with an insulating layer therebetween. The poles 108A and 108B are connected to a positive and negative terminal of a power source 12 respectively. Therefore, the pole 108A is positively biased and the pole 108 is negatively biased. The bias potentials of the poles 108A and 108B will be at the dielectric layer 1 Charges are induced in the surface areas adjacent to 〇6 and 110. For example, negative charges are induced in the bottom surface area 116 of the dielectric layer 106 on the pole 108A. On the other hand, relative to the bottom surface area 116 and the dielectric layer 106, A positive charge is induced in the upper surface region 118. Similarly, a positive charge is induced in the bottom surface region 120 of the dielectric layer 106 disposed on the pole 108B, and a negative charge is generated in the dielectric layer 10. 6 的 VERSE TOP SURFACE AREA 122. The positive and negative charges of the top surface regions Π8 and 122 of the dielectric layer 106 will sequentially induce charges along the bottom surface regions 124 and 126 of the wafer 102, and the potential induced between the dielectric layer 106 and the wafer 102 will generate An electrostatic force causes the wafer 102 to be clamped by the electrostatic fixture. When the wafer 102 is clamped, the gas plasma source is released into a wafer to be plasma-treated. In the slurry region 128, these plasma treatments such as engraving, vapor deposition, base ore, etc. will be performed until the etching or deposition reaches a desired level.
第6頁 46 49 五、發明說明（3) 不幸的是’這種電藥製程基本上無法獲得均勻性的結 果，這是因為晶圓1 02上之電漿分佈不均的關係，例如， 圖2 A所示之範例圖2 0 0係用以顯示一晶圓上的賤鑛率，曲 線202顯示出從晶圓102中心204起、沿徑向距離的電浆滅 鍍率’即如圖200所示，濺鍍率隨著徑向距離愈靠近晶圓 中心2 0 4而增加’相反地’晶圓1 〇 2徑向距離中心2 〇 4愈遠 則濺鍍率隨之遞減，而在接近晶圓邊緣時則會急遽增加。 晶圓上電漿分佈的不均句性基本上對製程所造成的結 果係指整個晶圓表面的不均勻，圖2B顯示一傳統電梁處理 室中’一蝕刻後晶圓的蝕刻表面2 1 0，為求解釋的方便， 假定在蝕刻製程之前的晶圓表面係一均勻的表面2丨2，在 蚀刻製程之後’晶圓表面2 1 0會從晶圓中心2丨4開始、雙向 形成一向上傾斜面，尤其，因為電漿在中心區域^較高的 濃度’触刻後表面210將顯示晶圓之中心214較其鄰接區域 有較大的钱刻程度^ 〇〇 、 圖顯示習-知之電漿處理室中，晶圓表面在進行電漿 沈積後沿徑向距離的沈積均勻度，虛線22〇係指接 前的晶圓表面，在電漿沈積製程之後’其所得的晶圓 22 2曰會從晶圓中心224的頂點向下傾斜’通常製裎結果所广 的晶圓表面222即反映出上述圖2A中所顯示的電漿八佑于 特由電漿蝕刻與沈積製程所造成之晶圓刀表二 均勻特生田然不是我們想要的結果，因為它 晶圓的良率與產能。 百丨年低母片 增進電漿均句度的傳統方式是使用具有額外孔隙戈開Page 6 46 49 V. Description of the invention (3) Unfortunately, 'this kind of electro-pharmaceutical process basically cannot obtain uniform results, which is because of the uneven plasma distribution on the wafer 102, for example, the graph The example shown in Fig. 2A is used to display the low ore rate on a wafer. Curve 202 shows the plasma removal rate in a radial distance from the center 204 of the wafer 102, as shown in Fig. 200. As shown, the sputtering rate increases as the radial distance is closer to the wafer center 204. Conversely, as the radial distance of the wafer 1 02 is further away from the center 204, the sputtering rate decreases. The wafer edge increases sharply. The unevenness of the plasma distribution on the wafer basically results in a process that refers to the unevenness of the entire wafer surface. Fig. 2B shows an etched surface of a wafer after etching in a conventional electric beam processing chamber 2 1 0, for the convenience of explanation, it is assumed that the wafer surface before the etching process is a uniform surface 2 丨 2, after the etching process, the 'wafer surface 2 1 0 will start from the wafer center 2 丨 4 and form a bidirectional Inclined surface, in particular, because the plasma in the center area ^ higher concentration 'after the surface is etched 210 will show that the center 214 of the wafer has a greater degree of money engraving than its adjacent area ^ 〇〇, the picture shows Xi-Knowing In the plasma processing chamber, the deposition uniformity of the wafer surface along the radial distance after the plasma deposition. The dotted line 22 refers to the wafer surface before the connection, and the resulting wafer 22 after the plasma deposition process 2 2 It will be inclined downward from the vertex of the wafer center 224. The wafer surface 222, which is generally produced, reflects the plasma plasma Yauyou shown in FIG. 2A, which is caused by the plasma etching and deposition process. Wafer Knife Table 2 Uniform Special Birth Ran Is Not Us The desired result because of its wafer yield and capacity. One hundred years of low mother film. The traditional way to increase the uniformity of the plasma is to use extra pores.
第7頁 孔係沿晶圓側邊配置，且其設 體電漿源’所以’晶圓中心以 漿’故能補償這些區域較低的 以增進均勻度至某一程度，但 間的距離十分敏感，例如，若 釋放的氣體電漿源可能即無法 不均勻分佈，另一方面，若晶 聚源可能沒有足夠的時間被均 射頭四周採用一限制磁環或靜 此環所疋義的區域之中，在電 之β又a十可增加晶圓週邊徑向區 ’導因於限制磁環之磁場，限 表面造成著名的尖端效應。 勻分佈的電漿還會造成非所欲 是因為暴露於較低電漿濃度下 較多的時間來形成所欲的蝕刻 沉積製程在一非均勻分佈的電 完成。 要的是能增進對晶圓電漿處理 增加處理的時間與對晶圓離氣 感。 4 6 4 9 ------------- 五、發明說明¢4) 孔的噴射頭，這些孔隙或開 計可讓喷射頭釋放更多的氣 外的區域可以產生更多的電 電漿分佈，這種方法固然可 其結果卻對喷射碩與晶圓之 噴射頭離晶圓太遠，則由其 均勻分佈，故亦導致電漿的 圓離喷射頭過近，則氣體電 勻地分佈。 另一個解決方法是在喷 電爽具、以便將電漿限制在 楽被限制住的情況下，此環 域上的電漿濃度，不幸的是 制礤環常常會在晶圓的周邊 再者’在晶圓上產生均 之電漿密度降低的效應，這 之晶圓相較於高濃度者需要 或沉積結果’所以，蝕刻或 漿環境中需要較長的時間來 針對以上所述，吾人需 時的均勻度，且實質上不致 體電漿源之距離不致過於敏 發明概|The holes on page 7 are arranged along the side of the wafer, and they have a bulk plasma source, so the 'wafer center is plasma', so these regions can be compensated for lower uniformity to a certain degree, but the distance between them is very Sensitive, for example, if the released gas plasma source may not be distributed unevenly, on the other hand, if the crystal polymerization source may not have enough time, a restricted magnetic ring or a region defined by this ring may be used around the homogeneous head. Among them, β and a can increase the radial area around the wafer. This is due to the limitation of the magnetic field of the magnetic ring, which limits the surface to cause the famous tip effect. A uniformly distributed plasma can also cause unwanted results because it is exposed to lower plasma concentrations for more time to form the desired etch. The deposition process is performed with a non-uniformly distributed plasma. What is needed is to improve the plasma processing of wafers, increase the processing time, and degassing the wafer. 4 6 4 9 ------------- V. Description of the invention ¢ 4) Nozzles with holes, these holes or openings can make the nozzle release more air out of the area can produce more The plasma distribution of this plasma method, although the result is that the spray head and the spray head of the wafer are too far away from the wafer, it is evenly distributed by it, so the circle of the plasma is too close to the spray head. Evenly distributed. Another solution is to spray the electricity in order to limit the plasma to the circumstance that the thorium is confined. The plasma concentration in this ring region, unfortunately, the thorium ring will often be on the periphery of the wafer. Produces a uniform plasma density reduction effect on the wafer. This wafer requires or deposits more results than those with a higher concentration. Therefore, it takes longer to etch or paste the environment to address the above. We need time. Uniformity, and the distance between the plasma source is not too sensitive.
第8頁 五、發明制⑸ "1 — 大體上說，本發明所提供之方法與設備可補償電裝處 理室中不均勻的電漿處理、故能滿足上述之需求，值得注 意的是，本犛明可以多種方式實現，包括一製程、設備'、 系統、裝置、方法、或一電腦可讀之媒介，以下即描述幾 種本發明所創新之較佳實施例。 本發明之第一較佳實施例提供一方法，可補償電毀處 理室中不均勻的電漿處理，電漿處理室具有一靜電夹具以 夾住一晶圓，靜電夾具則具有複數層，藉由暴露於電紫之 中’將一第一晶圓（亦即範例晶圓）處理於第一電漿處理室 中之一靜電夾具上’並將其暴露於電漿之中，然後，此處 理過的第一晶圓之非均勻特性即可判定，根據此非均勻特 性即可設置靜電夾具的一或多層以實質上補償此非均句特 性’然後在此設好的靜電夾具上處理一第二晶圓以產生實 質上均勻的製程結果。 本發明之第二較佳實施例提供一方法，可補償電漿處 理室中不均勻的電漿處理，電漿處理室具有一靜電夾以夾 住一晶圓，而一電極則配置於此晶圓之上，藉由暴露於電 黎之中’將一第一晶圓處理於第一電漿處理室中之一靜電 夾具上，由此處理過之第一晶圓可判定非均勻特性，然 後’將電極配置成複數個電性分隔的部位，以便實質上補 償此處理過之第一晶圓的非均勻特性，使用此設好的電 極’即可在電漿處理室中處理一第二晶圓以便崖生實質上 均勻的製程結果。 本發明之另一較佳實施例提供一靜電夾異，以便在電Page 8 V. Invention System " 1 — Generally speaking, the method and equipment provided by the present invention can compensate for the uneven plasma treatment in the electrical equipment processing room, so it can meet the above requirements. It is worth noting that The present invention can be implemented in various ways, including a process, a device, a system, an apparatus, a method, or a computer-readable medium. Several preferred embodiments of the present invention are described below. The first preferred embodiment of the present invention provides a method that can compensate for non-uniform plasma processing in an electric destruction processing chamber. The plasma processing chamber has an electrostatic clamp to clamp a wafer, and the electrostatic clamp has multiple layers. The first wafer (that is, the example wafer) was processed on an electrostatic fixture in the first plasma processing chamber by being exposed to the electric violet, and then exposed to the plasma. The non-uniform characteristics of the first wafer can be judged. Based on the non-uniform characteristics, one or more layers of the electrostatic fixture can be set to substantially compensate for the non-uniform sentence characteristics. Then, a first Two wafers to produce a substantially uniform process result. A second preferred embodiment of the present invention provides a method that can compensate for uneven plasma processing in a plasma processing chamber. The plasma processing chamber has an electrostatic clamp to clamp a wafer, and an electrode is disposed on the crystal. Above the circle, a first wafer is processed on an electrostatic fixture in the first plasma processing chamber by being exposed to the electricity, so that the processed first wafer can determine non-uniform characteristics, and then 'Configure the electrode into a plurality of electrically separated parts so as to substantially compensate for the non-uniformity of the processed first wafer, and use this set electrode to process a second crystal in the plasma processing chamber. Round so that the cliff produces a substantially uniform process result. Another preferred embodiment of the present invention provides an electrostatic clamp
第9頁 4 6 4 9 7 五、發明說明（6) 裝處理室中進行電漿處理時能夾住晶圓，靜電夾具包含一 第一層與一電極，此電極配置在傳送叮電源給電漿之第一 層下’第一層具有一可變的第一阻抗，將此第一阻抗加以 調適以便在晶圓上產生一可變的DC偏壓，如此在電漿處理 室中的電漿（即離子）即以實質上均勻的方式被吸引至晶 圓。Page 9 4 6 4 9 7 V. Description of the invention (6) The wafer can be clamped during plasma processing in the processing chamber. The electrostatic fixture includes a first layer and an electrode. This electrode is configured to transmit the power to the plasma. Under the first layer, the first layer has a variable first impedance, and this first impedance is adjusted so as to generate a variable DC bias voltage on the wafer, so that the plasma in the plasma processing chamber ( That is, ions) are attracted to the wafer in a substantially uniform manner.
本發明之優點在於提供一有效率的方法與設備，能補 償電漿處理室中不均勻的電漿處理，藉由改變各層之厚度 與加入其它阻抗元件，可產生晶圓上的變化之DC偏壓及/ 或變化之電漿密度分佈’變化之DC偏壓的功能係在整個晶 圓表面上以實質上均勻的方式吸引電漿（即離子），藉以補 償晶圓上不均勻的電漿處理，本發明的這些優點參看以下 關於較佳實施例的詳細描述與各附圊即可清楚暸然D 鮫佳實施例之詳細說明 本發明係電衆處理室中之不均勻晶圓處理的補償方法 與設備’以下即係其詳細之說明，然而，對熟悉此相關習 知技術者而言’部分内容不需詳細說明亦得以實施，在其 它實施例中’一些習知的製程步驟亦不詳細說明以免造成 與本發明的混淆。 圖3顯示一範例之電漿處理系統3〇〇，根據本發明之較 值實施例’此系統用以處理一半導體晶圓3 〇 2，此電漿處 毽系統3 0 0包含一電漿處理室3〇4、一ESC電源3〇6、與一對 奸電源與310 ’電漿處理室304包含一噴射頭312與一雙The advantage of the present invention is to provide an efficient method and equipment that can compensate for non-uniform plasma processing in the plasma processing chamber. By changing the thickness of each layer and adding other impedance components, it can generate a changed DC bias on the wafer. The function of changing and / or changing the plasma density distribution 'varying DC bias' is to attract plasma (ie ions) in a substantially uniform manner across the entire wafer surface, thereby compensating for uneven plasma treatment on the wafer. These advantages of the present invention can be clearly understood by referring to the following detailed description of the preferred embodiment and the appended descriptions. D Detailed description of the preferred embodiment The present invention is a method for compensating for uneven wafer processing in an electric processing room "Equipment and equipment" are detailed descriptions below. However, for those skilled in the related art, some of the content can be implemented without detailed description. In other embodiments, some of the conventional process steps are not described in detail. So as not to cause confusion with the present invention. FIG. 3 shows an example plasma processing system 300. According to a comparative embodiment of the present invention, this system is used to process a semiconductor wafer 300, and the plasma processing system 300 includes a plasma processing. Room 304, an ESC power supply 306, and a pair of power supply and 310 'plasma processing room 304 contains a spray head 312 and a pair
第10頁 464975 五、發明說明（7)^ ~ ' " -- ，靜電夾具316，喷射頭312係用來在電漿處理室3〇4中將 風*體源引進晶圓302上之電漿區域3 22，配置晶圓302並將 其灸住於靜電夾具316之上以進行電漿處理，一頂端電極 314了配置於噴射頭312上以作為一單獨的組合單元，噴射 頭312及/或電極314可以適當的材料製成，諸如鋁、矽、 石墨等。 靜電夾具3 16包含一介電層318，此介電層318以雙極 之配置形成於一金屬層320之上，介電層318可以具有適當 阻抗特性之一或多種介電材料製成，金屬層3 2 〇包含一對 極子320A與320B，並被調適成具有靜電極（electr〇static pole)(亦即電極）之功能’極子320A與320B分別被連接至 ESC電源3 0 6之正負端子，在此方法中，極子32 〇 A之功能係 作為一負極、而極子3 2 0 B則當作一正極操作，一氣體（例 如氦氣）透過一或多個輸送管324穿過靜電夾具316而被加 壓供給至晶圓3 0 2 ’此氣體即如一冷卻媒介以控制電裂處 理過程中的晶圓溫度，靜電夾具31 6之上、下、或層318與 3 2 0之間尚可配置其它層’雖然此處僅說明了雙極靜電夾 具，但無疑地，電漿處理系統亦可使用其它具有任何數目 與型態之各層的單極與雙極靜電夾。 RF電源308提供RF電源至配置於喷射頭312上之電極 31 4，以激發電漿處理室3 0 4中之電漿，類似地，RF電源 310則用以提供RF電源至靜電夾具316，RF電源308與310可 以是任何適合產生RF電源之RF電源裝置，諸如線圈、平板 等。Page 10 464975 V. Description of the invention (7) ^ ~ '"-, electrostatic fixture 316, spray head 312 are used to introduce the wind source into the electricity on wafer 302 in the plasma processing chamber 300 In the slurry area 3 22, the wafer 302 is configured and moxibusted on the electrostatic fixture 316 for plasma processing. A top electrode 314 is arranged on the spray head 312 as a separate combination unit. The spray head 312 and / Or the electrode 314 may be made of a suitable material, such as aluminum, silicon, graphite, or the like. The electrostatic fixture 3 16 includes a dielectric layer 318. The dielectric layer 318 is formed on a metal layer 320 in a bipolar configuration. The dielectric layer 318 may be made of one or more dielectric materials with appropriate impedance characteristics. The metal Layer 3 2 0 contains a pair of poles 320A and 320B, and is adapted to function as a static pole (ie, an electrode). The poles 320A and 320B are connected to the positive and negative terminals of the ESC power source 3 06, respectively. In this method, the function of the pole 32 0A is as a negative electrode, while the pole 3 2 0 B is operated as a positive electrode. A gas (such as helium) passes through the electrostatic clamp 316 through one or more conveying pipes 324 and It is pressurized and supplied to the wafer 3 0 2 'This gas is like a cooling medium to control the wafer temperature during the electro-cracking process. The electrostatic fixture 3 16 can be arranged above, below, or between layers 318 and 3 2 0 Other layers' Although only bipolar electrostatic clamps are described here, undoubtedly, the plasma processing system can also use other unipolar and bipolar electrostatic clamps having any number and type of layers. The RF power source 308 provides RF power to the electrode 31 4 disposed on the spray head 312 to excite the plasma in the plasma processing chamber 300. Similarly, the RF power source 310 is used to provide RF power to the electrostatic fixture 316, RF. The power sources 308 and 310 may be any RF power supply device suitable for generating RF power, such as coils, flat plates, and the like.
第11頁 4 6 五、發明說明（8) ~ 一- 、田與ESC電源30 8、31 0、與3 0 6隨喷射頭3 1 2被啟動 =釋放氣體源至電漿區域時，電漿即由氣體源產生於晶圓 t上之電漿區域322中’所產生之電漿包含正負電荷，正 電荷通常是離子，同時，電極層32〇之負與正極子32〇八與 320B會在極子與對應之晶圓疊置區域感應靜電力，如此晶 圓302即藉由電槳處理中之靜電力而被爽至靜電夾具316。 根據本發明之一較佳實施例，ΕΚ電源3〇6係一可傳送 幾千伏（如± 20 00 volt)之高電力裝置，ESC電源3〇6傳送 D C電壓、而r ρ電源3 〇 8與3 1 0則傳送射頻電源，此處雖對 電讓處理系統3 0 0詳加描述以增進對本發明優點之瞭解， 然而’本發明並不受限於任何特定的晶圓處理設備或系 統’並可調適成任何適當的晶圓處理系統，且其調適亦不 堂限於沉積、氧化、蝕刻{包括乾蝕刻、電漿蝕刻、離子 反應银刻（R I E)、磁場加強式離子反應姓刻[magne t丨ca 1】y enhanced reactive ion etching(MERlE)]、電子環繞共 振式[electron cyclotron resonance(ECR)]}等等之用。 即如圖3所示’不論是單極與雙極esc之配置，在操作 電漿處理系統3 0 0之過程中，通常會在晶圓3 〇 2上施以一 dc 偏壓，此種DC偏壓之施行係熟知的習知技術，本發明在一 靜電夹具或頂端電極中設置有一層或多層之幾何構造及/ 或材料’以便在晶圓上產生變化之DC偏壓，並在晶圓整個 表面上以實質上均勻的方式吸引電漿（即離子），此在下面 會詳加解釋。 圖4 A係一較佳實施例之方法的流程圖，此方法提供電Page 11 4 6 V. Description of the invention (8) ~ 1-, Tian and ESC power supply 30 8, 31 0, and 3 0 6 are activated with the spray head 3 1 2 = When the gas source is released to the plasma area, the plasma That is, the plasma generated by the gas source in the plasma region 322 on the wafer t contains positive and negative charges, and the positive charges are usually ions. At the same time, the negative of the electrode layer 32 and the positive electrode 3208 and 320B will be in the The pole and the corresponding wafer stacking area induce electrostatic force, so that the wafer 302 is cooled to the electrostatic clamp 316 by the electrostatic force in the electric paddle process. According to a preferred embodiment of the present invention, the EK power source 306 is a high power device capable of transmitting several thousand volts (such as ± 20 00 volt), the ESC power source 306 transmits DC voltage, and the r ρ power source 308 And 3 10 transmit radio frequency power. Although the electrical processing system 300 is described in detail here to improve the understanding of the advantages of the present invention, the present invention is not limited to any specific wafer processing equipment or system. And can be adapted into any appropriate wafer processing system, and its adaptation is not limited to deposition, oxidation, etching {including dry etching, plasma etching, ion reactive silver etching (RIE), magnetic field enhanced ion reaction engraving [magne t 丨 ca 1] y enhanced reactive ion etching (MERlE)], electron cyclotron resonance (ECR)]} and so on. That is, as shown in FIG. 3 'Regardless of the unipolar and bipolar esc configuration, in the process of operating the plasma processing system 300, a dc bias is usually applied to the wafer 300. This type of DC The application of bias is a well-known and conventional technique. The present invention provides one or more layers of geometric structure and / or material in an electrostatic fixture or top electrode to generate a varying DC bias on the wafer, and Plasma (ie ions) is attracted in a substantially uniform manner over the entire surface, which is explained in more detail below. Figure 4 A is a flowchart of a method of a preferred embodiment, this method provides electricity
第12頁 五、發明說明（9) ： '一~—~~' -- 中均句的電讓處理’一開始是步驟402，然後是 傳統靜曾，其中在電漿處理室中，一範例晶圓被處理於一 搜電夹具上’此範例晶圓之處理係指任何適當的電漿 -:諸如蝕刻 '沉積、與濺鍍等。 外旦^圓處理凡後即可對其量測，且最好是在電漿處理室 性里二勒以便在步驟40 6產生處理後晶圓之製程均勻.度特 草@ <裎均勻度特性最好係量測晶圓複數個徑向位置上 量制曰例如蝕刻、沉積等）處理後的均句度，例如，可以 者作：阁：同位置上諸如蝕刻或沉積製程之深&，並將其 於曰S'/: ί位置的函I，如此，製程均勻度特性即關聯 以產生讧二、隹度上的製程均勻度，此均勻度特性可繪成圖 以產生一校準曲線或製程表格等等。 層，步驟408中，可在靜電夾具中配置-或多 補償範例晶圓之不均句；層根據此製程均句特性來 電爽具或電極配置了 _ i客t 較佳實施例則為靜 幾何結構使其阻抗實質2層之幾何結構（即外型）’調適 圓的不均句處理特性。補償具備某製程均勾特性之晶 根據本發明之另一較伟音访加 頂層電極之-或多層心；實施你1，亦可設置靜電炎具或 複數個部位且以複數種材；形：如擇；^將其分隔成 料，將各部位之材料性質钢滴：母-部位-種材 -較佳實施例[配合理之特性，然而在另 ※饤構造與材料之配置亦可提供足5. Description of the invention on page 12 (9): '一 ~ — ~~'-The electric letting process of Zhongjun sentence starts with step 402 and then the traditional Jingzeng. Among them, in the plasma processing room, an example The wafer is processed on a search fixture. The processing of this example wafer refers to any suitable plasma-such as etching, deposition, and sputtering. The outer circle can be measured after the round treatment, and it is best to put it in the plasma processing chamber so that the process of generating the processed wafer in step 40 6 is uniform. 特特 草 @ < 裎 Uniformity The characteristic is best to measure the average degree of the wafer after measuring at a plurality of radial positions (e.g., etching, deposition, etc.). For example, it can be: Ge: the depth of the same position such as the etching or deposition process And the function I at the position S '/: ί. In this way, the process uniformity characteristics are correlated to produce the process uniformity on the second and second degrees. This uniformity characteristic can be plotted to generate a calibration curve. Or process forms, etc. In step 408, an uneven sentence of the example wafer can be configured in the electrostatic fixture, or the uneven sentence of the example wafer can be compensated; the layer is called according to the characteristics of this process, or the electrode is configured. The preferred embodiment is static geometry The structure makes its impedance substantially 2 layers of geometric structure (ie appearance) 'adapts to the round uneven sentence processing characteristics. Compensate for crystals with uniform hooking characteristics in a certain process. According to the present invention, another relatively high-frequency sound plus top-layer electrodes or multi-layered cores; if you implement 1, you can also set static inflammation tools or multiple parts and multiple materials; shape: If you choose; ^ Separate it into materials, and separate the material properties of each part into steel: mother-part-seed material-preferred embodiment [with reasonable characteristics, but the structure and material configuration can also provide sufficient
第13頁 464975 五、發明說明（ίο) 以補償晶圓非均勻處理特性之阻抗。 .然後’將配置好的靜電夾具及/或電極安置在電漿處 理室中以處理新的晶圓，在步驟中，一新晶圓被處理 於新配置之電漿處理室中，因為靜電夾具及/或電極被設 成在晶圓表面上以實質上均勻的方式來吸引電榮（即離 子）’故所得之晶圓會有實質上均勻的處理特性，處理之 後，此方法即終止於步驟4 1 2，雖然這裡只描述單一晶 圓’但複數個晶圓可被同時處理於電漿處理室中，例如， 可處理複數個範例晶圓而讓每片晶圓皆有製程均勻之特 性’此外’亦可在處理室中使用配置之靜電夾具或頂端電 極以處理新的複數個晶圓。 圖4B係根據本發明之較佳實施例中配置幾何結構及/ 或材料之更為詳細的方法步驟4 〇 8，此方法起始於步驟 452，然後是步驟454，其中選擇ESC或頂端電極之一或多Page 13 464975 V. Description of the Invention (ίο) To compensate the impedance of the wafer non-uniform processing characteristics. Then 'place the configured electrostatic fixture and / or electrode in the plasma processing chamber to process the new wafer. In the step, a new wafer is processed in the newly configured plasma processing chamber because the electrostatic fixture And / or the electrodes are set to attract electricity (ie, ions) on the wafer surface in a substantially uniform manner, so the resulting wafer will have substantially uniform processing characteristics. After processing, this method ends in steps 4 1 2. Although only a single wafer is described here, 'a plurality of wafers can be processed in a plasma processing chamber at the same time. For example, a plurality of example wafers can be processed so that each wafer has a uniform process characteristic.' In addition, it is also possible to use a configured electrostatic jig or top electrode in a processing chamber to process a new plurality of wafers. FIG. 4B is a more detailed method of configuring the geometry and / or material according to a preferred embodiment of the present invention. Step 4 08, this method starts at step 452, and then step 454, where the ESC or the top electrode is selected One or more
層以進行配置，如上所述，ESC可包含複數個介電層、電 極層等等。 S 然後是步驟456 ’判定所選各層之阻抗以提供此偏壓 至晶圓，如此實質上可補償所量得之非均勻性，此 性即係製程均句特性之所示，而此判定阻抗以提供不同之 DC偏麼係熟知的習知技術，例如，由庫侖定律、 等所描述之著名方程式即可判定此阻抗， 一置所選各層之幾何構造及/或材料定之 阻抗’然後此方法即終止於步驟4 6 〇。 圖5A至5E係複數個靜電夾具之橫剖面冑，每個靜電夾 464975 五、發明說明（ll) 具皆包含諸如電極層、介電層等之複數層，然而，這些靜 電夾具只係一範例，它們可有任何數目之各層與材料，並 以任何適當的次序提供晶圓上之均勻電漿處理，此外，根 據均勻度之特性，頂層電極亦可以類似靜電夾具配置其幾 何構造及/或材料的方法來進行配置。 圖5A係一範例靜電夾具5〇2之橫剖面圖，根據本發明 之較佳實施例’此靜電夾具502之幾何構造被調適成可補 償非均勻製程之特性’靜電夾具5 0 2包含一配置於電極層 5 06上之介電層504，介電層504之頂部係平坦者，其底部 表面508則係彎曲者以便橫跨介電層5〇4而具有變化之厚 度’在一較佳實施例中，介電層5 〇 4被分隔成複數個部位 504A 、 504B 、 504C 、 504D 、 504E 、 504F 、 504G 、 504H 、與 5 0 4 I (以下則稱作” 5 0 4 A至5 0 4 I ”），雖然此處所述係分隔之 層，但本發明之介電層亦可不分隔成多個部位。 504A至5 0 4 1之每一分隔部位彼此電性隔離於其鄰接部 位’部位5 0 4 A至5 0 4 I則最好以相同的材料形成，但亦可使 用不同的材料，電極層506則補充介電層504之底表面 508 ° 在此配置中，介電層504中電性隔離部位504A至5041 之變化厚度被調適成具有橫跨介電層504之變化阻抗，介 電層504之變動厚度依序用來產生變化之DC偏壓，其藉由 在整個晶圓表面上以實質上均勻的方式吸引電漿（即離 子），因而可補償晶圓上之非均勻性電漿處理，例如，靜 電夾具502可用來補償以上圖2A、2B、與2C所示之晶圓製Layers, as described above, the ESC may include a plurality of dielectric layers, electrode layers, and the like. S is followed by step 456 'determining the impedance of the selected layers to provide this bias to the wafer, so that the measured non-uniformity can be substantially compensated, which is the characteristic of the mean sentence characteristic of the process, and this judges the impedance In order to provide different DC biases, which are well-known conventional techniques, for example, the famous equations described by Coulomb's law, etc. can determine this impedance, and then set the geometric structure and / or material-defined impedance of each selected layer, and then this method That is, it ends in step 46. Figures 5A to 5E are cross sections 复 of a plurality of electrostatic clamps, each of which is 464975. V. Description of the Invention (ll) The tool includes multiple layers such as electrode layers, dielectric layers, etc. However, these electrostatic clamps are only an example. , They can have any number of layers and materials, and provide uniform plasma processing on the wafer in any appropriate order. In addition, according to the characteristics of uniformity, the top electrode can also be similar to an electrostatic fixture to configure its geometry and / or material Method to configure. FIG. 5A is a cross-sectional view of an example electrostatic fixture 502. According to a preferred embodiment of the present invention, 'the geometry of this electrostatic fixture 502 is adapted to compensate for the characteristics of non-uniform process. The dielectric layer 504 on the electrode layer 506, the top of the dielectric layer 504 is flat, and the bottom surface 508 is curved so as to have a varying thickness across the dielectric layer 504. In the example, the dielectric layer 504 is divided into a plurality of locations 504A, 504B, 504C, 504D, 504E, 504F, 504G, 504H, and 5 0 4 I (hereinafter referred to as "5 0 4 A to 5 0 4 I ”), although described herein as a separated layer, the dielectric layer of the present invention may not be separated into a plurality of locations. Each of the separated parts of 504A to 5 0 4 1 is electrically isolated from each other's adjacent parts. The parts 5 0 4 A to 5 0 4 I are preferably formed of the same material, but different materials may also be used. The electrode layer 506 The bottom surface of the dielectric layer 504 is supplemented by 508 °. In this configuration, the thickness of the electrically isolated portions 504A to 5041 in the dielectric layer 504 is adjusted to have a varying impedance across the dielectric layer 504. The varying thickness is sequentially used to generate a varying DC bias, which attracts plasma (ie, ions) in a substantially uniform manner across the entire wafer surface, thus compensating for non-uniform plasma treatment on the wafer. For example, the electrostatic fixture 502 can be used to compensate the wafers shown in FIGS. 2A, 2B, and 2C above.
464975 五、發明說明（12) 程不均勻性’雖然圖中所示介電層5 〇4之低層表面5〇8係彎 曲者’其亦可具有其它形狀或幾何構造，的確，介電層 504可以任何一種形狀形成，在符合均勻特性之情況下， 並不受限於直線、非線性、彎曲、或階梯狀，此外，靜電 夾具502之上、下、或層508與506之間還可包含一些其它 的層。 —^ 圖5B係一範例靜電夾具512之橫剖面圖’根據本發明 之另一較佳實施例，此靜電夾具5丨2藉由階梯狀之幾何結 構可補償非均句性之製程特性，靜電夾具5〗2包含一配置 於一電極層516上之介電層514，介電層514被分隔成複數 個部位514A、514B、514C、514D、514E、514F、514G、 514H、與5141，（以下則稱作"514A至5141”），每個部位皆 與隔鄰部位電性隔離’介電層514之底表面us因為部位 514A至5141之厚度變化而呈階梯狀，介電層514之下的電 極層5 1 6則形成一互補的階梯層。 層514之厚度從中心部位514E至部位514B至514H逐步 減少，邊緣部位514A與5141實質上較部位514B與514H為 厚’以便補償晶圓邊緣部位上較大的電漿濃度，階梯狀之 厚度變化則在靜電夾具5 1 2上提供可變之阻抗，所以可具 有一可變之DC偏壓’以便在晶圓之整個表面上以均勻的方 式吸引電聚（即離子）’介電層5丨4與電極層5 1 6之階梯形狀 可藉由將均勻特性（例如，均勻曲線、表格等）劃分成複數 個區域而實現’然後，再為每一分隔區域判定介電層之厚 度。464975 V. Description of the invention (12) Process non-uniformity 'Although the lower layer surface of the dielectric layer 504 shown in the figure is a 508 bender', it may also have other shapes or geometric structures. Indeed, the dielectric layer 504 It can be formed in any shape, and it is not limited to being linear, non-linear, curved, or stepped in the case of conforming to uniform characteristics. In addition, the electrostatic fixture 502 may include a layer above, below, or between layers 508 and 506. Some other layers. — ^ FIG. 5B is a cross-sectional view of an example electrostatic clamp 512. According to another preferred embodiment of the present invention, the electrostatic clamp 5 丨 2 can compensate the process characteristics of nonuniformity by using a stepped geometric structure. The fixture 5 includes a dielectric layer 514 disposed on an electrode layer 516. The dielectric layer 514 is divided into a plurality of portions 514A, 514B, 514C, 514D, 514E, 514F, 514G, 514H, and 5141, (hereinafter It is called " 514A to 5141 "), each part is electrically isolated from the adjacent part. The bottom surface us of the dielectric layer 514 is stepped because of the thickness change of the parts 514A to 5141, and the dielectric layer 514 is below The electrode layer 5 1 6 forms a complementary step layer. The thickness of the layer 514 gradually decreases from the central portion 514E to the portions 514B to 514H, and the edge portions 514A and 5141 are substantially thicker than the portions 514B and 514H 'in order to compensate for the wafer edge Larger plasma concentration on the part, the step-like thickness variation provides a variable impedance on the electrostatic fixture 5 1 2, so it can have a variable DC bias' in order to uniformly spread the entire surface of the wafer Way to attract electropolymerization (ie ions) The stepped shape of the layers 5 丨 4 and the electrode layer 5 1 6 can be achieved by dividing uniform characteristics (for example, uniform curves, tables, etc.) into a plurality of regions. Then, the thickness of the dielectric layer is determined for each separated region .
第16頁 464975 五、發明說明（13) ' 類似地，圖5C係範例靜電夾具522之橫剖面圖，根據 本發明之另一較佳實施例，此靜電夹具522具有階梯狀之 各層，在靜電爽具522中，一電極層526被夾在一上介電層 524與一下介電層528之間，上介電層524被分隔成電性隔 離部位524A、524B、524C、524D、524E、524F、524G、 524H、與5241，層524之底表面wo則形成為階梯狀，電極 層526則補充上介電層524之階梯狀表面53()。 靜電夾具與/或上電極之各層不論其幾何構造是否有 所變動皆可被設以不同的材料，例如，圖5D係一靜電夾具 542之橫剖面圖，根據本發明之一較佳實施例，此靜電夾 具在一層中具有複數種材料，靜電夾具542包含一配置 2立電極層546上之介電層544，介電層544被分隔成複數 部位544A、544B、544C、5 44D、5 44E、5 44F、5 44G、與 5/41(以下則稱作” 544A至544 1 " )，544a至544 ί之每一部位 查根據所需阻抗而調適其材料，例如，均勻特性（例如， 句勾曲線’均勻表格等）可被劃分成複數個區域，然後， 介電層可被分隔成複數個部位5 4 4 Α至5 4 4 I，這些部位則對 ^於均勾特性之各分隔區域，並判定544A至544 1每一分隔 1位補償非均勻性之所需阻抗，然後544A至544 1之每—分 2。卩位即以可提供必要阻抗之材料製成，此時，介電層 4之·整體即可提供可變之阻抗以在晶圓的整個表面上產 °變之DC偏壓，如此即可以均勻之方式吸引電漿（即離 子）至晶圓。 在本發明之一較佳實施例中，部位544A至544 1之每一Page 16 464975 V. Description of the invention (13) Similarly, FIG. 5C is a cross-sectional view of an exemplary electrostatic clamp 522. According to another preferred embodiment of the present invention, the electrostatic clamp 522 has step-like layers. In the cooler 522, an electrode layer 526 is sandwiched between an upper dielectric layer 524 and a lower dielectric layer 528, and the upper dielectric layer 524 is separated into electrical isolation portions 524A, 524B, 524C, 524D, 524E, 524F , 524G, 524H, and 5241, the bottom surface wo of the layer 524 is formed in a step shape, and the electrode layer 526 supplements the stepped surface 53 () of the upper dielectric layer 524. The layers of the electrostatic clamp and / or the upper electrode can be provided with different materials regardless of whether the geometry is changed. For example, FIG. 5D is a cross-sectional view of an electrostatic clamp 542. According to a preferred embodiment of the present invention, This electrostatic clamp has a plurality of materials in one layer. The electrostatic clamp 542 includes a dielectric layer 544 disposed on the 2 vertical electrode layer 546. The dielectric layer 544 is divided into a plurality of locations 544A, 544B, 544C, 5 44D, 5 44E, 5 44F, 5 44G, and 5/41 (hereinafter referred to as "544A to 544 1 "), 544a to 544 ί, and adjust the material according to the required impedance, for example, uniform characteristics (for example, the sentence Hook curve 'uniform form, etc.) can be divided into a plurality of regions, and then the dielectric layer can be divided into a plurality of parts 5 4 4 Α to 5 4 4 I, and these parts correspond to each of the divided regions of the uniform hook characteristic. And determine the impedance required to compensate for non-uniformity by 1 bit separated by 544A to 544 1, and then every 2 minutes of 544A to 544 1. The niches are made of materials that can provide the necessary impedance. At this time, the dielectric Layer 4 as a whole can provide a variable impedance ° DC bias on the surface becomes the yield, i.e., such a manner of uniform plasma can be attracted (i.e., ions) to the wafer. In one preferred embodiment of the present invention, portions 544A to 5441 of each
第17頁 464975 五、發明說明（14) 部位皆以不同之材料組成以提供特定之阻抗，在另一較佳 實施例中，部位5 4 4 A至5 4 4 I之材料係以相對於中心部位 5 4 4 E之對稱方式組成，例如，部位5 4 4 B與5 4 4 ί以相同的材 料组成，而部位544Β與544Η則以另一材料組成，部位544C 與544G可有相同的材料，部位544D與544F則又係另一種材 料’這種配置極適於補償對稱曲線之非均勻性，其例子則 已顯示於先前之圖2Β與圖2C。 根據本發明之另一較佳實施例，圖5Ε係一範例靜電夾 具552之橫剖面圖，靜電夾具5 52包含一電極層556，此電 極層556配置在一上介電層554與一下介電層558之間，電 極層556被分隔成複數個電性隔離部位556Α、556Β、 556C、556D、與556Ε，此每一部位係以適當之材料形成以 提供所需阻抗，如此複數個部位556A、556B、556C、 556D、與556E即可提供可變之阻抗以在晶圓之整個表面上 形成可變之DC偏壓。 除了幾何結構與/或材料之配置外，尚可提供額外之 阻抗元件以產生所需之阻抗’例如，在一靜電夾具中之電 極層可連接至這些阻抗元件，圖5 ρ係一範例靜電夾具5 6 2 之橫刮面圖，根據本發明之一較佳實施例，此靜電^具 562具有複數個阻抗元件56〇Α、56〇β、56〇c、56⑽、與 5 6 0E，類似於圖5£所示之靜電夾具，靜電夾具562包^一 電極層5 6 6 ’此電極層5 6 6 g己置在—對〆電層5"愈⑽之 間，然而，在靜電夾具562中，阻抗元件56〇a、56〇b、 560C、5 60D、與560E則分別連接至電性分隔部位5 66A、Page 17 464975 V. Description of the invention (14) The parts are made of different materials to provide a specific impedance. In another preferred embodiment, the materials of parts 5 4 4 A to 5 4 4 I are relative to the center. Parts 5 4 4 E are composed symmetrically. For example, parts 5 4 4 B and 5 4 4 ί are composed of the same material, and parts 544B and 544Η are composed of another material. Parts 544C and 544G may have the same material. The parts 544D and 544F are another material. This configuration is very suitable for compensating for the non-uniformity of the symmetrical curve, and examples thereof have been shown in FIG. 2B and FIG. 2C. According to another preferred embodiment of the present invention, FIG. 5E is a cross-sectional view of an example electrostatic clamp 552. The electrostatic clamp 5 52 includes an electrode layer 556, which is disposed on a dielectric layer 554 and a lower dielectric layer. Between the layers 558, the electrode layer 556 is divided into a plurality of electrically isolated portions 556A, 556B, 556C, 556D, and 556E, each of which is formed of a suitable material to provide a desired impedance, such that the plurality of portions 556A, 556B, 556C, 556D, and 556E can provide variable impedance to form a variable DC bias voltage on the entire surface of the wafer. In addition to the geometry and / or material configuration, additional impedance elements can be provided to produce the required impedance. For example, an electrode layer in an electrostatic fixture can be connected to these impedance elements. Figure 5 is an example electrostatic fixture A cross-sectional view of 5 6 2. According to a preferred embodiment of the present invention, the electrostatic device 562 has a plurality of impedance elements 56〇A, 56〇β, 56〇c, 56⑽, and 5 6 0E, similar to The electrostatic clamp shown in FIG. 5 £, the electrostatic clamp 562 includes an electrode layer 5 6 6 'This electrode layer 5 6 6 g has been placed in between-the anti-electrical layer 5 " more, but in the electrostatic clamp 562 The impedance elements 56〇a, 56〇b, 560C, 5 60D, and 560E are respectively connected to the electrically separated parts 5 66A,
第18頁 464975 五 '發明說明（15) --- 56 6B、56 6C、566D、與5 6 6E ’以便提供橫跨電極層566而 變化之阻抗，阻抗元件可為任何功能足以作為阻抗元件之 元件，諸如電阻、電容器、電感器、或其任意組合，在圖 5E與5F中，要注意的是，分別位在電極層556與566上之介 電層554與564亦可被分隔。 頂層電極亦可以類似於靜電夾具之方法來設置其幾何 構造與/或材料’或者根據均勻特性而提供額外的阻抗元 件，舉例來說，圖5G係一範例電極5 72之橫剖面圖，根據 本發明之一較佳實施例，此電極5 7 2具有複數個阻抗元件 576A、576B、556C、556D、與556E，電極572 包含一電極 層574與複數個阻抗元件576A、576B、576C、576D、與 576 E’且其連接至一 RF電源，電極層574被分隔成複數個 電性隔離之部位574A、574B、5 74C、574D、與574E，其可 以相同或複數種不同的材料形成，部位574A、574B、 574C、574D、與574E則分別電性連接於阻抗元件576A、 576B、576C、576D、與576E，其被設成可在電極層574中 提供可變之阻抗以便在晶圓之表面上產生可變之DC偏壓， 或者是產生可變之電漿密度分佈，要注意的是，根據本發 明所描述之較佳實施例，靜電夾具之配置亦可類似地適用 於改變DC偏壓與/或電漿密度分佈。 本發明之另一較佳實施例係提供一ESC環，其被調適 成可補償晶圓周邊區域之非均勻性，例如，圖6A係一靜電 夾具600之立體圖，根據本發明之一較佳實施例，此靜電 夾具600包含一設置在RF電極604上之ESC環602，ESC環602Page 18 464975 Five 'Invention Note (15) --- 56 6B, 56 6C, 566D, and 5 6 6E' in order to provide impedance varying across the electrode layer 566, the impedance element can be any function sufficient to function as an impedance element. Components, such as resistors, capacitors, inductors, or any combination thereof. In FIGS. 5E and 5F, it should be noted that the dielectric layers 554 and 564 on the electrode layers 556 and 566, respectively, can also be separated. The top electrode can also be set in a similar way to an electrostatic fixture to set its geometry and / or materials' or provide additional impedance elements based on uniform characteristics. For example, Figure 5G is a cross-sectional view of an example electrode 5 72. According to this In a preferred embodiment of the invention, the electrode 5 7 2 has a plurality of impedance elements 576A, 576B, 556C, 556D, and 556E, and the electrode 572 includes an electrode layer 574 and a plurality of impedance elements 576A, 576B, 576C, 576D, and 576 E 'and it is connected to an RF power source, the electrode layer 574 is separated into a plurality of electrically isolated parts 574A, 574B, 5 74C, 574D, and 574E, which can be formed of the same or a plurality of different materials, the parts 574A, 574B, 574C, 574D, and 574E are electrically connected to the impedance elements 576A, 576B, 576C, 576D, and 576E, respectively, which are configured to provide a variable impedance in the electrode layer 574 to generate on the surface of the wafer Variable DC bias, or a variable plasma density distribution, it should be noted that, according to the preferred embodiment described in the present invention, the configuration of the electrostatic fixture can be similarly adapted to change the DC bias and / Or plasma density distribution. Another preferred embodiment of the present invention is to provide an ESC ring, which is adapted to compensate the non-uniformity of the peripheral area of the wafer. For example, FIG. 6A is a perspective view of an electrostatic clamp 600, which is a preferred implementation according to the present invention. For example, the electrostatic fixture 600 includes an ESC ring 602 and an ESC ring 602 disposed on the RF electrode 604.
464975 五、發明說明（16) 在靜電夾具600周圍形成一環，並包含一電極層6〇8，此電 極層.6 08設置在一上介電層60 6.與一下介電層之間，一 介電層則視需要設在ESC環602中之RF電極604上，因為ESC 環6 02較習知靜電電極中者為小，故其製造之複雜度與費 用可顯著地降低。 圖6 B係靜電夾具6 0 0之橫剖面圖，根據本發明之較佳 實施例，圖中顯示層6 0 6之材料與幾何構造，靜電夾具6 〇 〇 將一晶圓616夾在適當之處以進行處理，介電層6〇6包含二 部位61 4與61 8，此二部位以不同的材料形成，此外，二部 位614與618具有不同的幾何構造’這些具有不同材料之部 位與幾何構造可更均勻地吸引電漿（即離子）至晶圓6 1 6之 表面。 為降低費用與複雜度’可將ESC環6 0 2進一步簡化，圖 7係一範例靜電夾具70 0之立體圖，根據本發明之一較佳實 施例’此靜電夾具700包含複數個部位、704、706、與 708、而非ESC環602 ’部位702、704、706、與708之各層 可被獨立或對稱地設成具有所需之阻抗，如此一來，靜電 夹具700即可省下製造上大量的費用與複雜度。 電漿處理室中補償不均勻晶 述係用於方便說明本發明之 義地限制於該較佳實施例。 皆屬本發明申請專利之範 以上即係本發明中，在一 圓處理之方法與設備，其中所 較佳實施例，而非將本發明狹 凡依本發明所做之任何變更， 圍。464975 V. Description of the invention (16) A ring is formed around the electrostatic clamp 600 and includes an electrode layer 608, which is disposed on an upper dielectric layer 60 6. and a lower dielectric layer. The dielectric layer is provided on the RF electrode 604 in the ESC ring 602 as needed. Because the ESC ring 602 is smaller than the conventional electrostatic electrode, the complexity and cost of its manufacture can be significantly reduced. Figure 6 is a cross-sectional view of a B series electrostatic clamp 600. According to a preferred embodiment of the present invention, the material and geometry of the layer 606 are shown. The electrostatic clamp 600 clamps a wafer 616 in place. The dielectric layer 606 includes two parts 61 4 and 61 8 which are formed of different materials. In addition, the two parts 614 and 618 have different geometries. These parts and geometries with different materials The plasma (ie, ions) can be attracted to the surface of the wafer 6 1 more uniformly. In order to reduce costs and complexity, the ESC ring 602 can be further simplified. FIG. 7 is a perspective view of an example electrostatic clamp 700. According to a preferred embodiment of the present invention, the electrostatic clamp 700 includes a plurality of parts, 704, The layers of 706, 708, but not ESC ring 602 'parts 702, 704, 706, and 708 can be independently or symmetrically set to have the required impedance. In this way, the electrostatic clamp 700 can save a lot of manufacturing Cost and complexity. The description of compensating for non-uniform crystals in the plasma processing chamber is used to facilitate the explanation of the invention and is limited to the preferred embodiment. All belong to the scope of patent application of the present invention. The above are the preferred embodiments of the method and equipment for round processing in the present invention, rather than narrowing the present invention to any changes made in accordance with the present invention.
464975 圖式簡單說明 $細ΐ 3本發明之目的、優點和特色由以下較佳實施例之 圖羊細說日？並參考圖式當可更加明白，其令： a彳/。彳面.圖係用以顯示一夾住晶圓之靜電夾具範例； =用以說明晶圓上減鍍率之範例； 面；’、用以說明傳統電黎處理室中’晶圓银到後的轴刻表 距齙ί 〃員不傳統電漿處理室中’於實施電漿沉積後沿徑向 距離上之晶圓沉積均勻度· 係:以說明本發明之較佳實，處理半 之電漿處理系統的範例； 於電漿處理室中提 圖4A係根據本發明之較佳實施例中，r 供一均句之電漿處理的方法； 月b 設置幾何構造及/或 其調適後之幾何構造 其藉由階梯式的幾何 圖4B係根據本發明之較佳實施例 材料的方法； 圖5 A之橫剖面圖係一靜電夾具範例 可補償不均勻的製程特性； 圖5B之横剖面圖係一靜電夾具範例 構造可補償不均句的製程特性； 剖面圖係根據本發巧之較佳實施例中，一且有階 梯式各層之靜電夾具範例； Τ 八有％ 根據本發明之較佳實施例中，-靜電爽 异板0又成在—層中具有複數種材料； 圖5Ε係一靜電夾具範例的橫剖面圖； 圖5F之橫剖面圖係根據本發明之較佳實施例中，一具有複464975 Schematic description $ 细 ΐ 3 The purpose, advantages and characteristics of the present invention are illustrated by the following preferred embodiments. And you can understand it more clearly with reference to the drawing, which makes: a 彳 /. The figure is used to show an example of an electrostatic fixture holding a wafer; = an example to explain the plating reduction rate on the wafer; a surface; ', used to illustrate the' wafer silver in a traditional electrical processing room ' In the traditional plasma processing room, the axial engraving distance is not uniform. Wafer deposition uniformity in the radial distance after plasma deposition is implemented. An example of a plasma processing system; Figure 4A is a plasma processing method according to a preferred embodiment of the present invention, where plasma is provided in a plasma processing chamber; month b sets a geometric structure and / or adjusts it The geometry is constructed by a stepped geometry. Figure 4B is a method of materials according to a preferred embodiment of the present invention. Figure 5A is a cross-sectional view of an example of an electrostatic fixture that can compensate for uneven process characteristics. Figure 5B is a cross-sectional view. The example structure of an electrostatic fixture can compensate the process characteristics of the uneven sentence. The cross-sectional view is an example of an electrostatic fixture with stepped layers in the preferred embodiment of the present invention. T% is better according to the present invention. In the embodiment,-the electrostatic refreshing plate 0 becomes again- There are a plurality of materials in the layer; FIG. 5E is a cross-sectional view of an example of an electrostatic fixture; FIG. 5F is a cross-sectional view of a preferred embodiment according to the present invention.
第21頁 46 497 5 圖式簡單說明 數個阻抗元件之靜電夹具； 圖5 G之橫剖面圖係根據本發明之較佳實施例中，一具有複 數個阻抗元件之靜電夾具範例； 圖6A係一靜電夾具範例之透視圖，此靜電夾具包含設於 電極上之ESC環； ~ a ' 圖6B係根據本發明之較佳實施例中，一 HI ias - Μ- M- it ήχ a ^'電爽 /、的橫剖面 圖，其顯不此靜電夾具中修改過材料與幾何 圖7係一靜電爽具範例之透視圖’此靜電夾且 ， 部位而非單一ESC環。 、^ 3複數個 符號說明 靜電夾具100 晶圓1 0 2 介電層106 電極108 介電層110 極子108A 極子108B 電源11 2 底表面區域11 6 頂表面區域118 底表面區域1 20 頂表面區域122 底表面區域1 24Page 21 46 497 5 The diagram briefly illustrates the electrostatic fixture of several impedance elements; the cross-sectional view of FIG. 5G is an example of an electrostatic fixture with a plurality of impedance elements according to a preferred embodiment of the present invention; A perspective view of an example of an electrostatic fixture that includes an ESC ring provided on an electrode; ~ a 'FIG. 6B shows a HI ias-Μ- M-it price x a ^' The cross section of Shuang /, which shows the modified materials and geometry in this electrostatic fixture. Figure 7 is a perspective view of an example of an electrostatic fixture. 'This electrostatic clip has, instead of a single ESC ring. ^ 3 A plurality of symbols indicate electrostatic fixture 100 wafer 1 0 2 dielectric layer 106 electrode 108 dielectric layer 110 pole 108A pole 108B power supply 11 2 bottom surface area 11 6 top surface area 118 bottom surface area 1 20 top surface area 122 Bottom surface area 1 24
4 6 4 9 7 圖式簡單說明 底表面區域126 電漿區域128 曲線2 0 2 晶圓中心204 晶圓表面2 1 0 晶圓表面2 1 2 晶圓中心2 1 4 虛線2 2 0 晶圓表面2 2 2 晶圓中心224 電漿處理系統3 0 0 晶圓302 電漿處理室304 ESC電源306 RF電源308 RF電源31 0 喷射頭312 電極314 靜電夾具316 層318 層320 極子3 2 0A 極子320B 電漿區域3224 6 4 9 7 Schematic description of bottom surface area 126 Plasma area 128 Curve 2 0 2 Wafer center 204 Wafer surface 2 1 0 Wafer surface 2 1 2 Wafer center 2 1 4 Dashed line 2 2 0 Wafer surface 2 2 2 Wafer Center 224 Plasma Processing System 3 0 0 Wafer 302 Plasma Processing Room 304 ESC Power 306 RF Power 308 RF Power 31 0 Nozzle 312 Electrode 314 Static Fixture 316 Layer 318 Layer 320 Pole 3 2 0A Pole 320B Plasma area 322
第23頁 464975 圖式簡單說明 輪送管324 步驟 40 2, 404，406，40 8，410，412，452，454，456, 458， 460 靜電夾具502 介電層504 部位 504A，504B，504C，504D，504E, 504F，504G， 504H, 5041 電極層5 0 6 底表面5 0 8 靜電夾具51 2 介電層514 部位 514A, 514B，514C，514D，514E，514F, 514G, 514H, 5141 電極層5 1 6 底表面5 1 8 靜電夾具522 介電層524 電性隔離部位 524A, 524B, 524C，524D，524E, 524F， 524G, 524H, 5241 電極層5 2 6 介電層528 底表面5 3 0 靜電夾具542 介電層544Page 23 464975 Schematic description of carousel tube 324 Step 40 2, 404, 406, 40 8, 410, 412, 452, 454, 456, 458, 460 Electrostatic clamp 502 Dielectric layer 504 part 504A, 504B, 504C, 504D, 504E, 504F, 504G, 504H, 5041 Electrode layer 5 0 6 Bottom surface 5 0 8 Electrostatic clamp 51 2 Dielectric layer 514 part 514A, 514B, 514C, 514D, 514E, 514F, 514G, 514H, 5141 Electrode layer 5 1 6 Bottom surface 5 1 8 Electrostatic clamp 522 Dielectric layer 524 Electrically isolated portion 524A, 524B, 524C, 524D, 524E, 524F, 524G, 524H, 5241 Electrode layer 5 2 6 Dielectric layer 528 Bottom surface 5 3 0 Electrostatic Fixture 542 Dielectric layer 544
第24頁 圖式簡單說明 部位 544A，544B，544C，544D，544E, 544F，544G， 544H, 5441 電極層5 4 6 靜電夾具552 介電層5 5 4 電極層5 5 6Page 24 Brief Description of Drawings Parts 544A, 544B, 544C, 544D, 544E, 544F, 544G, 544H, 5441 Electrode layer 5 4 6 Electrostatic clamp 552 Dielectric layer 5 5 4 Electrode layer 5 5 6
部位 556A，556B，556C，556D, 556E 介電層558Location 556A, 556B, 556C, 556D, 556E Dielectric layer 558
阻抗元件 560A，560B, 560C, 560D，5 6 0E 靜電夾具562 介電層564 電極層5 6 6Impedance element 560A, 560B, 560C, 560D, 5 6 0E Electrostatic fixture 562 Dielectric layer 564 Electrode layer 5 6 6
電性分隔部位566A, 566B，566C， 5 6 6D，5 6 6E 介電層568 電極572 電極層5 7 4 部位 574A，574B，574C，574D，574E 阻抗元件 576A，576B，576C，576D, 576E 靜電夾具600 ESC 環602 RF電極602 上介電層606 電極層608 下介電層61 0 第25頁 46 497 圖式簡單說明 部位6 1 4 晶圓6 1 6 部位6 18 靜電夾具700 部位 702, 704，7 0 6, 7 0 8Electrically separated parts 566A, 566B, 566C, 5 6 6D, 5 6 6E Dielectric layer 568 Electrode 572 Electrode layer 5 7 4 parts 574A, 574B, 574C, 574D, 574E Impedance element 576A, 576B, 576C, 576D, 576E Static electricity Fixture 600 ESC ring 602 RF electrode 602 Upper dielectric layer 606 Electrode layer 608 Lower dielectric layer 61 0 Page 25 46 497 Schematic description of part 6 1 4 Wafer 6 1 6 Part 6 18 Electrostatic holder 700 Part 702, 704 , 7 0 6, 7 0 8
IHII1I 第26頁IHII1I Page 26
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-
1999
- 1999-03-31 US US09/282,644 patent/US6188564B1/en not_active Expired - Lifetime
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- 2000-02-25 WO PCT/US2000/005036 patent/WO2000058994A1/en active IP Right Grant
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- 2000-02-25 EP EP00912029A patent/EP1166323B1/en not_active Expired - Lifetime
- 2000-02-25 DE DE60035971T patent/DE60035971T2/en not_active Expired - Lifetime
- 2000-02-25 AU AU33829/00A patent/AU3382900A/en not_active Abandoned
- 2000-02-25 KR KR1020017012362A patent/KR100640241B1/en active IP Right Grant
- 2000-03-23 TW TW089105405A patent/TW464975B/en not_active IP Right Cessation
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| US6188564B1 (en) | 2001-02-13 |
| KR100640241B1 (en) | 2006-10-31 |
| JP2002540616A (en) | 2002-11-26 |
| DE60035971D1 (en) | 2007-09-27 |
| WO2000058994A1 (en) | 2000-10-05 |
| EP1166323B1 (en) | 2007-08-15 |
| EP1166323A1 (en) | 2002-01-02 |
| KR20010110708A (en) | 2001-12-13 |
| AU3382900A (en) | 2000-10-16 |
| DE60035971T2 (en) | 2008-05-08 |
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