TW464777B - Methods of forming liquid crystal display devices - Google Patents

Abstract

Methods of forming liquid crystal display devices includes the steps of forming a gate line and a gate electrode on a face of a transparent substrate and then forming an insulating layer (e.g. Si3N4) on the gate line and gate electrode. Formation of a thin film transistor (TFT) preferably comprising the gate electrode, amorphous silicon active regions and source and drain electrodes, is then completed on the insulating layer. To facilitate reduction of the number of masking steps needs to fabricated the display devices, a gate pad layer (e.g. indium tin oxide) is formed directly on the gate line by opening a window in the insulating layer and thereby eliminating an intermediates step (and associated masking step) of patterning the conductive material used to form the drain and source electrode on the gate line before forming the gate pad layer. To inhibit formation of hillocks (and potential electrical ""short"" caused thereby) and minimize signal delays associated with the gate lines and electrode, the gate lines and gate electrodes are preferably formed to comprise a plurality of layers including an aluminum or related alloy first layer, a tantalum or related alloy second layer on the first layer and an anodic oxide containing tantalum (e.g. TaO5) top layer.

Description

464777 V. Description of the invention (1) Description of the invention: The present invention relates to a display element and a manufacturing method thereof, and particularly to a liquid crystal display element and a manufacturing method thereof. The main method of manufacturing LCD devices and panels today is based on amorphous silicon (a-Si) TFT technology. Using these technologies, it is possible to produce cost-effective high-quality image displays in low-temperature processes. A conventional LCD element includes a transparent substrate, an array of TFTs arranged in an array, a plurality of pixel electrodes, and a plurality of gate lines and data lines arranged in an orthogonal arrangement. A color filter (Fi Iter) plate, a liquid crystal material between the substrate and the color filter plate. Amorphous silicon TFT technology requires the use of a separate peripheral integrated circuit to drive the array to align the gates and sources of TFTs. Therefore, a large number of pads are needed to connect the gate and data lines. The gate line coupling (couple) is connected to the "pole" and the data line is coupled to the peripheral driving circuit. One method of making an amorphous silicon TFT LCD display panel is to make a metal layer on a transparent substrate for the gate and gate lines. However, in large displays, the signal delay on the gate line will significantly reduce the uniformity of the image on the display panel. Therefore, the line resistance (Line resistance

The Rc time constant generated by Resistance and Line Capacitance must be minimized. In order to suppress defects caused by short circuits in the panel, it is necessary to prevent abnormal precipitation (H i 1 1 0 c k) from being formed. One method to prevent abnormal precipitation is to perform anodization on the gate and the gate lines to form a '0xide Surface Layer', for example, to form an aluminum oxide (A10) layer on the gate or gate lines. . Anodizing technology and production display

B. 6 47 V. Description of the invention (2) The method of the panel of the device is described in more detail in US Patent No. 5,397,719 filed by Kim et al., Entitled, "Method for Manufacturing" a Display Panel), which is generally assigned to the trustee of this application, and the part disclosed herein is incorporated into the reference material. Referring to FIGS. 1A-1G and 2A-2G, the conventional method for making LCD brake pads is described. Another method for making a TFT LCD display panel using conventional technology is described below. ^ 1A and 2A show that a gate metal layer is deposited on a substrate 20, a gate mask (not shown) is used, and the gate metal layer is etched (Etch) to make a gate line, the first Figures of a gate pad 1 2 1 and a gate electrode 1 2 2 "Figure 1 β and 2 B show, using a second photomask (not shown), an anodized layer 14 on the gate 1 22 and part of The first brake pad 1 2 1 is formed. Next, FIGS. C and 2C show that an insulating layer 20 is formed on the first gate pad 121 and the gate electrode 122. In addition, using a third photomask (not shown), an amorphous silicon layer 16 and an N amorphous silicon layer 8 are sequentially formed and patterned on the insulating layer opposite to the gate 丨 2 2 . The picture is called ... shown *, using the fourth mask (not shown): carved into the edge layer 20 to extend part of the first gate pad 121. Refer to Figures ^ and ", using the fifth mask ( (Not shown), a metal layer is deposited and a pattern is formed. After this etching step is completed, a data pad (data pad), a data line and a source electrode 222, a part of the data line, a drain electrode 223 and The second gate pad 221. Using the source 2 22 and the drain 22 3 as a photomask, the amorphous silicon layer 18 is etched, and a part of the amorphous silicon layer 16 under it is exposed (Expose). Figure ιρ And 2F show that a sixth layer of mask (not shown) is used to deposit and etch a passivation layer (P.aSS1vatlon Layer) 24 to expose part of the second gate pad 221 and

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4 6 47 7 7 5 'Explanation of invention (3) part and pole 223. FIGS. 1G and 2G show that after depositing a transparent conductive material, a seventh photomask (not shown) is used to form a pattern of the transparent conductive material, thereby fabricating a third gate pad 261 (in the second gate pad 221). Top) and the transparent pixel electrode 262 to complete the manufacture of the TFT element. Unfortunately, the above-mentioned method for manufacturing an LCD element requires a large number of photomasks and related engraving steps, and the formation of abnormal precipitation is also a common phenomenon and reduces the performance of the element. The main purpose of the present invention is to provide a special LCI element manufacturing method. A contact window is opened on the insulating layer, and a gate pad layer is directly formed on the gate line, so as to avoid the photomask step of the metal conductive layer. The gate wire and the gate are anodized to suppress abnormal precipitation 'and reduce the gate wire and gate signal delay. Brief description of the drawings: Figures 1 ~ 1G are the conventional methods for making LCD brake pads. 2A-2G are conventional methods for manufacturing a TFT LCD element. 3A-3F illustrate a method for manufacturing an LCD brake pad according to the first embodiment of the present invention. 4A-4F illustrate a method for manufacturing a TFT [CD element according to a first embodiment of the present invention. 5A-5F illustrate a method for manufacturing an LCD brake pad according to a second embodiment of the present invention. 6A-6F illustrate a method for fabricating a TFT LCD device according to a second embodiment of the present invention. 7A-7F illustrate a method for manufacturing an LCI) leisure pad according to a third embodiment of the present invention. 8A-8F illustrate a method for fabricating a TFT LCD device according to a third embodiment of the present invention. 9A-5F illustrate a method for manufacturing an LCD brake pad according to a fourth embodiment of the present invention. 10A-10F illustrate a method for fabricating a TFT LCD device according to a fourth embodiment of the present invention.

464777 V. Description of the invention (4) Drawing number illustrates first gate 102 insulation layer 106 passivation layer 114 substrate 200 insulation layer 204 insulation layer 304 purification layer 312 insulation layer 404 anodized layer 403 passivation Zhan 412 first gate pad 1021 gate 1022 Second gate pad 1161 Second gate 210 1 Drain 2103 First gate pad 30 2 1 TFT gate 30 2 2 First gate second layer 4022 First gate pad first 4012 Source gate 4102 attached The figures show embodiments of the present invention, with reference to which they can be more completely

464777 V. Description of Invention (5) Describe the invention. However, the present invention can be implemented in different ways. It is not limited by the embodiments herein. More precisely, the provision of these reward examples makes this disclosure more comprehensive and complete, and can convey all aspects of this invention to those skilled in the art. In the figure, in order to express more clearly, 'the thickness of the wide area is exaggerated' and reference is made to similar proportions. Furthermore, the "first conductive type" and "second conductive type" refer to two opposite conductive plastic types, such as P-type and N-type. However, each of the embodiments described and shown herein also includes a derivative thereof. Embodiments The preferred embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIGS. 3A-3F and 4A-4F, a method for manufacturing an LCD opening pad and a TFT LCD according to the first embodiment of the present invention. The first photomask is used. A pattern (eg, etching) of a gate metal layer is formed on a surface of a transparent substrate 100 (such as glass) to make a first gate pad 102 and a gate electrode 1 2 2 of TTF. The gate metal layer contains a suitable metal (eg, aluminum, or aluminum alloy) that can be oxidized.

Al-Si, Al_Pd, Al_Ni, A1-Ge, A1 ~ W), Mo (hetero),

Ti (titanium), Ta (tantalum), Mo-Ta. The gate metal layer includes an aluminum alloy (e.g., aluminum 'alloy Al-Nd or aluminum-platinum alloy Al-pt). Etchant used to etch out the pattern of the metal layer containing aluminum gates includes CHCOOH / HNO / HPO / HO. Referring to FIGS. 3B and 4B, an anodized layer 104 is formed on a portion of the first gate pad 1021 and the gate electrode 1022 using a second photomask. The anodic oxide layer 104 is produced in a 3% tartaric acid solution having a pH of 7.0 to 0.5, with ammonia (NΗΟ Η) as an additive, and ethylene glycol as a diluent. During the anodizing process, the first gate pad 1021 and the gate

Page 10 464777

Five to invention description (6) 1 0 22 series as the anode, and stainless steel or platinum (pt) as the cathode, and the standard anode voltage (An〇dization Voltage} is 14 volts, the degree of electrical bifurcation is 0.5 to 5 5 m A / cm. Figures 3C and 4C show that an insulating layer 10 (eg, SiN) is attached to the substrate 100, the first gate 1021, the gate 1022, and the anodized layer 104. 囷 4 ( : It is shown that a third mask is used to sequentially fabricate an amorphous silicon layer 108 and an N amorphous silicon layer 110 on an insulating layer 丨 0 and form a shape to manufacture an active region of a TFT. Refer to Figures 3D-4D for the drawing. On the other side of the first gate pad that has not been oxidized, the pattern of the source / drain metal layer has not been formed, but a source / drain A metal layer (eg, Cr), and a fourth mask is used to form a pattern to make the source and drain i 1 22, data lines, and data pads. A portion of the N amorphous stone layer 110 is also formed. (Patterned source / non-polar metal layer) is engraved as a self-aligned mask. Figures 3E and 3E show 'deposit a passivation using a fifth mask Layer 11 4 and forming a pattern, thereby exposing a part of the drain electrode 11 2 2 and a part of the insulating layer 10 6 'This insulating layer is stretched relative to a part of the first gate pad which has not been oxidized. In this step, the exposed insulating layer 10 is etched, thereby exposing the first gate pad 1 021 of the portion covered by the anodized layer 104. Figures 3F and 4F show 'depositing an optically transparent layer on the purification layer A conductive layer, such as Indium Tin Oxide (IT0), and then etched the transparent conductive layer pattern with a sixth photomask to make a pixel electrode 1162 (the first gate 1021 is an ohmic contact) ) To complete the manufacturing of the component. According to the manufacturing procedure of the first embodiment, the second brake pad 1 161 and the first brake pad 1 021 are directly connected without the intermediate brake pad layer in the conventional technology.

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46 47 7 T V. Description of the invention (7) The edge layer 106 and the passivation layer 114 are etched in the same step to expose the first gate pad 1021 'while eliminating the light of FIGS. 1A-1G and 2A-2G in the conventional technology Hood process. Referring to FIGS. 5A-5F and 6A-6F, a method of fabricating a CD brake pad and a TFT LCD element according to a second embodiment of the present invention. 5A and 6A show that a first photomask is used to form a pattern of a free metal layer (eg, etching) on the surface of a transparent substrate 200 (eg, glass) to make a first gate pad 2 0 2 1 and a TF. T's brake. Pole 2022. 5B and 6B show that an insulating layer 204 is attached to the surface of the substrate 200 and the first gate pad 2021 and the gate electrode 2022. FIG. 6B shows that a second photomask is used to sequentially fabricate an amorphous dream layer 206 and an N amorphous silicon layer 208 on the insulating layer 204, and a pattern is formed to manufacture an active region of the TFT. 9 Referring to FIGS. 5C and 6C, a third photomask is used to etch a part of the insulating layer 204 on the first gate pad 2021 to expose the first gate pad 2021. Using a fourth photomask, a source / drain metal layer (eg, Cr) is fabricated on the amorphous silicon layer and the first gate pad 2021 is exposed, and a pattern is produced to make a second gate pad 2101 , Source and drain 21 03, data line and data pad. The partial N amorphous silicon layer 208 uses the pattern of the source / drain metal layer as a self-aligned mask for etching to expose the amorphous silicon layer 206. 5E and 6E, a fifth mask is used to deposit a passivation layer 212 and pattern it, thereby exposing a part of the drain electrode 11 2 2 and a part of the second gate pad 2101. 5F and 6F show that a transparent conductive layer, such as an I TO layer, is deposited on the purification layer 212, and then a pattern of the transparent conductive layer is made to make a pixel electrode 2 1 4 (as a drain electrode 2 1 0 3 Ohmic contact) and the third brake pad 21.41 (ohmic contact with the second brake pad 2 1 〇1), and finally use the sixth light

Page 12 464777 Five 'invention description (8) mask, etching the transparent conductive layer to complete the production of elements "Referring to Figs. 7A-7E and 8A-8E, a method of manufacturing an LCD gate pad and a TFT LCD element according to a third embodiment of the present invention . FIGS. 7A and 8A show a pattern (eg, etching) of a gate metal layer on the surface of a transparent substrate 300 (eg, glass) using a first photomask to make a first gate pad 3 0 21 and One TFT gate 3022. The gate metal layer includes a metal alloy, such as an aluminum alloy (Al-Nd) or an aluminum chain alloy (Al-Pt). 7B and 8B show an insulating layer 304. It is attached to the surface of the substrate 300 and the first gate pad 3021 and the gate electrode 3022. FIG. 8B shows that a second photomask is used to sequentially fabricate an amorphous silicon layer 3 06 and an N amorphous silicon layer 3 08 on the insulating layer 3 04, and fabricate a pattern thereof to manufacture a TFT. Active area. Figures 7C-8C show 'Make a source / deposited metal layer containing chromium metal (Cr) on an amorphous silicon layer' and use the third mask to make a pattern to make the source and electrode 3 1 $ 2, the data line and the data pad, and the pattern of the opposite part of the metal layer of the source / drain stretched on the first closed circuit is not yet formed. Part of the N amorphous silicon layer 308 is etched using a source / drain metal layer pattern as a self-aligned photomask. 7D and 8D show that a passivation layer 312 is deposited and patterned using a fourth photomask, thereby exposing portions of the drain electrode 31 02 and a portion of the insulating layer 304. The exposed insulating layer 304 is etched, thereby exposing a portion of the first gate pad. Fig. 7E and "show that a transparent conductive layer, such as a 1TO layer, is deposited on the t passivation layer, and then a pattern of the conductive layer is made to make-the pixel electrode 3142 (in ohmic contact with the drain electrode 3102) and the first Second gate pad 3141 (After making ohmic contact with the first gate pad 30 21, the fifth photomask is used to etch the conductive layer to complete the device manufacturing

464777 V. Description of Invention (9). Therefore, according to the manufacturing procedure of the third embodiment, the second gate pad 3 1 41 is directly connected to the first gate pad 3021, and the intermediate gate pad layer of the conventional technology is not required. In addition, the insulating layer 304 and the passivation layer 312 are in the same Etching is performed in the step to expose the first gate pad 3021 and reduce the number of mask steps of the display element. Referring to FIGS. 9A-9F and 10A-10F, a method of manufacturing an LCD gate pad and a TFT LCD element according to a fourth embodiment of the present invention is shown in FIGS. 9A and 10A. In order to prevent abnormal precipitation, on the surface of a transparent substrate 400 (eg, glass) A multi-layered first gate and a multi-layered gate 2022 of a TFT are manufactured. A first layer containing aluminum is formed on the substrate, and then a second layer containing tantalum (Ta) is formed on the first layer. The first mask is used to etch to make patterns of these layers to produce the first layer The first gate pad 'of the layer 4011 and the second layer 4021 and the gate electrode including the first layer 4012 and the second layer 4022. 9B and 10B show that an anodized layer 403 including a pentoxide button (TaO) is formed on the surface of the second layers 4021, 4022. 9C and 10C show that an insulating layer 40 is formed on the first gate pad and the gate electrode, and then an amorphous silicon layer 2 06 and 1 are sequentially formed on the position of the insulating layer 40 with respect to the gate electrode. The N amorphous stone layer 208 'is patterned using a second photomask. Figures 91) and 10]) show that a third photomask is used to attach a metal layer of a source / drain to an amorphous layer and etch to form a source and a drain of 40.2. In this step, a portion of the N amorphous silicon layer 408 that is stretched with respect to the gate is etched to expose the heterogeneous amorphous broken layer 406. Referring to FIGS. 9E and 10E, it is shown that a purification layer 4 1 2 is attached to an insulating layer 404 and a drain electrode and a source electrode 41 2. Then, a fourth photomask is used.

4 6 4 7 7 7 V. Description of the Invention (ίο) Etching to expose the drain electrode 41 0 2. In this step, the insulating layer 4 04 and the anodized layer 40 3 (for example, TaO) are etched to expose the second layer 4022 of the first gate pad. The progress of this etching step can also expose the first wide 4012 of the first gate pad. 9F and 10F display ^ such as the IT0 layer, and then make a pattern of the transparent conductive layer to make a pixel electrode 4142 ( Make ohmic contact with the drain electrode 4102) and second gate pad 4141 (ohmic contact with the first gate pad) 'Finally use the fifth photomask to etch the conductive layer to complete the fabrication of the element. According to the manufacturing procedure of the fourth embodiment, the first gate 4141 and the first gate are directly connected without the intermediate gate pad of the conventional technique. In addition, a photomask is not required for the anodizing step shown in FIG. 9B and FIG. The method of the fourth embodiment reduces the conventional technique shown in Figs. 1a_1g * 2a_2Gk: 丨 all two: mask step ° At the same time, according to the fourth embodiment of the present invention, the LCD element (and the gate pad) is separated. To make the abnormal layered closed electrode * the first layer containing the inscription or the inscription alloy and the second layer containing tantalum or the tantalum alloy on the first layer sum up the above, when we know this; we have not seen ... what publication … = Creative 'and the only ones described above' are only used to limit the scope of the present invention: the best embodiment & 'Don't-equivalent changes and modifications made within the scope of the patent application of the present invention .. $ Shall belong to the model garden covered by the invention patent

Claims (1)

I I 464777 VI. Application patent scope 1. A method for manufacturing a liquid crystal display element, comprising the following steps: (1) using a first photomask to fabricate a gate line and a gate electrode of a thin film transistor on a surface of a transparent substrate; (2) An insulator and a semiconductor layer are sequentially deposited on the gate line and the gate electrode; (3) the semiconductor layer is patterned using a second photomask to make an active area of the thin film transistor; (4) a third photomask is used Make the data line, source and drain; (5) deposit a passivation layer; (6) use a fourth photomask to pattern the insulating layer and the insulating layer; to make a first contact hole that exposes the drain and to make Make a second contact hole exposing the first part of the gate line; (7) Use a fifth photomask to make a pixel connected to the exciter via the first contact hole on the first part of the exposed gate line. An electrode, and a first conductive layer is formed on the exposed first part of the gate wire, and the first conductive layer is in ohmic contact with the second conductive hole to form a gate pad. 2. The method for manufacturing a liquid crystal display device according to item 1 of the scope of the patent application, wherein the so-called semiconductor layer includes an undoped amorphous silicon layer fabricated on the insulating layer, and a doped non-crystalline layer on the insulating layer. The crystalline silicon layer further includes: using a data line, a source electrode, and a drain electrode as an etching mask to etch a doped amorphous silicon layer. 3. A method for manufacturing a liquid crystal display device, comprising the following steps: (1) using a first photomask to fabricate a gate electrode and a gate line having first and second surface portions on a surface of a transparent substrate; (2) ) Use a second photomask relative to the substrate, on the second surface portion of the gate line and Page 16 464777 VI. Apply for a patent to apply an anodized layer on the gate electrode. (3) On the first surface portion of the gate line and the anodized layer, an edge layer and a half conductive layer in sequence; (4) using a third photomask to pattern the semiconductor layer on the insulating layer as the active area of a field effect transistor; 'manufacturing (5) using a fourth photomask to make a data line and a source and drain (6) Deposition the passivation layer; '(7) use a fifth photomask to pattern the passivation layer and the insulation layer to expose the first contact hole of the drain electrode, and make a second contact hole exposing a surface portion; The first (8) uses a sixth photomask to make a pixel electrode. The first electrode is connected to the drain electrode through the first contact hole, and the first conductive electrode is on the first surface portion of the pixel wire. The contact hole and its ohm ^ = make a brake pad, which is electrically connected to the brake wire. Because 4. A method for manufacturing a liquid crystal display element, (1) using a first photomask to fabricate a closed electrode of a gate line film electrical body on a surface of the substrate, the gate line and the closed electrode including a first layer and a second electrode. The film_transistor surface includes the first metal on the substrate surface, the second layer includes t = metal, and it is different from the first metal on the first layer; gold (2) oxidizes one surface of the second layer to make An anodized layer; (3) sequentially depositing an insulating layer on the anodized layer; and [dream] (4) using a second photomask to pattern the amorphous silicon layer; F silicon layer, (5) using a third light Mask on amorphous stone; μ system; and make a thin-film transistor drain and 464777 on the Bθ layer. 6. Patent application scope (6) Deposit a passivation layer on the source and drain; (7) Use the first The four photomasks pattern the passivation layer, insulation layer, and anodized layer to make a first contact hole and a second contact hole. The first contact hole will expose the electrode and the second contact hole will expose the gate line The first part; (8) using a fifth photomask to fabricate an optically transparent pixel electrode and a conductive layer on the drain electrode The conductive layer is located in the first portion of the gate line. 5. The method for manufacturing a liquid crystal display element according to item 4 of the scope of patent application, wherein in step (1), the first metal is aluminum, the second metal is tantalum, and the anodized layer includes tantalum pentafluoride. 6. The method for manufacturing a liquid crystal display device according to item 5 of the scope of patent application, wherein the amorphous silicon layer includes a first amorphous silicon layer and a second amorphous silicon layer on an insulating layer, and the second amorphous silicon layer It is on the first amorphous silicon layer and has higher conductivity than the first amorphous silicon layer. 7. A method for manufacturing a liquid crystal display device, comprising the following steps: (1) using a first photomask to fabricate a gate line and a gate electrode of a thin film transistor on a transparent substrate; (2) sequentially on the gate line and the gate electrode Depositing an insulating layer and a semiconductor layer; (3) using a second photomask to pattern the amorphous silicon layer to make an active region of a thin film transistor; (4) using a third photomask to pattern the insulating layer, To expose the first part of the gate line; (5) use a fourth photomask to make a first conductive layer that exposes the first part of the data line, the drain, the source, and the gate line; (6) deposit and purify Floor; Page 18 464777 6. Application scope (7) Use a fifth shutter to pattern the passivation layer to make a first contact hole and a second contact hole. The first contact hole will expose the drain electrode and the second contact. The hole will expose the first conductive layer; (8) A sixth photomask is used to make a pixel electrode and a second conductive layer. The pixel electrode is connected to the drain electrode through the first contact hole, and the second conductive layer is connected through The second contact hole is connected to the exposed first conductive layer. Page 19