A7 46 3 45 6 6692twf/006 五、發明說明（ 本發明是有關於一種消除徧移電壓的方法，且特別 是有關於一種運算放大器欲消除偏移電壓的方法及裝置。 運算放大器具有三個端點；兩個輸入端和一個輸出 端’事實上，此放大器需要DC電源才能工作，而大部份 放大器需要兩個DC電嫄才能工作。現在我們考慮一理想 運算放大器的特性，運算放大器的主要功能是用來感知出 現在兩輸入端電壓訊號間的差額，並將此量乘以增益A造 成一電壓出現在輸出端。 理想的運算放大器並不會汲取任何輸入電流，故兩 端點的訊號電流均爲零。換言之，輸入阻抗爲無窮大。以 上描述可以看出運算放大器只對差額訊號有反應，因此它 完全忽視兩輸入間共同訊號部分。也就是說，若兩輸入電 壓相同則輸出爲零。我們稱此特性爲共模拒斥，因此一理 想的運算放大器具有一無窮大的共模拒斥。再者，增益A 被稱爲差額增益，而在零頻率至無窮大頻率之間增益A保 持常數。也就是說，理想的運算放大器以相同增益放大任 何頻率，實際上，在製程漂移、元件匹配.....等因素下， 運算放大器的偏移電壓將不爲零。在數位類比轉換器中， 若運算放大器有偏壓，則會造成訊號的失真，而影響輸出。 或用在Sensor小訊號時，因訊號源本身之電壓就很小’更 不容許運算放大器有偏壓的存在，所以消除偏壓是很重要 的。 故在一般運算放大器電路欲消除偏移電壓’皆需二個運算 放大器、三個電容，四個開關來達成如第1圖所繪示一般 泰紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先聞讀背面之注意事項#,填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 A7 B7 463456 6692twf/006 五、發明說明（之） 放大器欲消除偏移電壓之方法。但因，會造成放大器在晶 片上佔據很大的空間，而且若晶片中需要數個低偏移電壓 的運算放大器時，將會增加量產的成本而喪失競爭的優 勢。 因此本發明是提供一種運算放大器消除偏移電壓的 方法及消除偏移電壓的運算放大器裝置；此裝置只需一個 運算放大器、一個電容、三個開關’就可以輕易解決這一 個問題。. ' _ 一種消除傾壓的運算放大器裝置’包括·桌一開關， 具有第一端及第二端；第二開關’具有第一端及第二端’ 該第二開關之第一端耦接到第—開關之第一端，且連接至 一輸入訊號；一'電容，具有第一端及第一端’該電谷之第 —端耦接到該第一開關之第二端，該電容之第二端耦接到 . .·----- 該第二開關之第二端；第三開關’具有第一端及第二端， 該第三開關之第一端耦接到該電容之第二端；以及一運算 放大器，具有一非反向輸入端、一反向輸入端以及一輸出 端，該反向輸入端耦接到該第三開關之第二端，該非反向 輸入端親接到該電容之第一端，該輸出端親接到該反向輸 入端。當自動歸零相位時，該第一開關及第三開關閉路而 第二開關開路，當放大相位時，該第一開關及第三開關開 路而第二開關閉路。其中些開關係傳輸閘。而該自動歸零 相位小於放大相位。 綜合以上敘述，這三個開關分別受兩組不同相位控 制訊號操作，這兩組控制訊號分別爲自動歸零相位和放大 意 事 項A7 46 3 45 6 6692twf / 006 V. Description of the invention (The present invention relates to a method for eliminating the shift voltage, and in particular to a method and a device for eliminating an offset voltage of an operational amplifier. An operational amplifier has three terminals Point; two inputs and one output 'In fact, this amplifier requires DC power to work, and most amplifiers require two DC power sources to work. Now we consider the characteristics of an ideal operational amplifier, the main The function is used to sense the difference between the voltage signals appearing at the two input ends, and multiply this amount by the gain A to cause a voltage to appear at the output end. The ideal operational amplifier does not draw any input current, so the signals at the two ends are The current is zero. In other words, the input impedance is infinite. The above description shows that the operational amplifier only responds to the difference signal, so it completely ignores the common signal part between the two inputs. That is, if the two input voltages are the same, the output is zero. We call this feature common-mode rejection, so an ideal op amp has an infinite Modal rejection. Furthermore, the gain A is called the differential gain, and the gain A remains constant between zero and infinity. That is, an ideal operational amplifier amplifies any frequency with the same gain. In fact, the process drifts , Component matching, etc., the offset voltage of the operational amplifier will not be zero. In digital analog converters, if the operational amplifier is biased, it will cause signal distortion and affect the output. Or use When the Sensor is a small signal, the voltage of the signal source itself is very small. 'It does not allow the bias of the operational amplifier, so it is very important to eliminate the bias. Therefore, in general op amp circuits, it is necessary to eliminate the offset voltage.' Two operational amplifiers, three capacitors, and four switches to achieve the general Thai paper size as shown in Figure 1. Applicable to China National Standard (CNS) A4 specifications (210 X 297). (Please read the precautions on the back first #, Fill in this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 463456 6692twf / 006 V. Description of the invention (of) The method for the amplifier to eliminate the offset voltage. It will cause the amplifier to occupy a large space on the chip, and if several operational amplifiers with low offset voltage are needed in the chip, the cost of mass production will be increased and the competitive advantage will be lost. Therefore, the present invention provides an operational amplifier to eliminate Method of offset voltage and operational amplifier device for eliminating offset voltage; this device only needs one operational amplifier, one capacitor, and three switches' to easily solve this problem. '_ An operational amplifier device for eliminating dump voltage' Including a table switch having a first end and a second end; a second switch 'having a first end and a second end', the first end of the second switch is coupled to the first end of the first switch, and is connected to An input signal; a capacitor having a first terminal and a first terminal; the first terminal of the valley is coupled to the second terminal of the first switch, and the second terminal of the capacitor is coupled to the ... --- the second end of the second switch; the third switch 'has a first end and a second end, the first end of the third switch is coupled to the second end of the capacitor; and an operational amplifier having a Non-inverting input, Inverting input terminal and an output terminal, the inverting input terminal is coupled to the second terminal of the third switch, the non-inverting input terminal is connected to the first terminal of the capacitor, and the output terminal is connected to the inverting terminal. Input. When the phase is automatically reset to zero, the first switch and the third switch are open and the second switch is open. When the phase is amplified, the first switch and the third switch are open and the second switch is open. Some of them open the transmission brakes. The auto-zero phase is smaller than the amplified phase. Based on the above description, these three switches are operated by two sets of different phase control signals. The two sets of control signals are the auto-zero phase and the amplification.
I裝 I 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^63456 * A7 6692twf/006 __B7_____ 五、發明說明（多） 相位，透過這兩個相位來控制輸入訊號路徑’然後將偏移 電壓儲存在電容上。在放大相位時，電容上所儲存的偏移 電壓和放大器的偏移電壓將因極性相反而相互抵消。由於 電容上的電荷在自動歸零時是參考至輸入訊號，而非接地 端，因此可以擁有較廣闊的動態操作範圍。此種運算放大 器，可以大幅提高面積的使用率和功率的效率，使得成本 降低，增加競爭力。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖繪示的是根據一般的運算放大器欲消除偏移電 壓之電路圖； 第2圖繪示的是根據本發明之一較佳實施例的電路 圖： 第3A、3B圖繪示的是根據第2圖另一模式較佳實施 例之等效電路圖；以及 > 標號說明 10 ' 12、14 ' 25、26、27、28 :相位控制開關 17、 23 ' 24 :儲存電容 18、 20、21 :運算放大器 較佳實施例 一般運算放大器消除偏移電壓，因會造成運算放大 器在晶片上會佔據很大的面積，將會增加量的成本而喪失 競爭的優勢’故本發明提出一種運算放大器消除偏移電壓 ____5 本紙張尺度適用中國國家標準（CNS)A4规格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 463456 6692twf/006 ___B7_ 五、發明說明（斗） 之方法。需一個運算放大器18、一個電容17、三個開關10、 12、14，請參照第2圖繪示的是根據本發明之一較佳實施 例的電路圖，第一開關10具有第一端及第二端；而第二 開關12也具有第一端及第二端，則第二開關12之第一端 耦接到第一開關10之第一端，而第一開關10耦接到輸入 端(Vin)，因第二開關12之第一端耦接到第一開關10之第 一端，所以第二開關的第一端與輸入端(Vin)相通；一電容 17具有第一端及第二端，則電容17之第一端耦接到第一 開關10之第二端，該電容Π之第二端耦接到第二開關U 之第二端；再則第三開關14具有第一端及第二端’則第 三開關14之第一端耦接到該電容Π之第二端；因電容Π 第二端已與第二開關12的第二端耦接，所以第三開關14 的第一端與第二開關12的第二端是相通的；以及一運算 放大器18具有一非反向輸入端(V+) ' —反向輸入端(V—） 以及一輸出端（Vout)，該反向輸入端（V—）耦接到第三開關 14之第二端，則該非反向輸入端(V+)耦接到電容Π之第 一端，又因電容17的第一端與第一開關1〇的第二端耦接， 所以該非反向輸入端(v + )與第一開關1〇的第二端相通， 而輸出端(Vout)耦接到反向輸入端(V—），又因反向輸入端 (V-)與第三開關14的第二端耦接，所以輸出端與第三開 關14的第二端是相通的。 當自動歸零相位時，第一開關1 〇及第二開關14閉路 而第二開關12開路，則如第3A圖所繪示的是根據第2圖 之較佳實施例在自動歸零相位時之等效電路圖所示’輸入 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）I Pack I Order Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) ^ 63456 * A7 6692twf / 006 __B7_____ 5. Description of the invention (multi) Phase, Control the input signal path through these two phases and then store the offset voltage on the capacitor. When the phase is amplified, the offset voltage stored on the capacitor and the offset voltage of the amplifier will cancel each other out due to the opposite polarity. Because the charge on the capacitor is referenced to the input signal instead of ground during auto-zero, it can have a wide dynamic operating range. This kind of operational amplifier can greatly improve the area utilization and power efficiency, so that the cost is reduced and the competitiveness is increased. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments and the accompanying drawings to make detailed descriptions as follows: Brief description of the drawings: FIG. 1 illustrates It is a circuit diagram of an offset voltage to be eliminated according to a general operational amplifier. Fig. 2 shows a circuit diagram according to a preferred embodiment of the present invention: Figs. 3A and 3B show a comparison of another mode according to Fig. 2 Equivalent circuit diagram of the preferred embodiment; and > Symbol description 10 '12, 14' 25, 26, 27, 28: Phase control switch 17, 23 '24: Storage capacitors 18, 20, 21: Preferred embodiment of the operational amplifier Generally, the operational amplifier eliminates the offset voltage, because it will cause the operational amplifier to occupy a large area on the chip, which will increase the amount of cost and lose the competitive advantage. Therefore, the present invention proposes an operational amplifier to eliminate the offset voltage __5 This paper Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 public love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 463456 6692twf / 006 ___B7_ V. Method of Invention Description (Battle). An operational amplifier 18, a capacitor 17, three switches 10, 12, 14 are required. Please refer to FIG. 2 for a circuit diagram according to a preferred embodiment of the present invention. The first switch 10 has a first end and a first end. Two terminals; and the second switch 12 also has a first terminal and a second terminal, the first terminal of the second switch 12 is coupled to the first terminal of the first switch 10, and the first switch 10 is coupled to the input terminal ( Vin). Because the first terminal of the second switch 12 is coupled to the first terminal of the first switch 10, the first terminal of the second switch is in communication with the input terminal (Vin); a capacitor 17 has a first terminal and a second terminal. Terminal, the first terminal of the capacitor 17 is coupled to the second terminal of the first switch 10, the second terminal of the capacitor Π is coupled to the second terminal of the second switch U, and the third switch 14 has a first terminal And the second terminal, the first terminal of the third switch 14 is coupled to the second terminal of the capacitor Π; because the second terminal of the capacitor Π has been coupled to the second terminal of the second switch 12, the The first terminal is in communication with the second terminal of the second switch 12; and an operational amplifier 18 has a non-inverting input terminal (V +) '-inverting input terminal (V-) and The output terminal (Vout), the inverting input terminal (V-) is coupled to the second terminal of the third switch 14, the non-inverting input terminal (V +) is coupled to the first terminal of the capacitor Π, and because of the capacitor 17 The first terminal of is coupled to the second terminal of the first switch 10, so the non-inverting input terminal (v +) is in communication with the second terminal of the first switch 10, and the output terminal (Vout) is coupled to the reverse The input terminal (V-) and the inverting input terminal (V-) are coupled to the second terminal of the third switch 14, so the output terminal is in communication with the second terminal of the third switch 14. When the phase is automatically reset to zero, the first switch 10 and the second switch 14 are closed and the second switch 12 is open. As shown in FIG. 3A, when the phase is automatically reset to zero according to the preferred embodiment of FIG. The equivalent circuit diagram shown in 'input this paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love)
- L^i . —Γ: r-v-裝-----r I--訂·--------線 .., f-· (請先閲讀背面之注意事項it填窝本頁) V 4 6 3 45 6 6692twf/006 B7 五、發明說明（t) 端(Vm)與電容17的第一端耦接，而非反向輸入端(V + )與 電容17的第一端親接，又因電容17的第一端與輸入端耦 接，所以非反向輸入端（V+)與輸入端（Vin)相通，而電容 的第二端與反向輸入端(V-）耦接，輸出端(Vout)與反向輸 入端(V—)耦接，又因電容17的第二端與反向輸入端(V—) 耦接，則輸出端(Vout)與電容17第二端相通。則輸出電壓 Vout=Vin+Vos ;而電容上之偏電壓爲Vos^Vout—Vin。 當放大相位時，當第二開關12爲閉路；第一、第三 開關10、14爲開路，則如3B圖所繪示的是根據第2圖較 佳實施例在放大相位之等效電路圖所示，輸入端(Vin)與電 容17的第二端耦接，電容17的第一端與非反向輸入(V+) 端耦接，而反向輸入端(V-)與輸出(Vout)端耦接。則運算 放大器的非反向輸入端(V + )電壓V+ =Vin—Vos ;而輸出 電壓爲Vout = V + + Vos = Vin 1故消除了偏移電壓Vos。 在數位類比轉換器（Digital To Analog Converter)中， 消除運算放大器的偏移電壓也佔了很重要的一環，其數位 類比轉換器包括一電阻等分網路（Resistive _ Divider Network)、參考電壓源（Reference Voltage Source)、準位放 大器(Level Amplifier)、及一些邏輯電路（Logic Circuit)所組 成的資料輸入儲存電路。數位類比轉換器是一數位訊號輸 入；一類比輸出的轉換器。而數位輸出無法控制類比機械 設備輸出，所以需用數位類比轉換器將數位輸出變爲同値 之類比電壓以控制電機輸出。一個理想的數位類比轉換 器，當數位訊號輸入等量變動時，則類比訊號也相對作一 \ 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) ...>裝-----r---訂--------- 經濟部智慧財產局員工消費合作社印製 46345 6 * A7 6692twf/006 ___B7_ 五、發明說明（ό) 等量變動，當輸入的位元數爲6Bit，輸出之電壓範圍0〜3V : 在輸出的解析度約爲47mv，而運算放大器的偏壓爲 0mv~30mv，使得輸入與輸出因運算放大器的偏移電壓而有 誤差，造成輸出訊號的失真。或用在Sensor小訊號時，因 訊號源本身之電壓就很小，更不容許運算放大器有偏移電 壓的存在，所以消除偏移電壓是很重要的。 綜合上述，現將本發明的優點略述如下。本發明可以 大幅提高面積的使用率和電路的性能，降低量產的成本’ 增加競爭力。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在.不脫離本發明之精 神和範圍內，當可做些許之更動與潤飾，因此本發明之保 護範圍當視後附申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項#ί填寫本頁) 裝 訂- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐）-L ^ i. —Γ: rv- 装 ----- r I--Order · -------- Line .., f- · (Please read the precautions on the back first to fill in this page ) V 4 6 3 45 6 6692twf / 006 B7 V. Description of the Invention (t) Terminal (Vm) is coupled to the first terminal of capacitor 17, and the non-inverting input terminal (V +) is close to the first terminal of capacitor 17 Because the first terminal of the capacitor 17 is coupled to the input terminal, the non-inverting input terminal (V +) is connected to the input terminal (Vin), and the second terminal of the capacitor is coupled to the reverse input terminal (V-). , The output terminal (Vout) is coupled to the reverse input terminal (V-), and because the second terminal of the capacitor 17 is coupled to the reverse input terminal (V-), the output terminal (Vout) and the second terminal of the capacitor 17 Communicate. Then the output voltage Vout = Vin + Vos; and the bias voltage on the capacitor is Vos ^ Vout-Vin. When the phase is amplified, when the second switch 12 is closed; the first and third switches 10 and 14 are open, as shown in Figure 3B is the equivalent circuit diagram of the amplified phase according to the preferred embodiment of Figure 2 The input terminal (Vin) is coupled to the second terminal of capacitor 17, the first terminal of capacitor 17 is coupled to the non-inverting input (V +) terminal, and the inverting input (V-) and output (Vout) terminals Coupling. Then the non-inverting input terminal (V +) voltage of the operational amplifier is V + = Vin-Vos; and the output voltage is Vout = V + + Vos = Vin 1 so the offset voltage Vos is eliminated. In digital to analog converters, eliminating the offset voltage of the operational amplifier also occupies a very important part. The digital analog converter includes a resistive divider network (Resistive _ Divider Network), a reference voltage source (Reference Voltage Source), level amplifier (Level Amplifier), and some logic circuits (Logic Circuit) data input storage circuit. A digital analog converter is a digital signal input; an analog output converter. The digital output cannot control the output of the analog mechanical equipment, so a digital analog converter is needed to change the digital output to the same analog voltage to control the motor output. An ideal digital analog converter, when the digital signal input changes by the same amount, the analog signal is relatively relative. 7 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the back first Please fill in this page for the matters needing attention) ... > Packing ----- r --- Order --------- Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 46345 6 * A7 6692twf / 006 ___B7_ 5. Description of the invention (ό) Equivalent change, when the number of input bits is 6Bit, the output voltage range is 0 ~ 3V: the resolution of the output is about 47mv, and the bias of the operational amplifier is 0mv ~ 30mv, so that The input and output have errors due to the offset voltage of the op amp, causing distortion of the output signal. Or when it is used for small sensor signals, the voltage of the signal source itself is very small, and the offset voltage of the operational amplifier is not allowed, so it is very important to eliminate the offset voltage. In summary, the advantages of the present invention are briefly described as follows. The invention can greatly improve the area utilization rate and circuit performance, reduce the cost of mass production, and increase competitiveness. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended claims. (Please read the precautions on the back first # Fill in this page) Binding-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (21〇 297 mm)