TW463385B - Aluminum-doped zirconium dielectric film transistor structure and deposition method for same - Google Patents

Aluminum-doped zirconium dielectric film transistor structure and deposition method for same Download PDF

Info

Publication number
TW463385B
TW463385B TW089114476A TW89114476A TW463385B TW 463385 B TW463385 B TW 463385B TW 089114476 A TW089114476 A TW 089114476A TW 89114476 A TW89114476 A TW 89114476A TW 463385 B TW463385 B TW 463385B
Authority
TW
Taiwan
Prior art keywords
group
range
scope
thin film
film
Prior art date
Application number
TW089114476A
Other languages
Chinese (zh)
Inventor
Yanjun Ma
Yoshi Ono
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Application granted granted Critical
Publication of TW463385B publication Critical patent/TW463385B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Inorganic Insulating Materials (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

Description

463385 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 登明之背景及概述 , 本發明一般係有關於集成電路（I c)製造方法，而更特定 言之，係有關於一種高介電常數柵絕緣薄膜及—種此種薄 膜之沉積方法。 1 目前Si VLSI技術係使用Si〇2作為MOS裝置之柵介電質。 由於裝置尺寸愈來愈小，Si〇2層之厚度也必須減少以維持 柵與溝槽區之間之相同電容。預期在將來厚度將小於2毫 微米（nm)。然而’通過此種Si〇2薄膜之高隧道電流 (tvinnelmg current)之發生使得必須考慮使用另類材料。具 尚介電常數之材料可讓柵介電層作成更厚，而因此減輕隨 道電流的問題。這些所謂的高k介電薄膜，在此處係定義 為相對於二氧化矽具有較高之介電常數。一般而言，二氧 化石夕之介電常數為約4而高k薄膜之介電常數則為大於约 1 0。目前高k候用材料包括氧化鈦（Ti〇2)，氧化銼（Zr〇2)， 氧化钽（Ta205)及氧化鋇及鳃鈦（Ba，Sr)Ti03。 一個與上述高介電質有關之普通問題為彼等在正常製備 條件下會發展出結晶結構。結果，薄膜之表面即變得非常 粗糙。表面粗糙會在鄰近介電薄膜之溝道區中引起非均勻 之電場。此等薄膜即不適合作為MOSFET裝置之柵介電 質。 由於咼直接隧道電流之故’薄於1,5 nm之Si02薄膜即不 能用作為CMOS裝置中的柵介電質。目前業界都在致力於 尋找Si〇2之替代品’而以Ti〇2及Ta2〇5最受人矚目。然而， 高溫後沉積退火與介面Si〇2層之形成都會使相當於小於1.5 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝---1 l·---訂---------線 ί請先閱讀背面之注意事項S寫本頁〕 463385 A7 B7 五、發明說明（ nm之等效Si02厚度（EOT)極難達成。 如果高k介電薄膜可用作爲M0S電晶體中柵電極與 、、 (靖先閱讀背面之注意事項^^^寫本頁) 道區間之絕緣層，則將很有利β 如果高k介電薄，可形成具有減低之表面粗糙度，結▲性 及漏電率，將很有利。如果這些非結晶高介電常數材料可 用於集成電路之栅介電質及貯存電容器，將很有利。 若改良之高k介電材料可藉僅在目前既有之高]^介電材料 中摻雜或添加額外元素而形成，將很有利。 因此，本發明提供一種具有高介電常數（1〇至25)之薄 膜。該薄膜包括三價金屬，如鋁（八丨），钪（Sc)或鑭（La)， 自錯（Zr)及給（Hf)所組成之族群中所選出之金屬及氧。 一般而薄膜中三價金屬之百分比爲不超過約5〇〇/。， 而A1之百分比爲約2 5 %則爲較佳。 亦提供者爲一種M0SFET電晶體。該電晶體包含姆電 極 '在該柵電極下方具有上表面之溝道區，及夾置於栅電 極與溝道區上表面中的柵介電薄膜。介電薄膜之内容物如 上所述。一般而言’柵介電薄膜之厚度係在約2〇與2〇〇人之 範圍内。 經濟部智慧財產局員工消費合作社印^^ 本發明之一些方面進一步包含具有介面層之電晶體；該 介面層之厚度在約2至5A之範園内，且夾置於溝道區與柵 介電薄膜之間，介面材料係自氮化矽及氧氮化矽所組成之 族群中所選出’藉以將溝道區上表面作成更平滑以防止 MOSFET之電子遷移率減低。 在製作具有表面之集成電路（IC)時，也提供一種濺鍍方 -5- 本紙張尺㈣財關緒準(CNS)A4規格（210 >： 297公爱） A7 4 633 85 ----B7_______ 五、發明說明（3 ) 法以在1C表面上形成摻雜A1之金屬氧化物薄膜。該方法包 含下列步驟： a) 建立包括氧之氛圍； b) 在1C矽表面上濺艘至少一種包括自及Hf所组成之族 群中所選出之金屬及包括三價金屬之目標金屬； c) 回應步驟a)及b)，形成摻雜八丨之金屬氧化物膜；及. d) 在溫度範圍約4〇〇至80〇1下退火，藉以形成具有高介 電常數及良好絕緣性質之薄膜。 在本發明之一些方面，步驟（a)包括以個別目標—包括自 Zr及Hf所组成之族群中所選出之金屬之第一目標及包括三 價金屬之第二目標-共濺鍍。 另外’提供一種沉積捧雜A1之金屬氧化物薄膜之化學蒸 氣沉積（C VD )法，其包含下列步驟： a) 製備至少一種包括自Zr及Hf所组成之族群中所選出之 金屬及三價金屬之前驅物； b) 將前驅物蒸發； C)建立包括氧之氛圍； · d) 將IC表面上之前驅物分解，以藉由化學蒸氣沉積 (C VD)法沉積包括自z r及H f所組成之族群中所選出之金 屬，三價金屬及氧之合金薄膜；及 e) 在溫度範圍約400至800 °C下退火，藉以形成具有高介 電常數及良好絕緣性質之薄膜。 在另一替代例中，提供一種沉積摻雜A1之金屬氧化物薄 膜之蒸氣沉積方法，包括下列步驟： -6 - 本紙張尺度適用中國囤家標準（CNS)A4規格（210 X 297公釐） ----- -----I I I --------訂·-------- (請先閲讀背面之注意事項再4寫本頁) 經濟部智慧財產局員工消費合作社印製 4 ο 3 3 8 5 / c 〇 〇 〇 - 4 6 3參鉍丨54476號專利申請案 〇 P ) 中文說明書修正頁（90年8月） 品年次月芷/f fiw鑪象 1、發明説明（4 ) a) 建立真空（無氣體）氛圍； b) 製備至少一種包括自Zr及Hf所組成之族群中所選出之 金屬及三價金屬坩堝； C )將該至少一個坩堝於約1000至2000 °c範圍内之溫度下 加熱以蒸發步騾（b)製備之金屬； d)回應步驟a)至c)，沉積包括自Z r及H f所組成之族群f 所選出之金屬及三價金屬之合金薄膜；及 e )在包括氧之氛圍中及約400 - 800 °C範圍内之溫度下退火 以形成具有氧之合金薄膜，而形成具有高介電常數及良好 絕緣性質之薄膜。 附圖之簡要說明 圖1係一流程囷，說明本發明摻雜A1之金屬氧化物薄膜之 激鍵沉積方法。 圖2顯示Zr〇2薄膜與本發明摻雜A1之Zr02薄膜之X -射線 繞射測量比較。 圖3顯示100微米（yj^XlOO /zm電容器之63A Zr-AI-〇 薄膜之高頻CV曲線圖。 圖4係一 ϊ V曲線圖，顯示上述本發明薄膜之漏電特徵。 圖5顯示在約400-50(TC後沉積退火後之漏電特徵（初沈積與 經退火（500°C3〇S 〇2)之Zr-Al-Ο薄膜之I - V曲線）。 圖6顯示本發明三種不同厚度薄膜之高頻cv曲線，其中 p -型基材上3-7.5 nm Zr-Al-Ο薄膜之高頻（1 MHz) CV特徵後沈積 退火係在500°C下進行。 圖7顯示以Zr-Al-Ο薄膜厚度為函數之有效介電常數與薄膜 厚度之間的輕微關係，此即顯示有最小介面si〇2層之存 在。 圖8顯示圖6薄膜之iv曲線（Zr-Al-Ο之累積I V特徵）。 圖9顯示η -型基材上之漏電較p-型基材上類似厚度之薄膜 本紙張又度通用中8國家標準(CNS) Α4规格(210X297公釐} 4633 8 5 第89丨丨4476號專利申請案 中文說明書修正頁（90年8月） A7 ^_ B7 五、發明説明（5 ) 大約丨0倍（n ( @ 1 . 5 v)及p_型（@ i . 5 v)基材上Ζγ·α1_〇薄膜漏 電與溫度關係）。 圖10及11顯示圖6薄膜之可靠性，儘管薄膜中有電荷阱 之存在其中圖1 0係4.5 nm Zr-Al-Ο薄膜上TDDB測量結果之分 佈’應力電壓列示於嵌表中； 圖1 1係以柵電壓為函數之TDDB平均失敗時間外插值，若 操作電壓在-13V以下，可得丨〇年以上之平均壽命。 圖12及13顯示使用本發明摻雜A1之金屬氧化物薄膜製成 之完成電晶體中之步驟。 圖14係一流程圖，顯示形成本發明之摻雜a丨之金屬氧化 物薄膜之CVD方法之步騾。 圖15係一流程圖，顯示形成摻雜八丨之金屬氧化物薄膜之 蒸發方法之步騾。 鼓隹具體例之詳細說明 本發明研究掺雜A1之錯氧化物。掺雜Ai可降低漏電’而 提问柵介電質之結晶溫度。具有效介電常數為12_18之3 nM Zr-Al-Ο薄膜曾達到記錄上最高累積電容約28毫微微_ 法拉第（femt0_farads，fF)/平方微米’及漏電小於〇丨A/平 方厘米’曾以具有谩異特徵之Zr_Al-〇柵介電質製作成次 微米PMOSFETs。簡言之，據發現，以三價金屬（如ΑΙ)摻 雜Zr〇2薄膜可得在典型（高溫）加工處理條件下仍保持無晶 形之薄膜。 本發明係一種具有對氧化矽而言較高介電常數之薄膜， 其包含三價金屬’自锆（Zr)及铪（Hf)所组成之族群中所選 出之金屬’及氧。高介電薄膜可阻止結晶，保持無晶形以 形成較平滑表面。三價金屬係自鋁（A〇 ’钪（s c)及鑭（L a) 所組成之族群中所選出。 在有用應用中’薄膜厚度一般係在約2 〇至2〇〇 a之範圍 8· 本紙张尺度逋用_國理家標準(CNS) A4规格(210 X 297公爱） 463385 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 内’介電常數係在約丨〇至2 5之範圍内。 薄膜中AI，或其他三價金屬之百分比一般不超過約 5 0 %，而以百分比為約2 5 %為較佳。 圖1係一流程圖，顯示本發明摻雜A1之金屬氧化物薄膜 之濺鍍沉積方法。步驟1〇提供—具有表面之集成電路 (1C)。步驟12建立一包括氧之氛圍。一般而言’步驟Q包 括也包含氬(A〇之氛圍’ 〇AAr之比係在約5至25%之範 ，内。壓力係在約！至10毫托爾（mT)之範圍内。步驟㈣ 土/種包括®Zr&Hf所組成之族群中所選出之金屬之目 標金屬濺鍍在IC表面上。步騾14也將三價金屬濺鍍在⑴表 面上°三價金屬係自銘（A1)，钪（s〇及鑭（La)所組成之族 群t所選出。在本發明之-些方面，步驟Μ包括以下個別 目心包括自Zr及Hf所组成之族群中所選出之金屬之第— 目標及包括三價金屬之第二目標·共濺鍍。 一步驟〗6，回應步驟12及14，形成捧雜八丨之金屬氧化物 溥挺。步驟18在約400_800 ΐ範圍内之溫度下退火。退火 時間’视退火溫度而定’係在約1Q秒至⑽鐘之範園内。 步驟18包括建立—種氛園，其包括自Ar，N2，N2:h2形成 乳體’ 〇212〇12〇，，無氣體（無氣體環境）及氧 U所组成之族群中所選出之元素。步驟20係-產物，其 中形成具有高介電常數及良好絕緣性質之薄膜。 ^ 在本發明之—些方面，其中步驟1〇提供矽⑴表面，步驟 :6:前有另外一步驟。步驟⑷(未示幻在⑴矽表面建立 约ΐ溫至4 0 0 C範圍内之溫度^ -9 本纸張尺度適用中國國家標準（cns)at^⑵G χ 297公 裝-----r---訂---------線 <請先閲讀背面之注意事項尹4寫本頁> 經濟部智慧財產局員工消費合作社印製 633 85 A7 _____B7____ 五、發明說明（7 ) Z r - A1 - 0及H f- A1 - 0薄膜係藉上述共濺嫂方法製備。濺 鍍功率比調整至随氧化锆中A1濃度之量而異。 ‘463385 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (Background and overview of the invention, the present invention generally relates to the manufacturing method of integrated circuits (IC), and more specifically, it relates to a high-level Dielectric constant gate insulating film and a method for depositing such a film. 1 At present, Si VLSI technology uses Si02 as the gate dielectric of a MOS device. As the device size becomes smaller, the thickness of the Si02 layer also decreases. Must be reduced to maintain the same capacitance between the gate and trench regions. It is expected that the thickness will be less than 2 nanometers (nm) in the future. However, the occurrence of the high tvinnelmg current through this Si02 film makes it necessary to consider Use of alternative materials. Materials with a high dielectric constant allow the gate dielectric layer to be made thicker, thereby reducing the problem of current flow. These so-called high-k dielectric films are defined here as relative to silicon dioxide. Has a high dielectric constant. In general, the dielectric constant of the dioxide is about 4 and the dielectric constant of the high-k film is greater than about 10. At present, high-k candidate materials include titanium oxide (Ti. 2) Oxide files (ZrO2), tantalum oxide (Ta205), barium oxide and gill titanium (Ba, Sr) Ti03. A common problem related to the above-mentioned high dielectrics is that they will develop a crystalline structure under normal preparation conditions As a result, the surface of the film becomes very rough. The surface roughness can cause a non-uniform electric field in the channel region adjacent to the dielectric film. These films are not suitable as gate dielectrics for MOSFET devices. Because of the direct tunnel current The reason 'Si02 thinner than 1,5 nm cannot be used as the gate dielectric in CMOS devices. At present, the industry is working hard to find an alternative to Si02', with Ti〇2 and Ta205 being the most popular. It is noticeable. However, both post-annealing at high temperature and the formation of the interface SiO2 layer will make the equivalent of less than 1.5 -4- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- --------- install --- 1 l · --- order --------- line ί Please read the precautions on the back S to write this page] 463385 A7 B7 V. Description of the invention (The equivalent Si02 thickness (EOT) of nm is extremely difficult to achieve. If a high-k dielectric film can be used as a gate electrode in a MOS transistor, and (Jing (Please read the note on the back side ^^^ write this page) The insulation layer in the track area will be very beneficial. Β If the high-k dielectric is thin, it can form a surface with reduced surface roughness, junction properties and leakage rate, which will be very advantageous. It would be advantageous if these amorphous high dielectric constant materials can be used for gate dielectrics and storage capacitors of integrated circuits. If the improved high-k dielectric materials can be used only in the existing high] ^ dielectric materials It may be advantageous to form it by adding or adding additional elements. Therefore, the present invention provides a thin film having a high dielectric constant (10 to 25). The film includes trivalent metals, such as aluminum (A), ytterbium (Sc) or lanthanum (La), self-mistake (Zr), and selected metals from the group consisting of Hf and oxygen. Generally, the percentage of trivalent metal in the film is not more than about 500 /. It is more preferable that the percentage of A1 is about 25%. Also provided is a MOSFET transistor. The transistor includes a ohmic electrode, a channel region having an upper surface below the gate electrode, and a gate dielectric film sandwiched between the gate electrode and the upper surface of the channel region. The contents of the dielectric film are as described above. Generally, the thickness of the 'gate dielectric film is in the range of about 20 and 200 people. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ Some aspects of the present invention further include a transistor having an interface layer; the thickness of the interface layer is in the range of about 2 to 5A and is sandwiched between the channel region and the gate dielectric Between the thin films, the interface material is selected from the group consisting of silicon nitride and silicon oxynitride to make the upper surface of the channel region smoother to prevent the electron mobility of the MOSFET from decreasing. When manufacturing integrated circuits (ICs) with a surface, a sputtering method is also provided. -5- This paper ruler is a standard of A4 (210 >: 297 public love) A7 4 633 85 ---- B7_______ 5. Description of the invention (3) The method is to form a metal oxide film doped with A1 on the 1C surface. The method includes the following steps: a) establishing an atmosphere including oxygen; b) splashing on a 1C silicon surface at least one metal selected from a group consisting of self and Hf and a target metal including a trivalent metal; c) response Steps a) and b), forming a metal oxide film doped with metal; and d) annealing at a temperature in the range of about 400 to 801 to form a thin film with high dielectric constant and good insulation properties. In some aspects of the invention, step (a) includes co-sputtering with individual targets including a first target of a metal selected from the group consisting of Zr and Hf and a second target including a trivalent metal. In addition, a method of chemical vapor deposition (C VD) for depositing a metal oxide thin film of doped A1 is provided, which includes the following steps: a) preparing at least one metal selected from the group consisting of Zr and Hf and trivalent Metal precursors; b) Evaporate the precursors; C) Establish an atmosphere including oxygen; d) Decompose the precursors on the IC surface to deposit from zr and H f by chemical vapor deposition (C VD) Selected metal, trivalent metal, and oxygen alloy thin films of the group; and e) annealing at a temperature range of about 400 to 800 ° C to form a thin film with high dielectric constant and good insulation properties. In another alternative, a vapor deposition method for depositing a metal oxide film doped with A1 is provided, which includes the following steps: -6-This paper size is applicable to China Store Standard (CNS) A4 (210 X 297 mm) ----- ----- III -------- Order · -------- (Please read the notes on the back before writing this page) Printed by the cooperative 4 ο 3 3 8 5 / c 〇〇〇- 4 6 3 bismuth 丨 54476 patent application 〇P) Chinese manual revision page (August 90) Year of the year 芷 / f fiw furnace image 1 Description of the invention (4) a) Establish a vacuum (gas-free) atmosphere; b) Prepare at least one crucible including a metal and a trivalent metal selected from the group consisting of Zr and Hf; C) Place the at least one crucible in about Heating at a temperature in the range of 1000 to 2000 ° c to evaporate the metal prepared in step (b); d) in response to steps a) to c), depositing a metal selected from the group f consisting of Z r and H f and Alloy films of trivalent metals; and e) annealing in an atmosphere including oxygen at a temperature in the range of about 400-800 ° C to form alloy films having oxygen Forming a thin film having a high dielectric constant and good insulating properties of. Brief Description of the Drawings Fig. 1 is a flow chart illustrating a method for depositing an A1 doped metal oxide thin film by the present invention. Figure 2 shows a comparison of X-ray diffraction measurements of a ZrO2 film with an Al-doped Zr02 film of the present invention. Figure 3 shows the high-frequency CV curve of a 63-micron (yj ^ X100 / zm) capacitor 63A Zr-AI-〇 film. Figure 4 is a ϊV curve chart showing the leakage characteristics of the film of the present invention. Figure 5 shows about 400-50 (Leakage characteristics after deposition and annealing after TC (I-V curves of Zr-Al-O thin film deposited and annealed (500 ° C3SO2)). Figure 6 shows three different thickness films of the present invention. High-frequency cv curve, where the high-frequency (1 MHz) CV characteristic of 3-7.5 nm Zr-Al-O thin film on p-type substrate is post-deposition annealing at 500 ° C. Figure 7 shows the Zr-Al -〇 Thin film thickness is a function of the effective relationship between the effective dielectric constant and the thickness of the film, which shows the existence of the smallest interface SiO2 layer. Figure 8 shows the iv curve of the film in Figure 6 (the accumulation of Zr-Al-O IV characteristics). Figure 9 shows that the leakage current on the η-type substrate is higher than that of a film of similar thickness on the p-type substrate. The paper is also commonly used in China National Standard (CNS) A4 specification (210X297 mm) 4633 8 5th 89th丨 丨 Page 4476 of the Chinese specification of the patent application (August 1990) A7 ^ _ B7 V. Description of the invention (5) Approximately 丨 0 times (n (@ 1. 5 v) and p_type (@ i. 5 v) Leakage of the γ · α1_〇 thin film on the substrate as a function of temperature). Figures 10 and 11 show the reliability of the thin film of Figure 6, despite the presence of charge traps in the thin film. Figure 10 is 4.5 nm Zr-Al -The distribution of TDDB measurement results on the thin film 'stress voltage is listed in the embedded table; Figure 1 1 is the extrapolation of the TDDB average failure time using the gate voltage as a function. If the operating voltage is below -13V, it can be obtained for more than 10 years Average life. Figures 12 and 13 show the steps in a completed transistor made using the A1 doped metal oxide film of the present invention. Figure 14 is a flowchart showing the formation of a doped metal oxide of the present invention Steps of the CVD method for thin films. Figure 15 is a flowchart showing the steps of an evaporation method for forming a doped metal oxide film. Detailed description of specific examples of the drum The present invention studies the doped A1 doped oxide . Doping with Ai can reduce leakage and ask the crystallization temperature of the gate dielectric. The 3 nM Zr-Al-O film with an effective dielectric constant of 12_18 has reached a record of the highest accumulated capacitance of about 28 femto_ Faraday (femt0_farads, fF) / square micron 'and leakage current is less than丨 A / cm² was used to fabricate sub-micron PMOSFETs with Zr_Al-〇 gate dielectrics with unique characteristics. In short, it was found that doping Zr〇2 films with trivalent metals (such as Al) can be obtained in Films that remain amorphous under typical (high temperature) processing conditions. The present invention is a thin film with a high dielectric constant for silicon oxide, which contains trivalent metals, zirconia (Zr) and hafnium (Hf). The selected group of metals' and oxygen. The high-dielectric film prevents crystallization and remains amorphous to form a smoother surface. The trivalent metal is selected from the group consisting of aluminum (A ′ ′ (sc) and lanthanum (L a). In useful applications, the thickness of the thin film is generally in the range of about 20 to 2000a. 8 · Standards for this paper_National Standards (CNS) A4 specification (210 X 297 public love) 463385 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (within 6 the dielectric constant is about 丨Within the range of 0 to 25. The percentage of AI or other trivalent metals in the film generally does not exceed about 50%, and the percentage is preferably about 25%. Figure 1 is a flowchart showing the blending of the present invention Sputter deposition method for metal oxide thin film of doped A1. Provided in Step 10—Integrated Circuit (1C) with surface. Step 12 establishes an atmosphere including oxygen. Generally speaking, “Step Q includes argon (A〇 Atmosphere '〇 The ratio of AAr is in the range of about 5 to 25%. The pressure is in the range of about! To 10 millitorr (mT). Step ㈣ The soil / species includes the group consisting of ®Zr & Hf The target metal of the selected metal is sputtered on the IC surface. Step 14 also sputters the trivalent metal on the surface. The trivalent metal is selected from the group t consisting of Ming (A1), osmium (s0 and lanthanum (La). In some aspects of the present invention, step M includes the following individual objectives including those consisting of Zr and Hf The first target of the selected metal in the group and the second target including the trivalent metal. Co-sputtering. One step: 6, respond to steps 12 and 14, forming a metal oxide stiffener. Step 18 is in Annealing at a temperature in the range of about 400_800 。. The annealing time 'depends on the annealing temperature' is in the range of about 1Q seconds to ⑽Zhong Zhi Fan Yuan. Step 18 includes the establishment of a scented garden, which includes Ar, N2, N2: h2 Formation of a milk body '2121212, a selected element of a group consisting of no gas (no gas environment) and oxygen U. Step 20 is a product, in which a thin film having a high dielectric constant and good insulation properties is formed ^ In some aspects of the present invention, step 10 provides a silicon wafer surface, and step: 6: there is another step before. Step ⑷ (not shown on the silicon surface to establish a temperature range of about 40 ° C to 4 0 C Temperature ^ -9 This paper size applies Chinese National Standard (cns) at ^ ⑵G χ 297 Packing ----- r --- Order --------- line < Please read the notes on the back first Yin 4 Write this page > Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 633 85 A7 _____B7____ 5. Description of the invention (7) Z r-A1-0 and H f- A1-0 films are prepared by the above-mentioned co-sputtering method. The sputtering power ratio is adjusted to vary with the amount of A1 concentration in zirconia.

I 以下圖式顯示：以濺鍍比爲Zr = 300瓦（W)/A1 = 60W，在 〇2 : Ar氣體混合物=1.5毫托爾（mT)中製備之63入Zr-Al-◦薄膜之電容對電壓（C-V)及電流對電壓（i-V)特性。薄膜 進一步在氧氣中及500T：下退火30秒。 圖2顯示Zr〇2薄膜與本發明摻雜AitZr〇2薄膜比較之χ· 射線繞射測量。強峰顯示Zr02係結晶，而濺鍍之z r - A卜Ο 薄膜’即使在800 °C退火之後仍保持無晶形。I The figure below shows the 63-in Zr-Al-◦ film prepared with a sputtering ratio of Zr = 300 watts (W) / A1 = 60W, prepared in 〇2: Ar gas mixture = 1.5 millitorr (mT) Capacitance versus voltage (CV) and current versus voltage (iV) characteristics. The film was further annealed in oxygen at 500T for 30 seconds. FIG. 2 shows the χ · ray diffraction measurement of the ZrO2 film compared with the doped AitZrO2 film of the present invention. The strong peak shows that the Zr02 system is crystallized, and the sputtered zr-AbO thin film 'remains amorphous even after annealing at 800 ° C.

藉濺鍍法沉積Al/TiN上電極，並作成圖樣以製造10〇 x 100 " m2電容器供電測試之用。圖3顯示！ 〇〇微米m) X 100 "m電容器之63A Zr-Al-Ο薄膜之高頻CV曲線圖。從 C V測量測得Si〇2等效厚度爲〜1,5 nm，其即顯示此薄膜之 介電常數爲〜16。 圖4係一IV曲線圖’顯示上述本發明薄膜之漏電特徵。 漏電僅約6 X 1CT5 A /平方厘米，遠小於相等厚度之Si〇2薄 膜。 以功率比爲1 : 5 ’在氧及氬之混合物中及室溫下共濺鍍 A1及Zr目標製備摻雜A1之Zr02薄膜。圖5顯示在約400至 500 °C下後沉積退火之後之漏電特徵。此一溫度大大低於 其他薄膜所需要者，如Ti02薄膜，其通常須在750°C以上退 火才能減低漏電。薄膜之厚度係以光譜橢圓光度法評估。 圖6顯示本發明三種不同厚度薄膜之高頻c v曲線。m m 薄膜在柵偏壓（gait bias)爲-1.5 V時獲得最高累積電容26 -10- 本紙張尺度適用争國國家標準（CNS)A4規格（210 X 297公釐） I I ---------訂·--------線 (請先間讀背面之注意事項#4寫本頁> 4^3385 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（8) 平万微米，在更高柵偏壓時，柵漏電會使c 升’而不能精確測量電容。藉由外插法可估計電容在柵 壓為-2V時為約28fF/+方微米。這相當於典型介電質厚度 (CDT = Si02/C)為約 1.2 nm。將估計為％ 〇 q ® 耵怙彳為約0.3 nm之量子機械 才又正G括在内’即可得小於1 〇 nm之EOT。 圖7顯示薄膜有效介電常數與薄膜厚度間之輕微關係，此 即顯示有最小介面Si02層之存在。 圖8顯示圖6薄膜之IV曲線。以3 nm.膜而言，在-1 5γ 時，柄漏電為約0.5A/平方厘米，.而在可能操作電壓為_v 時則為約0.1 A/平方厘米。 圖9顯示η -型基材上之漏電遠較p _型基材上類似厚度之 薄膜大約10倍。漏電與溫度之關連也較大。這即顯示傳導 機制最可能是佛蘭凱爾-普立（Frenkd_p0〇ie)型，及電子傳 導之能障壁（energy barrier)遠較孔傳導者為小。電子味之 存在並不令人訝異，因為介電薄膜係使用濺鍍技術製得。 圖1 0及I 1顯示圖6薄膜之可靠性’儘管薄膜中有電荷牌 之存在。時間依賴之介電質擊穿（time dependent dielectric breakdown ’ TDDB)壽命’在約1.3V以下操作時，可外插 到1 0年以上。 具有Zr-Al-Ο柵介電質之PM0S電晶體係使用氮化物栅取 代方法加工處理’其中輕微摻雜之漏極（lightly d〇ped drain ’ LDD)及源極/漏極（source/drain)區係在最後柵昼 (gate stack)固定之前形成。Zr-Al-Ο柵介電質之厚度為約 6 nm，而在累積時測得之C最大為20 fF/ μ m2以上。 -11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I---裝-----r ---訂---------線 (請先閱讀背面之注意事項寫本頁) 463385 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（9 ) 自本發明電容器薄膜之研究 木到之相同《— -05- i1% xh Ά 用於柵介電質，貯存電容器 瓜特徵也適 鐵電存貯器。 呢阳體（1Τ) 圖1 2及1 3顯示使用本發明松 个货明掺雜Α1之金屬氧化物薄膜劁 之完成M〇SFET電晶體之步驟。 吳製侍 戈令r 士 L _ 1 Z *•.貝不具有溝道區5 2而 溝道區有上表面54之電晶辦^ ^ „ 薄膜56。 —0。溝道區52上方為柵介電 圖13顯示夹置於柵電極58與溝道區上表心中間的拇介 電薄膜。柵介電薄膜，相對於二氧切，具有較高介電常 數且包括自锆（Zr)及鈐（Hf)所組成之族群中所選出之金屬 及氧。柵介電薄膜56包括自銘（A1)，航（Sc)及綱（La)所组 成之族群中所選出之三價金屬。 薄膜56中之A1或其他三價金屬之百分比係在約〇至5 〇% 之範園内。薄膜5 6中A1之百分比較佳為約2 5 %。柵介電薄 膜5 6之厚度6 0 (圖1 3 )係在約2 0至200A之範圍内。柵介電 薄膜5 6之介電常數係在約1 〇至2 5之範圍内。 在本發明之一些方面’電晶體50包含具有厚度64在約2 至5A之範園内且夹置於溝道區52與柵介電薄膜56之間的 介面絕緣層6 2。介面絕緣層6 2係由自氮化碎與氧氮化;ί夕所 組成之族群中所選出之材料所構成，藉以使溝道區上表面 5 4作成更平滑以提高MOSFET 50之電子遷移率。 在大CMOS裝置應用之栅介電質之情形時，晶片係使用 任何最佳習知方法如隔離加工處理，繼之形成P -井及N -井 以使溝道區曝露。仍然可能需要超薄之氧化障壁層。在此 -12 本纸張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） - —1 — — — > I I I l· I I ] ^ «— — — I — — — — (請先閱讀背面之注意事項寫本頁) 4 633 85 經濟部智慧財產局員工消費合作杜印製 A7 五、發明說明（1ί)) 情形時，可能之障壁層包括氮化矽及氧氮化矽。接著，沉 積高k介電質。製備薄膜之方式有若干： A _在惰性或氧化性周圍中共濺錄z r及a 1 ; B ‘在惰性或氧化性周圍中共激錄複合目標，如z r _ a 1 ; C·化學蒸氣沉積Zr-Al-Ο及Hf-Al_〇 ;或 D.蒸發。 , 沉積之後，薄膜即在惰性（例如，Ar，，n2 : h2形成 氣體）及/或氧化性（〇2，H2〇 ’ Ν2〇，NO)，及無氣體周 圍氣氛中及命溫（400 - 900 °C )下退火以控制高k薄膜及高 k / S 1介面。然而’若薄膜係以蒸發沉積，則退火過程一般 包括氧，以在合金薄膜中包含氧。 退火之後，即沉積柵極，並作成柵疊之圖樣。柵材料可 爲金屬或聚矽。然後，使用任何最佳之裝置製作過程，以 習知方法，或使用氮化物，聚矽或聚siGe僞柵極之柵極取 代方法完成該裝置。 圖14係一流程圖，顯示形成本發明摻雜μ之金屬氧化物 薄膜之CVD方法之步驟。步驟1〇〇提供一具有表面之集成 電路（1C)。步驟1〇2製備至少—種前驅物，其包括自〜及 Hf所组成之族群中所選出之金屬及三價金屬。步驟ι〇2包 括自铭（A1)，銳（Sc)及鑭（La)所组成之族群中所選出之三 價金屬。在本發明之一些方面，步骤1〇2包含包括自^及 Hf所组成之族群中所選出之金屬之第一前驅物及包括三價 金屬t第二前驅物。步驟1〇4將該至少一前驅物蒸發。步 驟106建立包括氧之氛圍。一般而言，步驟106包括包含氬 -13- 本紙張尺度適用中國國家標準（CNSW規格 (210 X 297 公釐） ---------------------訂—-------- <請先閲讀背面之注意事項再4寫本I) 463385 經濟部智慧財產局員工消費合作社印制农 A7 B7 五、發明說明（11 ) (A〇之氛圍，〇2與Ar之比在約5至25%之範圍内，而壓力 則在約1至10T之範圍内。步驟1〇8將1(：表面之前驅物分 解，以藉化學蒸氣沉積（C VD )法沉積包括自ζ Γ及H f所组成 之族群中所選出之金屬，三價金屬及氧之合金薄膜。 步驟110係在溫度約400至800。(：之範園内退火。步驟i 10 包括建立包括自Ar，N2，N2 : H2形成氣體，〇2，h20 , NzO ’ NO，無氣缉及氧電漿所组成之族群中所選出之元素 之氛圍。步驟112係一產物，其中形成具高介電常數及良 好絕緣性質之薄膜。 在本發明之一些方面，步驟1〇〇提供—矽1C表面，及步 驟108之前置有另外一步驟。步驟106&將IC矽表面溫度建 立在約300至500°C之範圍内。 圖1 5係一流程圖，顯示形成摻雜A丨之金屬氧化物薄膜之 蒸發方法之步驟。步驟200提供一具矽表面之集成電路 (1C)。步驟202製備至少一個包括自zr及Hf所组成之族群 中所選出之金屬及三價金屬之坩堝。步驟202包括自鋁 (A1)，銳（S c )及鑭（L a)所组成之族群中所選出之三價金 屬。步驟204建立眞空（無氣體）氛園。步騍206將該至少一 個坩堝加熱至坩堝溫度在約1000至2000 °C之範圍内，以蒸 發步驟202所製備之金屬。步驟208，回應步驟202至206， 將包括自Zr及Hf所组成之族群中所選出之金屬及三價金屬 之合金薄膜沉積a步驟210在包括氧之氛圍中及溫度範圍 約400至800 °C下退火以形成包括自Z r及H f所组成之族群中 所選出之金屬，三價金屬及氧之合金薄膜。步雜210包括 • 14- 本紙張尺度適用令舀國家標準（CNS)A4規格（210 x 297公釐） ---I I I I ---—II I I I----訂，！ — — — — — (請先間讀背面之注意事項再成寫本頁) 463385 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（12 ) 建互包括自Ar ’ N2 ’ N2 : H2形成氣體，〇2，h2〇， 2〇 N〇 ’揉机及氧電漿所组成之族群中所選出之元素之 氛圍。步驟212係—產物，其中形成具高介電常數及良好 絕緣性質之薄膜。 '在本發明之—些方面，步驟202包括供自Zr&Hf所組成 之族群中所選出之金屬用之第一坩堝及供三價金屬用之第 二坩堝。然後，步驟206包括將第一坩堝加熱至溫度約 1000至2000T之範圍内，及將第二坩堝加熱至溫度約]〇〇〇 至2000 c之範圍内，3 Zr/Hf坩堝無需與三價金屬坩堝同一 溫度。 - 在本發明之一些方面，步驟210包括次步驟（未示出）。步 驟210a在包括氧之氛圍中及溫度約4〇〇至8〇〇1之範圍内退 火。步樣210b在包括自Ar，N2，N2 : H2形成氣體，〇2， Ηβ ’ NW，NO，無氣體及氧電漿所組成之族群中所選 出之元素之氛圍中及溫度約4〇〇至8〇〇之範圍内退火。 以上已揭示在相當高退火溫度下仍保持無晶形之高k介電 薄膜。因爲薄膜不會形成結晶結構，故相鄰薄膜之介面之 不規則性不多。當用作柵介電質時，薄膜可作成厚到可提 供栅電場偶合於溝道區所需之電容，而溝道區之表面蚋可 作成平滑到可支撐'高電子遷移率。薄膜係經由CVD，濺 鍍’或蒸發沉積方法而形成。精於本技藝之其他人士將會 想起本發明之其他變異及具體例。 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） --------------裝--------訂---------線 (請先閱讀背面之注意事項一^寫本頁)An Al / TiN upper electrode was deposited by sputtering and patterned to make a 10 x 100 " m2 capacitor for power supply testing. Figure 3 shows! 〇〇μm m) X 100 " m capacitor 63A Zr-Al-O thin film high frequency CV curve. The SiO 2 equivalent thickness measured from C V measurement is ~ 1,5 nm, which indicates that the dielectric constant of this film is ~ 16. Fig. 4 is an IV curve chart 'showing the leakage characteristics of the film of the present invention. The leakage current is only about 6 X 1CT5 A / cm2, which is much smaller than the Si02 thin film of the same thickness. A1 and Zr targets were co-sputtered with a power ratio of 1: 5 'in a mixture of oxygen and argon at room temperature to prepare Zr02 films doped with A1. Figure 5 shows the leakage characteristics after post-deposition annealing at about 400 to 500 ° C. This temperature is much lower than those required for other films, such as Ti02 film, which usually must be annealed above 750 ° C to reduce leakage. The thickness of the film was evaluated by spectral ellipsometry. FIG. 6 shows the high-frequency cv curves of three different thickness films of the present invention. mm film obtains the highest accumulated capacitance when the gate bias is -1.5 V 26 -10- This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) II ------ --- Order · -------- line (please read the note on the back first # 4 write this page) 4 ^ 3385 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8) At the level of 10,000 microns, at higher gate bias voltages, the gate leakage will increase c 'and the capacitance cannot be measured accurately. By extrapolation, the capacitance can be estimated to be about 28fF / + square micron when the gate voltage is -2V. This is equivalent to a typical dielectric thickness (CDT = Si02 / C) of about 1.2 nm. A quantum machine estimated to be% 〇q ® 约 is about 0.3 nm is included in the positive G ', which is less than 1 EOT of 0 nm. Fig. 7 shows the slight relationship between the effective dielectric constant of the film and the thickness of the film, which shows the existence of the smallest interface Si02 layer. Fig. 8 shows the IV curve of the film of Fig. 6. In terms of 3 nm. At -1 5γ, the leakage current of the handle is about 0.5A / cm2, and when the possible operating voltage is _v, it is about 0.1 A / cm2. Figure 9 shows that the leakage current on the η-type substrate is much larger than p The thickness of the thin film on the _ type substrate is about 10 times. The relationship between leakage and temperature is also large. This indicates that the conduction mechanism is most likely a Frenkd_p0ie type and an energy barrier for electron conduction. (Energy barrier) is much smaller than the hole conductor. The existence of electronic flavor is not surprising, because the dielectric film is made using sputtering technology. Figures 10 and I 1 show the reliability of the film of Figure 6. There is a charge plate in the film. When the time-dependent dielectric breakdown (TDDB) lifetime is below 1.3V, it can be extrapolated to more than 10 years. With Zr-Al-O gate The dielectric PM0S transistor system uses a nitride gate replacement method to process the lightly doped drain (LDD) and source / drain regions in the last gate day. (gate stack) is formed before fixing. The thickness of Zr-Al-O gate dielectric is about 6 nm, and the maximum C measured during accumulation is more than 20 fF / μm2. -11 This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) I I --- installed ----- r --- ordered ------ --- line (please read the precautions on the back to write this page) 463385 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (9) The research wood from the capacitor film of the present invention is the same "—- 05- i1% xh Ά For gate dielectrics, storage capacitors are also suitable for ferroelectric memory. Nitride Body (1T) Figures 12 and 13 show the steps of completing a MOSFET transistor using the metal oxide thin film A1 doped with A1 of the present invention. Wu Zhi Shi Ge Ling r Shi L _ 1 Z * •. Bei does not have a channel region 5 2 and the channel region has an upper surface 54 of the transistor ^ ^ ^ film 56.-0. The channel region 52 is a gate Dielectric Figure 13 shows the thumb dielectric film sandwiched between the gate electrode 58 and the epicenter on the channel region. The gate dielectric film has a higher dielectric constant than dioxygen and includes self-zirconium (Zr) and The metal and oxygen selected from the group consisting of Hf. The gate dielectric film 56 includes the trivalent metal selected from the group consisting of Ziming (A1), Hang (Sc) and Gang (La). The percentage of A1 or other trivalent metals in 56 is in the range of about 0 to 50%. The percentage of A1 in thin film 56 is preferably about 25%. The thickness of gate dielectric thin film 56 is 60 (Fig. 1 3) is in the range of about 20 to 200 A. The dielectric constant of the gate dielectric film 56 is in the range of about 10 to 25. In some aspects of the invention, the 'transistor 50 includes a crystal having a thickness of 64 An interface insulating layer 62 in a range of about 2 to 5A and sandwiched between the channel region 52 and the gate dielectric film 56. The interface insulating layer 62 is made of self-nitride and oxynitride; Composition of the group The selected material is used to make the upper surface of the channel region 54 smoother to improve the electron mobility of the MOSFET 50. In the case of the gate dielectric of a large CMOS device, the chip uses any best practice Known methods such as isolation processing, followed by the formation of P-wells and N-wells to expose the channel region. Ultra-thin oxide barriers may still be required. Here -12 This paper applies Chinese National Standard (CNS) A4 Specification (210 x 297 mm)-—1 — — — > III l · II] ^ «— — — I — — — — (Please read the notes on the back first to write this page) 4 633 85 Intellectual Property of the Ministry of Economic Affairs In the case of consumer cooperation of the Bureau, Du printed A7. 5. Description of the Invention (1ί)) In the case, possible barrier layers include silicon nitride and silicon oxynitride. Then, high-k dielectrics are deposited. There are several ways to prepare the film: A _Co-sputter zr and a 1 in inert or oxidizing surroundings; B 'Co-pulse compound targets in inert or oxidizing surroundings, such as zr _ a 1; C · Chemical vapor deposition Zr-Al-O and Hf-Al_ 〇; or D. Evaporate., After deposition, the film is inert (for example, Ar ,, n2: H2 forms a gas) and / or oxidizing property (〇2, H2〇 'Ν2〇, NO), and annealed in a gas-free surrounding atmosphere and at a life temperature (400-900 ° C) to control high-k films and high-k / S 1 interface. However, if the thin film is deposited by evaporation, the annealing process generally includes oxygen to include oxygen in the alloy thin film. After annealing, the gate is deposited and a gate stack pattern is formed. The gate material can be metal or polysilicon. The device is then completed using any optimal device fabrication process, using conventional methods, or using gate replacement methods using nitride, polysilicon, or polysiGe dummy gates. Fig. 14 is a flowchart showing the steps of a CVD method for forming a doped metal oxide film of the present invention. Step 100 provides an integrated circuit (1C) with a surface. Step 102 prepares at least one precursor, which includes a metal and a trivalent metal selected from the group consisting of ~ and Hf. Step ι02 includes the trivalent metal selected from the group consisting of the inscription (A1), sharp (Sc), and lanthanum (La). In some aspects of the invention, step 102 includes a first precursor including a metal selected from the group consisting of H and Hf and a second precursor including a trivalent metal t. Step 104 includes evaporating the at least one precursor. Step 106 establishes an atmosphere including oxygen. Generally speaking, step 106 includes containing argon-13- this paper size is applicable to Chinese national standards (CNSW specification (210 X 297 mm) --------------------- Order —-------- < Please read the notes on the back before writing 4 copies I) 463385 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (11) (A0 atmosphere The ratio of 〇2 to Ar is in the range of about 5 to 25%, and the pressure is in the range of about 1 to 10T. Step 108 decomposes the 1 (: precursor on the surface to deposit by chemical vapor (C (VD) method deposits a metal, trivalent metal, and oxygen alloy thin film selected from the group consisting of ζ Γ and H f. Step 110 is performed at a temperature of about 400 to 800. (: annealing in the fan garden. Step i 10 Including the establishment of an atmosphere including elements selected from the group consisting of Ar, N2, N2: H2 forming gas, 〇2, h20, NzO'NO, airless and oxygen plasma. Step 112 is a product, wherein the formation Thin film with high dielectric constant and good insulation properties. In some aspects of the present invention, step 100 provides a silicon 1C surface, and additional steps are provided before step 108. Step 106. The IC silicon surface temperature is established in the range of about 300 to 500 ° C. Figure 15 is a flowchart showing the steps of an evaporation method for forming a doped metal oxide film. Step 200 provides An integrated circuit (1C) with a silicon surface. Step 202 prepares at least one crucible including a metal selected from the group consisting of zr and Hf and a trivalent metal. Step 202 includes aluminum (A1), sharp (S c ) And lanthanum (La) selected trivalent metals. Step 204 establishes a hollow (gas-free) atmosphere garden. Step 206 heats the at least one crucible to a temperature of about 1000 to 2000 ° C. Within the range, the metal prepared in step 202 is evaporated. In step 208, in response to steps 202 to 206, an alloy thin film including a metal selected from the group consisting of Zr and Hf and a trivalent metal is deposited. Annealed in an atmosphere and a temperature range of about 400 to 800 ° C to form an alloy thin film including a metal selected from the group consisting of Zr and Hf, a trivalent metal and oxygen. Step 210 includes • 14- 本Paper size applies to national standards (CNS) A4 specifications (210 x 297 mm) --- IIII ----- II II I ---- Order ,! — — — — — (Please read the notes on the back before writing this page) 463385 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (12) The construction of the mutual includes the formation of gas from Ar 'N2' N2: H2, 〇2, h2〇, 2〇N〇 'kneading machine and oxygen The atmosphere of the selected elements in the group of pulp. Step 212 is a product in which a thin film having a high dielectric constant and good insulation properties is formed. 'In aspects of the invention, step 202 includes a first crucible for a metal selected from the group consisting of Zr & Hf and a second crucible for a trivalent metal. Then, step 206 includes heating the first crucible to a temperature ranging from about 1000 to 2000 T, and heating the second crucible to a temperature ranging from about 1000 to 2000 c. The 3 Zr / Hf crucible does not need to be mixed with a trivalent metal. Crucible at the same temperature. -In some aspects of the invention, step 210 includes a secondary step (not shown). Step 210a is annealed in an atmosphere including oxygen and at a temperature in the range of about 4,000 to 8000. Step 210b is in an atmosphere including an element selected from the group consisting of Ar, N2, N2: H2 forming gas, 〇2, Ηβ 'NW, NO, no gas, and oxygen plasma, and the temperature is about 400 to Anneal in the range of 800. The foregoing has revealed high-k dielectric films that remain amorphous at relatively high annealing temperatures. Because the film does not form a crystalline structure, the interface of adjacent films has few irregularities. When used as a gate dielectric, the thin film can be made thick enough to provide the capacitance required for the gate field to couple to the channel region, and the surface of the channel region can be made smooth to support 'high electron mobility. The thin film is formed by a CVD, sputtering ', or evaporation deposition method. Others skilled in the art will remember other variations and specific examples of the invention. -15- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 meals) -------------- Installation -------- Order ---- ----- line (please read the note on the back first ^ write this page)

Claims (1)

463385 A8 B8 C8 D8 六、申請專利範圍 1. 一種相對於二氧化矽具有較高介電常數之薄膜，其包 含： - 三價金屬·， 自锆（Zr)及給（Hf)所组成之族群中所選出之金屬，及 氧’精以形成典晶形南介電薄膜。 ’ 2. 如申請專利範圍第1項之薄膜，其中該三價金屬係自鋁 (A1)，銳（Sc)及鑭（La)所组成之族群中所選出。 3. 如申請專利範圍第1項之薄膜，其中薄膜之厚度係在約 20至200 A之範園内。 4. 如申請專利範圍第1項之薄膜，其中薄膜之介電常數係 在10至25之範圍内。 5. 如申請專利範圍第i項之薄膜，其中薄膜中之a丨之百分 比爲不超過約5 0 %。 6，如申請專利範圍第5項之薄膜，其中薄膜中之A1之百分 比爲約2 5 %。 7. —種MOSFET電晶體，其包含： ’ » 柵電極； 在該柵電極下方具有上表面之溝道區；及 夾置於該柵電極與該溝道區上表面中間，具有相對於 二氧化矽較高介電常數，包括自結（Zr)及铪（Hf)所组成 之族群中所選出之金屬，及包括氧之柵介電薄膜。 8. 如中請專利範圍第7項之電晶體，其中該柵介電薄膜包 括自鋁（A1)，航（Sc)及鑭（La)所組成之族群中所選出之 三價金屬。 -16- ‘ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------裝—— (請先閱讀背面之注意事項一^寫本頁) 訂： 線- 經濟部智慧財產局員工消費合作杜印製 888QP ABCD 463385 六、申請專利範圍 9.如申請專利範圍第8項之電晶體，其中薄膜中之4 1之百 分比係在約〇至5 〇 %之範園内》 10·如申請專利範圍第9項之電晶體，其中薄膜中之A 1之百 分比為約2 5 %。 11.如申請專利範圍第7項之電晶體，其中該柵介電薄膜之 厚度係在約2 0至2〇〇A之範圍内。 12·如申請專利範圍第7項之電晶體，其中該柵介電薄膜之 介電常數係在約1 〇至2 5之範圍内。 13. 如申請專利範圍第7項之電晶體，進一步包含： 具厚度在约2至5A之範圍内且夾置於該溝道區與該柵 介電薄膜中間之介面絕緣層，該介面絕緣層包括自氮化 砂及氧氮化矽所組成之族群中所選出之材料，而致該溝 道區上表面較為平滑而提高MOSFET之電子遷移率。 14. 一種在製作具有表面之集成電路（IC)時在ic表面上形成 摻雜A1之金屬氧化物薄膜之方法，包含下列步驟： a) 建立包括氧之氛圍； b) 在1C矽表面上濺鍍至少一種包括自ZriHf所組成之 族群中所選出之金屬，及包括三價金屬之目標金屬； c) 回應步驟a)及b)，形成摻雜A1之金屬氧化物薄膜；及 d) 在溫度約400至800 °C之範圍内退火，藉以形成具有 高介電常數及良好絕緣性質之薄膜。 15. 如申請專利範圍第1 4項之方法，其中提供紗I c表面，及 在步驟c )之前包含以下另外步驟： b [)建il在約室溫至约400 t：範園内之I c矽表面溫度。 -17- 本紙張尺&遇用中國國家標準（CJsJS)A4規格（210x 297公釐） — — — — — — — — — — —----I--- I I 訂·--— II-- (請先間讀背面之注意事項寫本頁) 經濟部智慧財產局員工消費合卞 經濟部智慧財產局員工消費合作社印製 4633 85 A8 驾 __________D8 六、申請專利範圍 16. 如申&專利範圍第Μ項之方法，其中步驟a)包括包含氬 (Ar)(氛圍，其中心與^之比係在約5至Μ%支範圍 内’及其中壓力係在約1至1〇毫拖爾（πιΤ)之範圍内。 17. 如申請專利範圍第14項之方法，其中步驟d)包括建立.包 括自 Ar ’ N2，N2 : h2 形成氣體，〇2，H20，n2〇， N〇 ’無氣體及氧電漿所组成之族群中所選出之元素之氛 圍。 18. 如申請專利範圍第i 4項之方法，其中步驟b)包括自鋁 (A1) ’銃（Sc)及鑭（La)所組成之族群中所選出之三價金 屬。 19. 如申請專利範圍第1 4項之方法，其中步驟b)包括以包括 自Zr及Hf所組成之族群中所選出之金屬之第—目標及包 括三價金屬之第二目檩之個別目標共濺鍍。 20- —種在製作具有表面之集成電路（iC)時形成摻雜幻之金 屬氧化物薄膜之方，法，其包括下列步驟： ‘ a) 製備至少一種包括自Zr及Hf所组成之族群中所選出 之金屬及三價金屬之前驅物； b) 將該至少一種前驅物蒸發； c) 建立包括氧之氛圍； d) 將1C表面上之前驅物分解，以藉由化學蒸氣沉積 (C VD)法沉積包括自Z r及H f所组成之族群中所選出之金 屬，三價金屬及氧之含金薄膜；及 e) 在溫度約400至800°C範圍内退火，藉以形成具有高 介電常數及良好絕緣性質之薄膜。 -18- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 <請先閱讀背面之注意事項tinjf寫本頁) 經濟部智慧財產局員工消費合作社印製 4633 8 5 A8 § —__________D8 六、申請專利範圍 21.如中请專利範圍第2〇項之方法，其中提供矽IC表面，及 在步驟d)之前包括以下另外步驟： - ci)將1C矽表面溫度建立在約之範圍内。 21如中請專利範圍第2〇項之方法，其中步驟c)包括包含氬 (Ar)心氛圍’其中化與^之比係在約5至η%之範圍 内，及其中壓力係在約i至j 〇拖爾（τ)之範圍内。. 23. 如申請專利範圍第2〇項之方法，其中步驟〇包括建立包 括自 Ar ’ N2 ’ N2 : H2 形成氣體，〇2，h20，N20， NO，無氣體及氧電漿所組成之族群中所選出之元素之氛 圍。 24. 如申請專利範圍第2〇項之方法，其中步驟㈧包括自鋁 (A1) ’叙（Sc)及鑭（La)所組成之族群中所選出之三價金 屬。 25. 如申請專利範圍第2〇項之方法，其中步驟幻包含包括自 Zr及Hf所纽成之族群中所選出之金屬之第一前驅物及其 中步驟a)包含包括三價金屬之第二前驅物。 . 26. —種在製作具有矽表面之集成電路（IC)時形成摻雜μ之 金屬軋化物薄膜之方法，其包含下列步驟： a) 製備至少一種包括自Zr&Hfm組成之族群中所選出 之金屬及三價金屬之坩堝； b) 建立眞空氛圍； c) 將該至少一個坩堝加熱至坩堝溫度在約1〇〇〇至2〇〇〇 c之範圍内，以蒸發步驟（a)製備之金屬； <1)回應步骤a)至c)，沉積包括自^^及只^所組成之族群 -19 - 本紙張尺糾肖巾國國家標準（CNS)A4規格（210 X 297公爱了 -------------裝--------訂--------線 (請先閱讀背面之注意事項^1#寫本頁) A8B8C8D8 4 633 85 六、申請專利範圍 中所選出之金屬及三價金屬之合金薄膜；及 e )在包括氧之氛園中及溫度在約400 _ 8〇〇 X：之―範園内 退火以形成包括自Zr及Hf所组成之族群中所遽出之金 屬’三價金屬及氧之合金薄膜，藉以形成具宥高介電常 數及良好絕緣性質之薄膜。 27. 如申請專利範圍第2 6項之方法，其中步驟a)包括供自Z r 及Hf所组成之族群中所選出之金屬用之第一坩堝，及供 三價金屬用之第二坩堝，及其中步驟〇包括將第一坩塢 加熱至溫度在約1000與2000°C之範圍内，及將第二坩蜗 加熱至溫度在約1000至2000°C之範圍内。 _ 28. 如申請專利範圍第2 6項之方法，其中步驟e )包括建立包 括自 Ar，N2，N2 : H2 形成氣體，〇2，h2〇，n2〇，N〇 ’無氣體及氧電漿所組成之族群中所選出之元素之氛園。 29. 如申請專利範圍第28項之方法’其中步驟e)包括次步聲 如下： ’ 在包括氧之氛圍中及溫度在約400至8〇〇。(：之範園内 退火；及 e2)在包括自Ar，N2 ’ N2 : H2形成氣體，， hO，MW，NO，無氣體及氧電漿所組成之族群^所 選出之元素之氛圍中及溫度在約400至8〇〇。(：之範圍内、< 火。· ‘退 30. 如申請專利範圍第26項之方法，其中步驟a)包括自 (A1) ’銳（S c)及鑭（L a)所組成之族群中所選出3 φ ,印心二ΐ貝金 20· 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 展--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製463385 A8 B8 C8 D8 6. Scope of patent application 1. A thin film with a high dielectric constant relative to silicon dioxide, which includes:-Trivalent metal, a group consisting of zirconium (Zr) and Hf The selected metal and oxygen are refined to form a typical crystalline southern dielectric film. ′ 2. The thin film according to item 1 of the patent application scope, wherein the trivalent metal is selected from the group consisting of aluminum (A1), sharp (Sc) and lanthanum (La). 3. For example, the thin film of the first patent application range, wherein the thickness of the thin film is within the range of about 20 to 200 A. 4. For the thin film of the first patent application, the dielectric constant of the thin film is in the range of 10 to 25. 5. As for the thin film of scope i of the patent application, the percentage of a 丨 in the thin film is not more than about 50%. 6. The thin film of claim 5 in which the percentage of A1 in the thin film is about 25%. 7. A MOSFET transistor, comprising: '»a gate electrode; a channel region having an upper surface below the gate electrode; and interposed between the gate electrode and the upper surface of the channel region, and having a relative to dioxide The higher dielectric constant of silicon includes metals selected from the group consisting of self-junctions (Zr) and hafnium (Hf), and gate dielectric films including oxygen. 8. The transistor according to item 7 of the patent application, wherein the gate dielectric film includes a trivalent metal selected from the group consisting of aluminum (A1), aviation (Sc), and lanthanum (La). -16- 'This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) --------------- Packing-(Please read the note 1 on the back first ^ Write this page) Order: Line-Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 888QP ABCD 463385 VI. Patent Application Scope 9. For the transistor in the 8th scope of the patent application, the percentage of 41 in the film is Within the range of about 0 to 50% of the range "10. The transistor of item 9 of the patent application scope, wherein the percentage of A 1 in the thin film is about 25%. 11. The transistor as claimed in claim 7 in which the thickness of the gate dielectric film is in the range of about 20 to 2000A. 12. The transistor as claimed in claim 7 in which the dielectric constant of the gate dielectric film is in the range of about 10 to 25. 13. The transistor as claimed in item 7 of the patent application scope, further comprising: an interface insulating layer having a thickness in the range of about 2 to 5A and sandwiched between the channel region and the gate dielectric film, and the interface insulating layer It includes materials selected from the group consisting of sand nitride and silicon oxynitride, so that the upper surface of the channel region is smoother and the electron mobility of the MOSFET is improved. 14. A method for forming an A1-doped metal oxide film on an ic surface when fabricating an integrated circuit (IC) having a surface, comprising the following steps: a) establishing an atmosphere including oxygen; b) sputtering on a 1C silicon surface Plating at least one metal selected from the group consisting of ZriHf and a target metal including a trivalent metal; c) responding to steps a) and b) to form a metal oxide film doped with A1; and d) at temperature Annealing in the range of about 400 to 800 ° C, to form a thin film with high dielectric constant and good insulation properties. 15. The method according to item 14 of the scope of patent application, wherein the surface of the yarn I c is provided, and the following additional steps are included before step c): b [) built at about room temperature to about 400 t: I c in the fan garden Silicon surface temperature. -17- This paper rule & used the Chinese National Standard (CJsJS) A4 specification (210x 297 mm) — — — — — — — — — — — — — — — II Order II --- II -(Please read the notes on the back first to write this page) Consumption of Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 4633 85 A8 Driving __________D8 6. Application for Patent Scope 16. Such as applying & amp The method of item M of the patent scope, wherein step a) comprises argon (Ar) (atmosphere, the ratio of the center of which is in the range of about 5 to M% branch) and its medium pressure is about 1 to 10 millimeter Within the scope of Tuer (πιΤ). 17. The method of the scope of application for patent No. 14, wherein step d) includes the establishment. Including gas formation from Ar 'N2, N2: h2, 〇2, H20, n2〇, N〇. 'The atmosphere of selected elements in a group of gas and oxygen plasma. 18. The method according to item i 4 of the scope of patent application, wherein step b) includes a trivalent metal selected from the group consisting of aluminum (A1) '铳 (Sc) and lanthanum (La). 19. The method as claimed in item 14 of the scope of patent application, wherein step b) includes individual targets including a first target including a metal selected from the group consisting of Zr and Hf and a second target including a trivalent metal Total sputtering. 20-—A method for forming a doped metal oxide thin film when fabricating an integrated circuit (iC) with a surface, which includes the following steps: 'a) preparing at least one group consisting of Zr and Hf Selected metal and trivalent metal precursors; b) evaporating the at least one precursor; c) establishing an atmosphere including oxygen; d) decomposing the precursors on the 1C surface for chemical vapor deposition (C VD ) Method includes metal selected from the group consisting of Z r and H f, gold-containing thin films of trivalent metal and oxygen; and e) annealing at a temperature of about 400 to 800 ° C, thereby forming a high-level dielectric Film with a constant electric capacity and good insulation properties. -18- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation -------- Order ----- ---- line < Please read the note on the back of tinjf first to write this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 4633 8 5 A8 § —__________ D8 VI. Scope of patent application 21. If so, please apply for patent scope No. 2 The method of item 0, wherein the silicon IC surface is provided, and before step d), the following additional steps are included:-ci) the 1C silicon surface temperature is established within a range of about. 21 The method of claim 20, wherein step c) includes an argon (Ar) core atmosphere, wherein the ratio of 化 to ^ is in the range of about 5 to η%, and the medium pressure is in the range of about i. Within the range of j 拖 Torr (τ). 23. The method of claim 20 in the scope of patent application, wherein step 0 includes establishing a group consisting of a gas formed from Ar 'N2' N2: H2, 02, h20, N20, NO, no gas and oxygen plasma. The atmosphere of the selected elements. 24. The method of claim 20, wherein step ㈧ includes a trivalent metal selected from the group consisting of aluminum (A1) '(Sc) and lanthanum (La). 25. The method of claim 20, wherein the step includes a first precursor including a metal selected from the group formed by Zr and Hf and step a) includes a second including a trivalent metal. Precursor. 26. — A method of forming a μ-doped metal rolling compound film when fabricating an integrated circuit (IC) having a silicon surface, comprising the following steps: a) preparing at least one selected from the group consisting of Zr & Hfm Crucibles of metals and trivalent metals; b) establishing an empty atmosphere; c) heating the at least one crucible to a crucible temperature in the range of about 1000 to 2000c, and evaporating the prepared in step (a) Metal; < 1) Responding to steps a) to c), the deposit includes the group consisting of ^^ and ^ -19-National Paper Standard (CNS) A4 (210 X 297) ------------- Installation -------- Order -------- Line (Please read the precautions on the back first ^ 1 # Write this page) A8B8C8D8 4 633 85 VI. Alloy thin films of metals and trivalent metals selected in the scope of patent applications; and e) in an atmosphere garden including oxygen and at a temperature of about 400 _ 800X: of-annealing in the fan garden to form Zr And trivalent metal and oxygen alloy thin film out of the group composed of Hf and Hf to form a thin film with high dielectric constant and good insulation properties27. The method of claim 26, wherein step a) includes a first crucible for a metal selected from the group consisting of Z r and Hf, and a second crucible for a trivalent metal, And step 0 therein includes heating the first crucible to a temperature in a range of about 1000 to 2000 ° C, and heating the second crucible to a temperature in a range of about 1000 to 2000 ° C. _ 28. The method according to item 26 of the scope of patent application, wherein step e) includes establishing a gas including argon, N2, N2 and H2, 〇2, h2〇, n2〇, No ′ plasma and oxygen-free plasma. A garden of selected elements in the group of people. 29. The method according to item 28 of the scope of patent application, wherein step e) includes a substep sound as follows: ′ In an atmosphere including oxygen and at a temperature of about 400 to 800. (: Annealing in the range garden; and e2) in the atmosphere and temperature of the group consisting of the gas formed from Ar, N2 'N2: H2, hO, MW, NO, no gas and oxygen plasma ^ selected elements At about 400 to 800. (Within the range, < Fire. · 'Retreat 30. The method of item 26 of the patent application, wherein step a) includes a group consisting of (A1)' sharp (S c) and lanthanum (L a) Among the selected 3 φ, the incisive diobi gold 20 · This paper size is applicable to the Chinese national standard (CNS > A4 size (210 X 297 mm)) Exhibition -------- Order ------- --Line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
TW089114476A 1999-07-19 2000-07-18 Aluminum-doped zirconium dielectric film transistor structure and deposition method for same TW463385B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/356,470 US6060755A (en) 1999-07-19 1999-07-19 Aluminum-doped zirconium dielectric film transistor structure and deposition method for same

Publications (1)

Publication Number Publication Date
TW463385B true TW463385B (en) 2001-11-11

Family

ID=23401555

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089114476A TW463385B (en) 1999-07-19 2000-07-18 Aluminum-doped zirconium dielectric film transistor structure and deposition method for same

Country Status (4)

Country Link
US (2) US6060755A (en)
JP (1) JP3703373B2 (en)
KR (1) KR100342316B1 (en)
TW (1) TW463385B (en)

Families Citing this family (165)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6048769A (en) * 1997-02-28 2000-04-11 Intel Corporation CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers
KR100455737B1 (en) * 1998-12-30 2005-04-19 주식회사 하이닉스반도체 Gate oxide film formation method of semiconductor device
US6235594B1 (en) * 1999-01-13 2001-05-22 Agere Systems Guardian Corp. Methods of fabricating an integrated circuit device with composite oxide dielectric
JP3417866B2 (en) * 1999-03-11 2003-06-16 株式会社東芝 Semiconductor device and manufacturing method thereof
US6297539B1 (en) * 1999-07-19 2001-10-02 Sharp Laboratories Of America, Inc. Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
FI117979B (en) * 2000-04-14 2007-05-15 Asm Int Process for making oxide thin films
US6184072B1 (en) * 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
US6444512B1 (en) * 2000-06-12 2002-09-03 Motorola, Inc. Dual metal gate transistors for CMOS process
JP2004501857A (en) * 2000-06-26 2004-01-22 ノース・キャロライナ・ステイト・ユニヴァーシティ Novel amorphous oxides for use in microelectronics, optics and other applications
KR100545706B1 (en) * 2000-06-28 2006-01-24 주식회사 하이닉스반도체 Semiconductor device manufacturing method
US6943078B1 (en) * 2000-08-31 2005-09-13 Micron Technology, Inc. Method and structure for reducing leakage current in capacitors
KR100814980B1 (en) 2000-09-28 2008-03-18 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 Vapor deposition of oxides, silicates, and phosphates
US6486080B2 (en) * 2000-11-30 2002-11-26 Chartered Semiconductor Manufacturing Ltd. Method to form zirconium oxide and hafnium oxide for high dielectric constant materials
US6602805B2 (en) * 2000-12-14 2003-08-05 Macronix International Co., Ltd. Method for forming gate dielectric layer in NROM
US20020102797A1 (en) * 2001-02-01 2002-08-01 Muller David A. Composite gate dielectric layer
US6844604B2 (en) * 2001-02-02 2005-01-18 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US7371633B2 (en) * 2001-02-02 2008-05-13 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
JP3732098B2 (en) 2001-02-19 2006-01-05 株式会社ルネサステクノロジ Semiconductor device
US6541280B2 (en) 2001-03-20 2003-04-01 Motorola, Inc. High K dielectric film
EP1256638B1 (en) * 2001-05-07 2008-03-26 Samsung Electronics Co., Ltd. Method of forming a multi-components thin film
US7358578B2 (en) * 2001-05-22 2008-04-15 Renesas Technology Corporation Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring
US7037862B2 (en) * 2001-06-13 2006-05-02 Micron Technology, Inc. Dielectric layer forming method and devices formed therewith
US6642131B2 (en) * 2001-06-21 2003-11-04 Matsushita Electric Industrial Co., Ltd. Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film
JP2003017687A (en) * 2001-06-29 2003-01-17 Hitachi Ltd Semiconductor device
KR100411306B1 (en) * 2001-06-30 2003-12-18 주식회사 하이닉스반도체 Method for fabricating semiconductor device with hydrogen barrier
JP5073136B2 (en) * 2001-08-24 2012-11-14 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2003069013A (en) 2001-08-29 2003-03-07 Hitachi Ltd Semiconductor device and method of manufacturing the same
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US6844203B2 (en) * 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US6806145B2 (en) * 2001-08-31 2004-10-19 Asm International, N.V. Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
KR100646296B1 (en) * 2001-09-12 2006-11-23 닛본 덴끼 가부시끼가이샤 Semiconductor device and production method therefor
US6472337B1 (en) * 2001-10-30 2002-10-29 Sharp Laboratories Of America, Inc. Precursors for zirconium and hafnium oxide thin film deposition
US6743681B2 (en) * 2001-11-09 2004-06-01 Micron Technology, Inc. Methods of Fabricating Gate and Storage Dielectric Stacks having Silicon-Rich-Nitride
US6667246B2 (en) * 2001-12-04 2003-12-23 Matsushita Electric Industrial Co., Ltd. Wet-etching method and method for manufacturing semiconductor device
US6953730B2 (en) 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
EP1324393B1 (en) * 2001-12-28 2008-04-09 STMicroelectronics S.r.l. Manufacturing process of a semiconductor non-volatile memory cell and corresponding memory-cell
US6563183B1 (en) * 2001-12-31 2003-05-13 Advanced Micro Devices, Inc. Gate array with multiple dielectric properties and method for forming same
US6894355B1 (en) * 2002-01-11 2005-05-17 Advanced Micro Devices, Inc. Semiconductor device with silicide source/drain and high-K dielectric
US6767795B2 (en) 2002-01-17 2004-07-27 Micron Technology, Inc. Highly reliable amorphous high-k gate dielectric ZrOXNY
US6893984B2 (en) * 2002-02-20 2005-05-17 Micron Technology Inc. Evaporated LaA1O3 films for gate dielectrics
US7323422B2 (en) * 2002-03-05 2008-01-29 Asm International N.V. Dielectric layers and methods of forming the same
US6812100B2 (en) * 2002-03-13 2004-11-02 Micron Technology, Inc. Evaporation of Y-Si-O films for medium-k dielectrics
US6846516B2 (en) * 2002-04-08 2005-01-25 Applied Materials, Inc. Multiple precursor cyclical deposition system
US7087480B1 (en) * 2002-04-18 2006-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Process to make high-k transistor dielectrics
US7045430B2 (en) 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US6642066B1 (en) * 2002-05-15 2003-11-04 Advanced Micro Devices, Inc. Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer
CA2386380A1 (en) * 2002-05-27 2003-11-27 Mohammed Saad Heavy metal oxide thin film, active and passive planar waveguides and optical devices
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7135421B2 (en) * 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
JP4614639B2 (en) * 2002-06-10 2011-01-19 アイメック Enhancement of dielectric constant (k value) of Hf-containing composition
US7067439B2 (en) * 2002-06-14 2006-06-27 Applied Materials, Inc. ALD metal oxide deposition process using direct oxidation
US6858547B2 (en) * 2002-06-14 2005-02-22 Applied Materials, Inc. System and method for forming a gate dielectric
US20030232501A1 (en) * 2002-06-14 2003-12-18 Kher Shreyas S. Surface pre-treatment for enhancement of nucleation of high dielectric constant materials
US7326988B2 (en) * 2002-07-02 2008-02-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
JP2004047503A (en) * 2002-07-08 2004-02-12 Fujitsu Ltd Semiconductor device and its manufacturing method
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US6915592B2 (en) * 2002-07-29 2005-07-12 Applied Materials, Inc. Method and apparatus for generating gas to a processing chamber
US6921702B2 (en) * 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6919251B2 (en) * 2002-07-31 2005-07-19 Texas Instruments Incorporated Gate dielectric and method
US20040105244A1 (en) * 2002-08-06 2004-06-03 Ilyas Mohammed Lead assemblies with offset portions and microelectronic assemblies with leads having offset portions
US6884739B2 (en) * 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
CN100423266C (en) * 2002-08-20 2008-10-01 独立行政法人产业技术综合研究所 Semiconductor ferroelectric storage device and its manufacturing technics
JP4887481B2 (en) * 2002-08-20 2012-02-29 独立行政法人産業技術総合研究所 Semiconductor ferroelectric memory device
JP5019297B2 (en) * 2002-08-20 2012-09-05 独立行政法人産業技術総合研究所 Manufacturing method of semiconductor ferroelectric memory device
US7041609B2 (en) * 2002-08-28 2006-05-09 Micron Technology, Inc. Systems and methods for forming metal oxides using alcohols
US6958300B2 (en) 2002-08-28 2005-10-25 Micron Technology, Inc. Systems and methods for forming metal oxides using metal organo-amines and metal organo-oxides
US7112485B2 (en) 2002-08-28 2006-09-26 Micron Technology, Inc. Systems and methods for forming zirconium and/or hafnium-containing layers
US7084078B2 (en) * 2002-08-29 2006-08-01 Micron Technology, Inc. Atomic layer deposited lanthanide doped TiOx dielectric films
JP3773475B2 (en) * 2002-09-06 2006-05-10 株式会社日立製作所 Semiconductor device
US6905737B2 (en) * 2002-10-11 2005-06-14 Applied Materials, Inc. Method of delivering activated species for rapid cyclical deposition
US6713358B1 (en) * 2002-11-05 2004-03-30 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6982230B2 (en) * 2002-11-08 2006-01-03 International Business Machines Corporation Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US6958302B2 (en) * 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US6753224B1 (en) 2002-12-19 2004-06-22 Taiwan Semiconductor Manufacturing Company Layer of high-k inter-poly dielectric
JP2004214366A (en) * 2002-12-27 2004-07-29 Nec Electronics Corp Semiconductor device and its fabricating process
JP4290421B2 (en) 2002-12-27 2009-07-08 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6762114B1 (en) * 2002-12-31 2004-07-13 Texas Instruments Incorporated Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness
US6828200B2 (en) * 2003-01-03 2004-12-07 Texas Instruments Incorporated Multistage deposition that incorporates nitrogen via an intermediate step
JP2004241612A (en) * 2003-02-06 2004-08-26 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2004247341A (en) * 2003-02-10 2004-09-02 Renesas Technology Corp Semiconductor device
US20040168627A1 (en) * 2003-02-27 2004-09-02 Sharp Laboratories Of America, Inc. Atomic layer deposition of oxide film
US6930059B2 (en) * 2003-02-27 2005-08-16 Sharp Laboratories Of America, Inc. Method for depositing a nanolaminate film by atomic layer deposition
US7192892B2 (en) * 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
EP1602745B1 (en) * 2003-03-07 2010-10-27 Nippon Mining & Metals Co., Ltd. Hafnium alloy target and process for producing the same
US6716707B1 (en) * 2003-03-11 2004-04-06 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP4051063B2 (en) * 2003-03-13 2008-02-20 富士通株式会社 Manufacturing method of semiconductor device
AU2003221174A1 (en) * 2003-03-20 2004-10-11 Fujitsu Limited Semiconductor device having high dielectric film neutralizing fixed charge
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US20040198069A1 (en) * 2003-04-04 2004-10-07 Applied Materials, Inc. Method for hafnium nitride deposition
US7183186B2 (en) * 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
US20040232408A1 (en) * 2003-05-21 2004-11-25 Heeger Alan J. Bilayer high dielectric constant gate insulator
US7192824B2 (en) * 2003-06-24 2007-03-20 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
US7049192B2 (en) * 2003-06-24 2006-05-23 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectrics
US20050124121A1 (en) * 2003-12-09 2005-06-09 Rotondaro Antonio L. Anneal of high-k dielectric using NH3 and an oxidizer
US7351626B2 (en) 2003-12-18 2008-04-01 Texas Instruments Incorporated Method for controlling defects in gate dielectrics
KR100639673B1 (en) * 2003-12-22 2006-10-30 삼성전자주식회사 Semiconductor device including a gate dielectric layer formed of a high dielectric alloy and method of fabricating the same
US7005333B2 (en) * 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US7002224B2 (en) * 2004-02-03 2006-02-21 Infineon Technologies Ag Transistor with doped gate dielectric
US20050233477A1 (en) * 2004-03-05 2005-10-20 Tokyo Electron Limited Substrate processing apparatus, substrate processing method, and program for implementing the method
US20080217678A1 (en) * 2004-03-11 2008-09-11 National University Of Singapore Memory Gate Stack Structure
US7094671B2 (en) * 2004-03-22 2006-08-22 Infineon Technologies Ag Transistor with shallow germanium implantation region in channel
US20050252449A1 (en) 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US8323754B2 (en) 2004-05-21 2012-12-04 Applied Materials, Inc. Stabilization of high-k dielectric materials
US20060062917A1 (en) * 2004-05-21 2006-03-23 Shankar Muthukrishnan Vapor deposition of hafnium silicate materials with tris(dimethylamino)silane
US7141857B2 (en) * 2004-06-30 2006-11-28 Freescale Semiconductor, Inc. Semiconductor structures and methods of fabricating semiconductor structures comprising hafnium oxide modified with lanthanum, a lanthanide-series metal, or a combination thereof
US7601649B2 (en) 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7494939B2 (en) * 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
US7588988B2 (en) 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7106088B2 (en) * 2005-01-10 2006-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of predicting high-k semiconductor device lifetime
JP4185057B2 (en) 2005-01-28 2008-11-19 富士通株式会社 Manufacturing method of semiconductor device
US7374964B2 (en) 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7390756B2 (en) 2005-04-28 2008-06-24 Micron Technology, Inc. Atomic layer deposited zirconium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7572695B2 (en) 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
KR100644724B1 (en) * 2005-07-26 2006-11-14 삼성전자주식회사 Semiconductor device and method of manufacturing the same
US7402534B2 (en) 2005-08-26 2008-07-22 Applied Materials, Inc. Pretreatment processes within a batch ALD reactor
JP2006140514A (en) * 2005-12-19 2006-06-01 Fujitsu Ltd Semiconductor device and its manufacturing method
WO2007091302A1 (en) * 2006-02-07 2007-08-16 Fujitsu Limited Semiconductor device and process for producing the same
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) * 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
JP4965878B2 (en) * 2006-03-24 2012-07-04 株式会社東芝 Nonvolatile semiconductor memory device
JP5284081B2 (en) * 2006-03-28 2013-09-11 富士通株式会社 Manufacturing method of semiconductor device
US7537804B2 (en) * 2006-04-28 2009-05-26 Micron Technology, Inc. ALD methods in which two or more different precursors are utilized with one or more reactants to form materials over substrates
US7798096B2 (en) 2006-05-05 2010-09-21 Applied Materials, Inc. Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films
TWI435376B (en) 2006-09-26 2014-04-21 Applied Materials Inc Fluorine plasma treatment of high-k gate stack for defect passivation
JP2008193005A (en) * 2007-02-07 2008-08-21 Eudyna Devices Inc Manufacturing method for semiconductor device
WO2008108128A1 (en) * 2007-03-08 2008-09-12 Nec Corporation Dielectric material, capacitor using dielectric material, semiconductor device using dielectric material, and method for producing dielectric material
US20090035946A1 (en) * 2007-07-31 2009-02-05 Asm International N.V. In situ deposition of different metal-containing films using cyclopentadienyl metal precursors
JP2009035784A (en) * 2007-08-02 2009-02-19 Kobe Steel Ltd Oxide coating film, material coated with oxide coating film, and method for formation of oxide coating film
US20100123993A1 (en) * 2008-02-13 2010-05-20 Herzel Laor Atomic layer deposition process for manufacture of battery electrodes, capacitors, resistors, and catalyzers
EP2259305A4 (en) 2008-03-28 2014-06-18 Renesas Electronics Corp Capacitor, semiconductor device comprising the same, method for manufacturing the capacitor, and method for manufacturing the semiconductor device
JP5279312B2 (en) 2008-03-28 2013-09-04 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
US7659158B2 (en) 2008-03-31 2010-02-09 Applied Materials, Inc. Atomic layer deposition processes for non-volatile memory devices
US8383525B2 (en) * 2008-04-25 2013-02-26 Asm America, Inc. Plasma-enhanced deposition process for forming a metal oxide thin film and related structures
US8491967B2 (en) 2008-09-08 2013-07-23 Applied Materials, Inc. In-situ chamber treatment and deposition process
US20100062149A1 (en) 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
KR101547313B1 (en) * 2008-11-25 2015-09-07 삼성전자주식회사 Semiconductor devices including a dielectric
BRPI1007463B1 (en) * 2009-02-24 2019-12-24 Graphic Packaging Int Inc packaging for packaging a plurality of articles, blanket for forming a packaging, method of assembling a packaging
US8524617B2 (en) * 2009-02-27 2013-09-03 Canon Anelva Corporation Methods for manufacturing dielectric films
PT2462611T (en) 2009-08-05 2019-12-18 Inst Jozef Stefan Amorphous multicomponent dielectric based on the mixture of high band gap and high k materials, respective devices and manufacture
JP5932221B2 (en) * 2011-01-14 2016-06-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device
US20120235276A1 (en) * 2011-03-18 2012-09-20 Intermolecular, Inc. Electrode treatments for enhanced dram performance
WO2012141698A1 (en) 2011-04-13 2012-10-18 Empire Technology Development Llc Dielectric nanocomposites and methods of making the same
US8383490B2 (en) 2011-07-27 2013-02-26 International Business Machines Corporation Borderless contact for ultra-thin body devices
CN103367409B (en) * 2013-07-04 2015-10-28 西安电子科技大学 Based on the preparation method of the La base high-dielectric-constant gate dielectric material of germanium substrate
US10134732B2 (en) * 2014-04-07 2018-11-20 International Business Machines Corporation Reduction of negative bias temperature instability
WO2018017360A2 (en) * 2016-07-19 2018-01-25 Applied Materials, Inc. High-k dielectric materials comprising zirconium oxide utilized in display devices
US20180026055A1 (en) * 2016-07-19 2018-01-25 Applied Materials, Inc. Hybrid high-k dielectric material film stacks comprising zirconium oxide utilized in display devices
US10354871B2 (en) 2017-09-11 2019-07-16 General Electric Company Sputtering system and method for forming a metal layer on a semiconductor device
US10714486B2 (en) 2018-09-13 2020-07-14 Sandisk Technologies Llc Static random access memory cell employing n-doped PFET gate electrodes and methods of manufacturing the same
CN109962112B (en) * 2019-03-26 2021-04-27 湘潭大学 Ferroelectric grid field effect transistor and preparation method thereof
US11251261B2 (en) * 2019-05-17 2022-02-15 Micron Technology, Inc. Forming a barrier material on an electrode
KR102276021B1 (en) * 2019-08-12 2021-07-12 아주대학교산학협력단 Method of manufacturing a strontium titanate based dielectric layer having high dielectric constant and low leakage current density and method of manufacturing a capacitor including the strontium titanate based dielectric layer
CN115968501A (en) * 2020-07-16 2023-04-14 恩特格里斯公司 Carbon-free laminated hafnium oxide/zirconium oxide film for ferroelectric memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4520413A (en) * 1982-04-13 1985-05-28 Minnesota Mining And Manufacturing Company Integrated magnetostrictive-piezoelectric-metal oxide semiconductor magnetic playback head
US6069070A (en) * 1993-09-20 2000-05-30 East/West Technology Partners, Ltd. Multilevel interconnections of electronic components
JP3320180B2 (en) * 1993-12-22 2002-09-03 ティーディーケイ株式会社 Method for manufacturing thin film transistor
JP3336747B2 (en) * 1994-06-09 2002-10-21 ソニー株式会社 Method for forming insulating film, method for manufacturing semiconductor device, and semiconductor device
JP2907111B2 (en) * 1996-04-22 1999-06-21 日本電気株式会社 Vapor phase growth method and apparatus
US6033919A (en) * 1996-10-25 2000-03-07 Texas Instruments Incorporated Method of forming sidewall capacitance structure
US5780922A (en) * 1996-11-27 1998-07-14 The Regents Of The University Of California Ultra-low phase noise GE MOSFETs
US5929467A (en) * 1996-12-04 1999-07-27 Sony Corporation Field effect transistor with nitride compound
US6054331A (en) * 1997-01-15 2000-04-25 Tong Yang Cement Corporation Apparatus and methods of depositing a platinum film with anti-oxidizing function over a substrate
JP3734586B2 (en) * 1997-03-05 2006-01-11 富士通株式会社 Semiconductor device and manufacturing method thereof
KR100236098B1 (en) * 1997-09-06 1999-12-15 김영환 Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP3703373B2 (en) 2005-10-05
US6207589B1 (en) 2001-03-27
JP2001077111A (en) 2001-03-23
US6060755A (en) 2000-05-09
KR20010029968A (en) 2001-04-16
KR100342316B1 (en) 2002-07-02

Similar Documents

Publication Publication Date Title
TW463385B (en) Aluminum-doped zirconium dielectric film transistor structure and deposition method for same
US6713846B1 (en) Multilayer high κ dielectric films
Wilk et al. Hafnium and zirconium silicates for advanced gate dielectrics
TW564549B (en) Semiconductor device and the manufacturing method thereof
US6407435B1 (en) Multilayer dielectric stack and method
KR100297210B1 (en) High Temperature Electrode-Barriers for Ferroelectric Capacitors and Other Capacitor Structures
US6297539B1 (en) Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
US6875667B2 (en) Method for forming capacitor
US6291283B1 (en) Method to form silicates as high dielectric constant materials
US6743668B2 (en) Process for forming a metal oxy-nitride dielectric layer by varying the flow rate of nitrogen into the chamber
JP2002373945A (en) Semiconductor device and its manufacturing method
TW494576B (en) Lead germanate ferroelectric structure with multi-layered electrode and deposition method for same
JP2002524859A (en) Ternary nitride-carbide barrier layer
US20160027642A1 (en) Methods of Forming Capacitors
Yang et al. Effect of SiO2 intermediate layer on Al2O3/SiO2/n+-poly Si interface deposited using atomic layer deposition (ALD) for deep submicron device applications
US6235594B1 (en) Methods of fabricating an integrated circuit device with composite oxide dielectric
JPH11297867A (en) Electronic component having doped metal oxide dielectric material and manufacturing process of electronic component having doped metal oxide dielectric material
Al-Shareef et al. Metallization schemes for dielectric thin film capacitors
US7300852B2 (en) Method for manufacturing capacitor of semiconductor element
CN102007591A (en) Capacitor and process for manufacturing capacitor
TW200304184A (en) Semiconductor device and production method therefor
WO2024070800A1 (en) Method for producing semiconductor device, and semiconductor device
Roberts et al. Deposition and Properties of Ultra-Thin High Dielectric Constant Insulators
JP2002110969A (en) Semiconductor device and its manufacturing method
WO1998006131A1 (en) Semiconductor device and its manufacture

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees