TW463327B - Method for forming dynamic random access memory - Google Patents
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- TW463327B TW463327B TW090100132A TW90100132A TW463327B TW 463327 B TW463327 B TW 463327B TW 090100132 A TW090100132 A TW 090100132A TW 90100132 A TW90100132 A TW 90100132A TW 463327 B TW463327 B TW 463327B
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- 238000000034 method Methods 0.000 title claims abstract description 88
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 238000005192 partition Methods 0.000 claims description 13
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- 238000001459 lithography Methods 0.000 claims description 8
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- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000005496 tempering Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000004575 stone Substances 0.000 claims 1
- 238000005234 chemical deposition Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 108091006146 Channels Proteins 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- 239000000243 solution Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
463327 五、發明說明（1) 一 發明領域： 本發明係關於一種形成動態隨機存取記憶體（DRAM cell)的方法，特別是關於一種具嵌入式問極 (recessed-gate)之動態隨機存取記憶體的形成方法》 發明背景： 1 近年來隨著半導體製程工業以及半導體設備工業的快 速進步，超大型積體電路（uHra_large scaie integrated c i rcu i t s ; ULS I)的產業有著極為快速的發 展。超大型積體電路通常由為數龐大的金氧半場效電晶體 (MOSFETs)所組成，其中每一個金氧半場效電晶體包含一 源極（s 〇 u r c e )和一沒極（d r a i η )，以及位於二者之間的閘 極（gate)。為求增加積體電路之元件密度（device density)和操作速率（operating speed)，必須不斷地努 力細小電晶體的特徵尺寸（feature size)。特別的是’電 晶體之P型通道或N型通道的通道長度（channel length)與 元件的操作速率習習相關，為求增加積體電路的操作速 率，勢必不斷地努力縮小電晶體的通道長度。 能否將電晶體的通道長度縮短的關鍵技術在於微影製 程（photolithography process)。習知技術是以步進機 (stepper)來進行微影製程，近年來為求達到更小尺寸的 微影極限（photolithography limit)，己渐漸使用掃描機 (scanner)來取代步進機。一般而言，在微影製程中所能 獲致最短之電晶體的通道長度，便等於所述步進機或掃描463327 V. Description of the invention (1) Field of the invention: The present invention relates to a method for forming a dynamic random access memory (DRAM cell), and more particularly to a dynamic random access with embedded-gate. "Methods of Forming Memory" Background of the Invention: 1 In recent years, with the rapid progress of the semiconductor process industry and the semiconductor equipment industry, the industry of ultra-large integrated circuits (uHra_large scaie integrated ci rcu its; ULS I) has developed extremely rapidly. Very large integrated circuits are usually composed of a large number of metal-oxide-semiconductor field-effect transistors (MOSFETs), where each metal-oxide-semiconductor field-effect transistor includes a source (source) and a pole (drai η), and A gate between the two. In order to increase the device density and operating speed of the integrated circuit, the feature size of the small transistor must be continuously worked on. In particular, the channel length of the P-type channel or N-type channel of a transistor is related to the operation rate of the device. In order to increase the operation rate of the integrated circuit, efforts are always made to reduce the channel length of the transistor. The key technology that can shorten the channel length of the transistor is the photolithography process. Conventional technology uses a stepper to perform the lithography process. In recent years, in order to reach a smaller size photolithography limit, a scanner has gradually been used to replace the stepper. In general, the shortest channel length of a transistor in a lithography process is equal to the stepper or scan
第4頁 46 33 2 7 五、發明說明（2) 機之微影極限。 為了形成通道長度為次0 1微米（sub-〇.lum)級的電晶 體，美國專利第6, 0 9 3, 947號專利中揭露了 一種具喪入式 閘極（recessed-gate)的金氧半場效電晶體。依據前揭專 利案’首先在一半導體基板上陸續形成一層墊氧化石夕層 (pad oxide layer)和一層介電層，其中所述半導體基板 上包含有複數個淺渠溝隔離區域（shallow tl~eneh isolation regions)。其次’在所述半導體基板上形成一 孔洞（h ο 1 e )’其包含有底壁及側壁。接下來先形成一層氧 化矽層’再利用非等向性蝕刻技術進行回蝕刻，以在所述 孔洞的侧壁上形成具摻雜材質之氧化石夕間隙壁區域（〇 χ丨d e spacer regions) 〇Page 4 46 33 2 7 V. Description of the invention (2) The lithographic limit of the camera. In order to form a transistor with a channel length of sub-0.1 micron (sub-0.1 micron), US Pat. No. 6,093,947 discloses a recessed-gate gold Oxygen half field effect transistor. According to the previous patent publication, 'a pad oxide layer and a dielectric layer are successively formed on a semiconductor substrate, wherein the semiconductor substrate includes a plurality of shallow trench isolation regions (shallow tl ~ eneh isolation regions). Secondly, 'a hole (h ο 1 e)' is formed in the semiconductor substrate, which includes a bottom wall and a sidewall. Next, a silicon oxide layer is formed first, and then anisotropic etching technology is used to etch back, so as to form a spacer region with a doped material on the sidewall of the hole. 〇
接下來在所述孔洞的底壁上形成閘極氧化矽層（g a t e oxide layer )。其次在所述孔洞及介電層上形成一層複晶 矽層（polysilicon layer)’再以化學機械研磨法（CMP p r 〇 c e s s )將位於所述孔洞外的複晶矽層去除。 接下來將所述介電層去除，以裸露出所述墊氧化碎層和所 述氧化矽間隙壁區域的外壁。接下來並在所述孔洞之旁形 成源極/汲極區域。 最後進行一道回火製程（annealing process)將含於 所述氧化矽間隙壁區域内之摻雜材質擴散出來，以形成源 極 /没極擴展區域（source/drain extension regions)。 接下來在所述墊氧化矽層上形成氮化矽間隙壁，並形成金 屬接觸點，以完成所述具欲入式閘極（r e c e s s e d - g a t e )之Next, a gate silicon oxide layer (g a t e oxide layer) is formed on the bottom wall of the hole. Next, a polysilicon layer 'is formed on the holes and the dielectric layer, and then the polycrystalline silicon layer located outside the holes is removed by a chemical mechanical polishing method (CMP p rc c s s). Next, the dielectric layer is removed to expose the pad oxide fragmentation layer and the outer wall of the silicon oxide spacer region. Next, a source / drain region is formed next to the hole. Finally, an annealing process is performed to diffuse the doped material contained in the silicon oxide spacer region to form source / drain extension regions. Next, a silicon nitride spacer is formed on the pad silicon oxide layer, and a metal contact point is formed to complete the desired gate (r e c e s s e d-g a t e).
463327 五、發明說明（3) 金氧半場效電晶體的製程。 惟，根據前述之習知技術，為了形成動態隨機存取記 憶體之堆疊式電容器（stacked capacitor)，需要在上述 電晶體之上形成兩層複晶矽層（如第二複晶石夕層/第三複晶 硬層、或是第二複晶<5夕層/第四複晶石夕層所述堆疊式電 容益在半導體基板上導致極的拓樸輪廊（high topology)’使得後續之微影及蝕刻製程產生極高的困難 度，而使製程的良率大幅下降。在另一方面，若是形成渠 溝式電容器（trench capacitor)之動態隨機存取記憶體； 則必須在動態隨機存取記憶體的記憶胞中形成額外^渠 溝’如此會浪費半導體基板的面積’相對地使製程的 大幅提高。463327 V. Description of the invention (3) Manufacturing process of metal-oxide half field-effect transistor. However, according to the aforementioned conventional technology, in order to form a stacked capacitor of a dynamic random access memory, two layers of a polycrystalline silicon layer (such as a second polycrystalline silicon layer / The third polycrystalline hard layer, or the second polycrystalline < 5th polycrystalline layer / the fourth polycrystalline polycrystalline layer, the stacked capacitor benefits on the semiconductor substrate, resulting in a very high topology. The lithography and etching processes have extremely high difficulty, which greatly reduces the yield of the process. On the other hand, if it is a dynamic random access memory that forms a trench capacitor, it must be in dynamic random access. The formation of additional trenches in the memory cells that access the memory 'so that the area of the semiconductor substrate is wasted' relatively increases the manufacturing process relatively.
此，發展出一種新的方法以形成動態隨機存取記 體，以提高製程的良率並降低製程的成本，便成為 路業界一項十分重要的課題 發明之概述： 本發明之主要目的是提供一種具嵌入式閘極 ^ecessed-gate)之動態隨機存取記憶體的形成方法。 二二之次要目的是提供—種形成動態隨機存取記情體 (DRAM ce 1 1 )的方法。 U篮 本發明揭露-種形成動態隨機存取記憶體的方法 導體基板上形成隔離區域及濃摻雜區㉟，並在所 达丰導體基板上陸續形成第一介電層和第二介電層並=Therefore, the development of a new method to form a dynamic random access memory to improve the yield of the process and reduce the cost of the process has become a very important subject of the road industry. Summary of the invention: The main purpose of the present invention is to provide A method for forming a dynamic random access memory with an embedded gate (ecessed-gate). The second and second purpose is to provide a method to form a dynamic random access memory (DRAM ce 1 1). The invention discloses a U-basket. A method for forming a dynamic random access memory. An isolation region and a heavily doped region are formed on a conductor substrate, and a first dielectric layer and a second dielectric layer are successively formed on the Dafeng conductor substrate. And =
4 6 33 2 7 五、發明說明（4) 利用微影及非等向性蝕刻製程在所述半導體基板上形成一 渠溝，並同時形成源極/汲極區域。後續在所述渠溝的側 壁上形成含有摻雜材質之第一間隙壁，並在所述渠溝的底 壁上形成一層閘極介電層。 在所述閘極介電層之上形成第一插塞之後，利用熱氧 化技術在所述第一插塞上形成一層隔離層，並利用回火技 術形成源極/汲極擴展區域。其次在所述隔離層上方形成 第二插塞，其中所述第二插塞的頂層表面和所述第二介電 層的表面有相同高度。將所述第二介電層去除之後，在所 述第一間隙壁的側壁上形成第二間隙壁，並在所述第二間 隙壁的側壁上形成第三間隙壁，其中所述第三間隙壁係由 導電材質（例如摻有雜質的複晶矽層）所構成。將所述第 二間隙壁和所述第一間隙壁的上層部分去除之後，在所述 第二插塞和所述第三間隙壁之上形成一電容器。 圖號說明： 1 0半導體基板 1 4濃摻雜區域 18第二介電層 2 2第一間隙壁 26第一導電層 3 0隔離層 3 4第二間隙壁 1 2淺渠溝隔離 16第一介電層 2 0渠溝 2 4閘極介電層 2 8第一插塞 32第二導電層 3 6第三間隙壁4 6 33 2 7 V. Description of the invention (4) A lithography and anisotropic etching process are used to form a trench on the semiconductor substrate, and a source / drain region is formed at the same time. Subsequently, a first spacer wall containing a doped material is formed on a side wall of the trench, and a gate dielectric layer is formed on a bottom wall of the trench. After a first plug is formed over the gate dielectric layer, a layer of isolation is formed on the first plug using a thermal oxidation technique, and a source / drain extension region is formed using a tempering technique. Secondly, a second plug is formed above the isolation layer, wherein the top surface of the second plug and the surface of the second dielectric layer have the same height. After the second dielectric layer is removed, a second gap wall is formed on a side wall of the first gap wall, and a third gap wall is formed on a side wall of the second gap wall, wherein the third gap The wall is made of a conductive material (such as a polycrystalline silicon layer doped with impurities). After the second spacer and the upper portion of the first spacer are removed, a capacitor is formed over the second plug and the third spacer. Description of drawing number: 10 semiconductor substrate 1 4 heavily doped region 18 second dielectric layer 2 2 first spacer 26 first conductive layer 3 0 isolation layer 3 4 second spacer 1 2 shallow trench isolation 16 first Dielectric layer 2 0 trench 2 4 gate dielectric layer 2 8 first plug 32 second conductive layer 3 6 third gap
463327 五、發明說明（5) 4 0下層電極 4 2上層電極 本發明係關於一種形成動態隨機存取記憶體（DRAM c e 1 1 )的方法’特別是關於一種具嵌入式閘極 (r e c e s s e d - g a t e )之動態隨機存取記憶體的形成方法。 首先請參考圖一’其為本發明中形成淺渠溝隔離、濃摻雜 區域、第一介電層和第二介電層的製程剖面圖。首先提供 一 P型單晶的半導體基板10’並在所述半導體基板1〇上形 成淺渠溝隔離（shallow trench isolation regions;STI) 1 2。接下來，利用傳統的離子佈值技術形成濃摻雜區域 14’並在所述半導體基板1〇上陸續形成第一介電層i 6和第 二介電層1 8。 所述淺渠溝隔離1 2的形成方法，係首先利用傳統的微 影及非等向性蝕刻技術在所述半導體基板1 〇的表面上形成 淺渠溝（shallow trenches)。在將光阻以氧氣電漿去除之 後’利用低壓化學 >儿積法（LPCVD)或電聚增強式化學沉積 法（PECVD)形成一層氧化矽層以填滿該淺渠溝，再利用化 學機械研磨法（CMP)將半導體基板1〇表面上的該氧化砍廣 去除。對於N型金氧半場效電晶體而言’所述濃摻雜區域 1 4的摻雜離子係砷（As )或磷（p)離子；對於p型金氧半場 效電晶體而言’所述濃摻雜區域1 4的摻雜離子係删（b )離 子。所述濃摻雜區域14的摻雜濃度介於2E15 to 9E15離 子/平方公分之間；離子的植入能量介於丨5至2 5 ke V之 間’使摻雜離子的植入深度介於1 〇 〇 〇至2 0 〇 〇埃之間。所463327 V. Description of the invention (5) 4 0 lower layer electrode 4 2 upper layer electrode The present invention relates to a method for forming a dynamic random access memory (DRAM ce 1 1), and particularly to a method with a recessed gate ) Method for forming dynamic random access memory. First, please refer to FIG. 1 ', which is a cross-sectional view of a process for forming a shallow trench isolation, a heavily doped region, a first dielectric layer, and a second dielectric layer in the present invention. First, a P-type single crystal semiconductor substrate 10 'is provided and a shallow trench isolation regions (STI) 1 2 is formed on the semiconductor substrate 10. Next, a heavily doped region 14 'is formed using a conventional ion layout technique, and a first dielectric layer i 6 and a second dielectric layer 18 are successively formed on the semiconductor substrate 10. The method for forming the shallow trench isolation 12 is to first form shallow trenches on the surface of the semiconductor substrate 10 using conventional lithography and anisotropic etching techniques. After the photoresist is removed with an oxygen plasma, a silicon oxide layer is formed using LPCVD or PECVD to fill the shallow trench, and chemical machinery is used. The polishing method (CMP) removes the oxide on the surface of the semiconductor substrate 10. For N-type metal-oxide-semiconductor field-effect transistor, 'the doped ion-based arsenic (As) or phosphorus (p) ion of the heavily doped region 14; for p-type metal-oxide-semiconductor field-effect transistor', The doped ions of the heavily doped region 14 delete (b) ions. The doping concentration of the heavily doped region 14 is between 2E15 to 9E15 ions / cm 2; the implantation energy of the ions is between 5 and 2 5 ke V ′, so that the implantation depth of the doped ions is between Between 1000 and 2000 Angstroms. All
4 633 2 7 五、發明說明（6) 述第一介電層1 6係以傳統之低壓化學沉積法（L P C V D )或電 漿增強式化學沉積法（PECVD)所形成，其厚度介於50至 2 〇 〇埃之間。所述第一介電層1 6係二氧化矽層、氧化鈦層 (Ti〇2)或氧化钽層（Ta205)。所述第二介電層18係氮化矽 層（silicon nitride)或氮氧化石夕層（silicon 〇 X y n i t r i d e ) ’以傳統之低壓化學沉積法（L P C V D )或電漿增 強式化學沉積法（PECVD)所形成，其厚度介於3000至 1 0 0 0 0埃之間。其中所述第一介電層1 6和第二介電層1 8之 間必須有蝕刻選擇性。本發明的重點之一在於，所述第二 介電層1 8的厚度較習知技術厚得多，使得後續製程可以在 電晶體之上方直接形成電容器，而不會產生高的拓樸輪 廓。 接下來請參考圖二，利用微影及非等向性蝕刻技術在 所述半導體基板1 0上形成渠溝2 0。所述非等向性蝕刻技術 係分別對所述第二介電層1 8 '第一介電層1 6和半導體基板 1 0進行姓刻。 所述渠溝2 0係位於所述濃摻雜區域1 4之間，延伸穿透 部分之濃摻雜區域1 4 ’如圖二所示。所述渠溝2 0的深度介 於3 0 0 0埃至1 〇 〇 〇 〇埃之間，其底壁的深度大於所述漢摻雜 區域14的接面深度（junction depth)，因而該非等向性餘 刻製程延伸穿透部分之漢摻雜區域1 4而形成源極/汲極區 域（source/drain regions)14A。在本發明的一個實施例 中’所述渠溝的寬度小於0. 1微米；在本發明的另一個實 施例中’所述渠溝的寬度等於〇. 1微米。4 633 2 7 V. Description of the invention (6) The first dielectric layer 16 is formed by a conventional low pressure chemical deposition method (LPCVD) or a plasma enhanced chemical deposition method (PECVD), and has a thickness of 50 to Between 200 angstroms. The first dielectric layer 16 is a silicon dioxide layer, a titanium oxide layer (Ti02), or a tantalum oxide layer (Ta205). The second dielectric layer 18 is a silicon nitride layer or a silicon nitride oxide layer (silicon OXnitry). The traditional low-pressure chemical deposition method (LPCVD) or plasma enhanced chemical deposition method (PECVD) is used. ), With a thickness between 3000 and 100 angstroms. There must be an etch selectivity between the first dielectric layer 16 and the second dielectric layer 18. One of the important points of the present invention is that the thickness of the second dielectric layer 18 is much thicker than the conventional technology, so that the subsequent process can form a capacitor directly above the transistor without generating a high topology. Next, referring to FIG. 2, trenches 20 are formed on the semiconductor substrate 10 by using lithography and anisotropic etching techniques. The anisotropic etching technology engraves the second dielectric layer 18 ', the first dielectric layer 16 and the semiconductor substrate 10, respectively. The trench 20 is located between the heavily doped regions 14 and the heavily doped regions 1 4 'extending and penetrating are shown in FIG. The depth of the trench 20 is between 300 angstroms and 1000 angstroms, and the depth of the bottom wall is greater than the junction depth of the Chinese-doped region 14. The directional epitaxial process extends the Han-doped regions 14 through the penetrating portions to form source / drain regions 14A. In one embodiment of the present invention, the width of the trench is less than 0.1 micron; in another embodiment of the present invention, the width of the trench is equal to 0.1 micron.
463327 五'發明說明（7) ^ ---：-- 接下來清參考圖三，其為在所述渠溝2 〇的側壁上形成 含有摻雜材質之第一間隙壁22、閘極介電層24、及第一導 電層26的不意圖°首先利用傳統之PECVD技術或LPCVD技術 形成一 f含有榜雜材質之氧化矽層，並利用非等向性蝕刻 技術進行回蚀刻’以在所述渠溝2 〇的側壁上形成含有摻雜 材質之第間隙壁2 2。所述第一間隙壁2 2内含有p型摻雜 材質（例如删）或N型摻雜材質（例如砷或磷），使得後續利 用一回火製程便可將所述摻雜材質擴散至半導體基板中。 接下來進行一道濃姓刻製程’以NH /和HF的混合溶液對 所述半導體基10進行濕蝕刻，以去除半導體基板1〇表面 上的晶格缺陷。其中所述心4?和HF的混合溶液僅會蝕刻 石夕基板’對於其他各層不會有損害。接下來利用熱氧化製 程或化學汽相沉積法在所述渠溝2 0的底壁上形成閘極介電 層2 4。所述閘極介電層2 4的厚度介於2 0埃至3 0埃之間，由 氧化矽或含氮之氧化矽所構成。在本發明的另一個實施例 中’所述閘極介電層2 4的厚度小於2 〇埃。接下來在所述閘 極介電層24、第一間隙壁22、第二介電層18的表面上形成 第一導電層26’厚度介於1〇〇 〇埃至3〇〇〇埃之間。所述第一 導電層2 6係一層摻有P型或N型雜質的複晶矽層，由傳統之 低壓化學沉積法（LPCVD)或電漿增強式化學沉積法（pecVD) 所形成。在本發明的一個實施例中，所述雜質係在第一導 電層2 6的沉積過程中同步沉積（in-situ)而摻入第一導電 層2 6中；在本發明的另一個實施例中，係先形成本徵的 (intrinsic)複晶矽層，再以離子佈植技術將所述雜質摻463327 Five 'invention description (7) ^ ---: --- Next, refer to FIG. 3, which is to form a first spacer 22 containing a doped material and a gate dielectric on the sidewall of the trench 20. Unintentional layer 24 and first conductive layer 26 ° First, a conventional silicon oxide layer or a LPCVD technology is used to form a silicon oxide layer containing an impurity material, and an anisotropic etching technique is used to etch back the ' A second partition wall 22 containing a doped material is formed on the sidewall of the trench 20. The first partition wall 22 contains a p-type doped material (for example, deleted) or an N-type doped material (for example, arsenic or phosphorus), so that the doped material can be diffused to the semiconductor by a subsequent tempering process. Substrate. Next, a thick etching process is performed to wet-etch the semiconductor substrate 10 with a mixed solution of NH / and HF to remove lattice defects on the surface of the semiconductor substrate 10. Wherein, the mixed solution of the core 4? And HF will only etch the Shi Xi substrate 'and will not damage the other layers. Next, a gate dielectric layer 24 is formed on the bottom wall of the trench 20 by using a thermal oxidation process or a chemical vapor deposition method. The gate dielectric layer 24 has a thickness between 20 angstroms and 30 angstroms, and is composed of silicon oxide or silicon oxide containing nitrogen. In another embodiment of the present invention, the thickness of the gate dielectric layer 24 is less than 20 angstroms. Next, a first conductive layer 26 'is formed on the surfaces of the gate dielectric layer 24, the first spacer 22, and the second dielectric layer 18, and the thickness is between 1000 angstroms and 3,000 angstroms. . The first conductive layer 26 is a polycrystalline silicon layer doped with P-type or N-type impurities, and is formed by a conventional low-pressure chemical deposition method (LPCVD) or a plasma enhanced chemical deposition method (pecVD). In one embodiment of the present invention, the impurities are simultaneously deposited in-situ during the deposition process of the first conductive layer 26 and doped into the first conductive layer 26; in another embodiment of the present invention In the system, an intrinsic polycrystalline silicon layer is formed first, and then the impurities are doped by ion implantation technology.
第10頁 463327 五、發明說明（8) 入所述第一導電層2 6中。 後續請參考圖四，利用非等向性蝕刻技術對所述導電 層26進行回蝕刻，以在所述渠溝20内形成第一插塞28，以 做為動態隨機存取記憶體之電晶體的欲入式問極 乂 (recessed-gate)。接下來利用一熱氧化技術，在所述第 一插塞2 8的表面上形成一隔離層3〇。後續進行—道回火製 程（anneal ing process)，將含於所述第一間隙壁22内之 摻雜材質擴散出來，以形成源極/没極擴展區域 (source/drain extension regi〇ns)32。所述回火製程— 般係以快速熱回火製程（rapid thermal annealing; RTa) 所進行。所述源極/沒極擴展區域3 2包覆所述第一間隙辟 2 2，用以連接所述源極/汲極區域1 4 A和位於所述閘極介f 層2 4下方的通道區域a接下來在所述隔離層30、第-間％ 壁22、和第二介電層18的表面上形成第二導電層32，厚度 介於2 0 0 0埃至5 0 0 0埃之間，用以將所述渠溝2 0填滿。所述 第二導電層3 2係一層摻有P型或N型雜質的複晶矽層，由傳 統之低壓化學沉積法（LPC VD)或電焚增強式化學沉積法 C P E C V D )所形成。在本發明的一個實施例中，所述雜質係 在第二導電層3 2的沉積過程中同步沉積（丨11_5丨1：11)而摻入 第二導電層3 2中；在本發明的另一個實施例中，係先形成 本徵的（i n t r i n s i c )複晶ξ夕層，再以離子佈植技術將所述 雜質摻入所述第二導電層32中。 接下來請參考圖五，利用化學機械研磨技術 (chemical tnachnical polishing; CMp)將位於所述渠溝Page 10 463327 V. Description of the invention (8) Into the first conductive layer 26. Please refer to FIG. 4 in the following, using anisotropic etching technology to etch back the conductive layer 26 to form a first plug 28 in the trench 20 as a transistor of a dynamic random access memory. Recessed-gate. Next, a thermal oxidation technique is used to form an isolation layer 30 on the surface of the first plug 28. Subsequent process—annealing process, diffuses the doped material contained in the first spacer 22 to form a source / drain extension region (32) . The tempering process is generally performed by rapid thermal annealing (RTa). The source / non-electrode extension region 3 2 covers the first gap 2 2 to connect the source / drain region 1 4 A and a channel below the gate dielectric layer f 4 The region a next forms a second conductive layer 32 on the surface of the isolation layer 30, the first-middle wall 22, and the second dielectric layer 18, with a thickness ranging from 20,000 to 500 angstroms. To fill the trench 20. The second conductive layer 32 is a layer of a polycrystalline silicon layer doped with P-type or N-type impurities, and is formed by a conventional low-pressure chemical deposition method (LPC VD) or an electro-enhanced chemical deposition method (C P E C V D). In one embodiment of the present invention, the impurities are simultaneously deposited (丨 11_5 丨 1:11) and deposited in the second conductive layer 32 during the deposition process of the second conductive layer 32; In one embodiment, an intrinsic complex crystal layer is formed first, and then the impurity is doped into the second conductive layer 32 by an ion implantation technique. Please refer to FIG. 5 next. Chemical tnachnical polishing (CMp) will be located in the trench.
第11頁 463327 五、發明說明（9) 2 0外之第二導電層3 2去除，以在所述渠溝2 0内形成第二插 塞3 2 A。接下來進行一道選擇性蝕刻製程，以將所述第二 介電層1 8去除。在本發明的一個實施例中，所述選擇性姓 刻製程係以濕蝕刻技術進行，將半導體基板1 0浸入熱磷酸 溶液中。後續在所述第一間隙壁2 2的側壁上形成第二間隙 壁3 4。所述形成第二間隙壁3 4的步驟，係先利用傳統之 PECVD技術或LPCVD技術形成一層氧化矽層，再利用非等向 性蝕刻技術進行回蝕刻，以在所述第一間隙壁2 2的側壁上 形成第二間隙壁3 4。接著在所述第二間隙壁3 4的側壁上形 成第三間隙壁3 6。所述形成第三間隙壁3 6的步驟，係先利 用傳統之PECVD技術或LPCVD技術形成一層含有摻雜材質之 複晶矽層，再利用非等向性蝕刻技術進行回蝕刻，以在所 述第二間隙壁3 4的側壁上形成第三間隙壁3 6。在本發明的 一個實施例中，所述雜質係在複晶矽層的沉積過程中同步 沉積（in-situ)而摻入複晶矽層中；在本發明的另一個實 施例中，係先形成本徵的（i n t r i n s i c )複晶矽層，再以離 子佈植技術將所述雜質摻入所述複晶矽層中。 接下來請參考圖六，利用一道濕蝕刻技術將所述第二 間隙壁3 4和所述第一間隙壁2 2的上層部分去除，以裸露出 所述第二插塞3 2 A的側壁。接下來利用傳統之化學汽相沉 積法形成一層導電層（例如摻雜之複晶矽層），再利用微 影及蝕刻技術定義所述導電層，以形成動態隨機存取記憶 體之電容器的下層電極40。其次，電容器介電層（未顯示 在圖上）和電容器的上層電極4 2亦依序形成在所述下層電Page 11 463327 V. Description of the invention (9) The second conductive layer 32 outside the 20 is removed to form a second plug 3 2 A in the trench 20. Next, a selective etching process is performed to remove the second dielectric layer 18. In one embodiment of the present invention, the selective lasting process is performed by a wet etching technique, and the semiconductor substrate 10 is immersed in a hot phosphoric acid solution. Subsequently, a second gap wall 34 is formed on a side wall of the first gap wall 22. The step of forming the second spacer wall 34 is to form a silicon oxide layer by using conventional PECVD technology or LPCVD technology, and then perform an etch-back using anisotropic etching technology to form a second spacer wall 2 2 A second partition wall 34 is formed on the side wall of the substrate. A third partition wall 36 is then formed on the side wall of the second partition wall 34. The step of forming the third spacer wall 36 is to first form a polycrystalline silicon layer containing a doped material by using conventional PECVD technology or LPCVD technology, and then etch back using anisotropic etching technology to A third partition wall 36 is formed on a side wall of the second partition wall 34. In one embodiment of the present invention, the impurities are in-situ and doped into the polycrystalline silicon layer during the deposition of the polycrystalline silicon layer. In another embodiment of the present invention, the An intrinsic polycrystalline silicon layer is formed, and the impurities are doped into the polycrystalline silicon layer by an ion implantation technique. Next, referring to FIG. 6, an upper portion of the second spacer wall 34 and the first spacer wall 22 is removed by using a wet etching technique to expose the sidewall of the second plug 3 2 A. Next, a conventional chemical vapor deposition method is used to form a conductive layer (such as a doped polycrystalline silicon layer), and then the conductive layer is defined by lithography and etching techniques to form the lower layer of the capacitor of the dynamic random access memory. Electrode 40. Secondly, a capacitor dielectric layer (not shown in the figure) and an upper electrode 42 of the capacitor are also sequentially formed on the lower layer.
第12頁 463327 五、發明說明（ίο) 極4 0之上。 本發明的重點在於，所述電容器之下層電極4 0不僅位 於第二插塞3 2 A的側壁上，同時亦位於第三間隙壁3 6的表 面及側壁上。因此利用本發明技術所形成之動態隨機存取 記憶體非但具有較低之拓樸輪廓，更具有較大之電容器面 積，不但可提高製程的良率，更可有效地增加電容器的電 容值。 以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明的範圍，而且熟知此技藝的人士亦能明暸，適當 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍。Page 12 463327 V. Description of the Invention (ίο) Above 40. The main point of the present invention is that the lower electrode 40 of the capacitor is not only located on the side wall of the second plug 3 2 A, but also on the surface and the side wall of the third gap wall 36. Therefore, the dynamic random access memory formed by using the technology of the present invention not only has a lower topological profile, but also has a larger capacitor area, which can not only improve the yield of the process, but also effectively increase the capacitance value of the capacitor. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will also understand that making small changes and adjustments appropriately will still lose the essence of the present invention. Without departing from the spirit and scope of the invention.
第13頁 463327 圖式簡單說明 圖一為本發明中形成淺渠溝隔離、濃摻雜區域、第一 介電層和第二介電層的製程剖面圖。 圖二是本發明中在所述半導體基板上形成渠溝的製程 剖面圖。 圖三是本發明中在所述渠溝的側壁上形成含有摻雜材 質之第一間隙壁、閘極介電層、及第一導電層的製程剖面 示意圖。 圖四是本發明中形成第一插塞、隔離層、及源極/汲 極擴展區域的製程剖面圖。 圖五是本發明中形成第二插塞、第二間隙壁、以及第 三間隙壁的製程剖面圖。 圖六是本發明中形成電容器的製程剖面圖。Page 13 463327 Brief description of the drawings Figure 1 is a cross-sectional view of a process for forming a shallow trench isolation, a heavily doped region, a first dielectric layer and a second dielectric layer in the present invention. FIG. 2 is a cross-sectional view of a process for forming a trench on the semiconductor substrate according to the present invention. FIG. 3 is a schematic cross-sectional view of a process for forming a first spacer wall containing a doped material, a gate dielectric layer, and a first conductive layer on a sidewall of the trench in the present invention. FIG. 4 is a cross-sectional view of a process for forming a first plug, an isolation layer, and a source / drain extension region in the present invention. FIG. 5 is a cross-sectional view of a process for forming a second plug, a second spacer, and a third spacer in the present invention. FIG. 6 is a cross-sectional view of a process for forming a capacitor in the present invention.
第14頁Page 14
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090100132A TW463327B (en) | 2001-01-03 | 2001-01-03 | Method for forming dynamic random access memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090100132A TW463327B (en) | 2001-01-03 | 2001-01-03 | Method for forming dynamic random access memory |
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| TW090100132A TW463327B (en) | 2001-01-03 | 2001-01-03 | Method for forming dynamic random access memory |
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