TW483121B - Formation method of dynamic random access memory - Google Patents

Abstract

This invention provides a formation method of dynamic random access memory. Firstly, an isolation region, a heavily doped region, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. Subsequently, a trench and source/drain region are formed through photolithography and anisotropic etching on the substrate. A dopant-containing silicon oxide spacer is formed on the side wall of the trench, and a gate dielectric layer is formed at the bottom of the trench. A gate plug is formed on the top of the gate dielectric layer and then an isolation layer is formed on the plug and source/drain extension region is formed also. Finally, a capacitor is formed on the isolation layer of the trench.

Description

V. Description of the invention (1) Field of the invention: The present invention relates to a method for forming a kinetic cell to access ten χ _L ΛL 1 think-memory access memory cells (dram cells), especially about a capacitor. The device is directly located Forming method of dynamic random access memory above transistor with "ecessed-gate". Background of the Invention: In recent years, Ik has made rapid progress in the semi-V body packaging industry and the semiconductor equipment industry. The industry of uHra—Urge scale integrated cirCuits (ULS I) has developed extremely rapidly. Large integrated circuits are usually composed of a large number of metal-oxide-semiconductor field-effect transistors (MOSFETs), each of which has a metal-oxide-semiconductor field-effect transistor The transistor includes a source and a drain, and a gate between them. In order to increase the device density and operating speed of the integrated circuit ), We must continuously strive to reduce the feature size of the transistor. In particular, the channel length of the P-channel or N-channel of the transistor and the operation of the device Speed is related, in order to increase the operation rate of the integrated circuit, it is bound to continuously strive to reduce the channel length of the transistor. The key technology for reducing the channel length of the transistor is the lithography process (ph〇t〇1 i 1 : H 〇graphypr〇cess). The conventional technology uses a stepper to perform the lithography process. In recent years, in order to reach a smaller size lithography limit (phot ο 1 i thography 1 imit), it has been gradually used. Scanner (sca η ner) instead of stepper. Generally speaking, 483121 can be used in lithography process. 5. Description of the invention (2) The shortest channel length of the transistor is equal to the stepper or scan. In order to form a transistor with a channel length of the sub-0.1 micron (sub-0 · 1 u π) level, a U.S. Patent No. 6,093,94 7 discloses a device with a gate. Recessed-gate metal-oxide-semiconductor field-effect transistor. According to the previous patent, a layer of a pad oxide layer and a dielectric layer are successively formed on a semiconductor substrate. It includes a plurality of shallow trench isolation regions (shal low treneh substrate

isolation regions). Secondly, a hole (h ο 1 e) is formed in the semiconductor substrate, which includes a bottom wall and a sidewall. Next, a silicon oxide layer is formed first, and then anisotropic etching technology is used to etch back to form a silicon oxide spacer region with doped material on the sidewall of the hole. A gate oxide layer is formed on the bottom wall of the hole. Next, a polysilicon layer (polysi 1 icon layer) is formed on the holes and the dielectric layer, and then the polycrystalline silicon layer located outside the holes is removed by a chemical mechanical polishing method (CMp p r oc e s s). Next, the dielectric layer is removed to expose the outer wall of the pad silicon oxide layer and the reversed oxide stone gap wall region. Next and next to the hole

Into the source / non-polar region. Finally, a tempering process is performed to diffuse out the doped material contained in the interstitial region of the oxidized stone to form source regions) 0, and form gold poles and > and pole extension regions ( s〇urce / drain extensi〇n Next, a silicon nitride spacer is formed on the pad silicon oxide layer.

Page 5 483121 V. Description of the invention (3) It is a contact point to complete the process of the recessed-gate metal-oxygen half field effect transistor. However, according to the aforementioned conventional technology, in order to form a stacked capacitor of a dynamic random memory, it is necessary to form two layers of a polycrystalline silicon layer (such as a polycrystalline silicon layer / Third ^ silicon layer, or third polycrystalline silicon layer / fourth polycrystalline silicon layer). The stack: the type = the container leads to a very high topography on the semiconductor substrate (h 丨 gh and industry and private = opolo), which makes the subsequent lithography and etching process extremely difficult, and makes the process The yield has dropped significantly. On the other hand, if the moving cap of the trench capacitor (trench capacit〇r) is stored randomly, it must be formed in the memory of the dynamic random access memory: J: amplitude :: will waste semiconductors The surface of the substrate "is relatively important in making random access memory circuits in the manufacturing industry-a very important lesson; the low" cost has become an overview of the integrated circuit invention: The main purpose of the invention is to provide-

Crecessed-gate) ^ <, intrusive idle pole The secondary object of the present invention = a method of forming a memory. Memory (DRAM cel 1). A method for forming dynamic random access memory The present invention discloses a method for forming memory on a semiconductor substrate. A slave device accesses a memory, firstly forming a disjoint region, a heavily doped region, and a first medium. The present invention further discloses that a dynamic random access memory device includes 483121 five 'invention description (4) an electrical layer and a second dielectric layer. Subsequent lithography and anisotropic etching processes are used to form a trench on the edge + conductor substrate and simultaneously form the source / drain regions. Next, a silicon oxide spacer containing a doped material is formed on a sidewall of the trench, and a gate dielectric layer is formed on a bottom wall of the trench. After a gate plug is formed on the gate dielectric layer, an isolation layer is formed on the gate plug, and a source / drain extension region is formed. Finally, a capacitor is formed on the isolation layer in the trench. Crystal and ~ capacitor. The transistor is located in a trench of a semiconductor substrate, and includes a source / drain region, an interrogation / channel region, a source index, and a pole extension region. Wherein, the source / non-electrode region is separated by the gate / pass; the inter-electrode / channel region includes a channel region between: 5 regions, wherein the gate region is located on a silicon oxide gap wall Layer Gate Dielectric ★ @ ^ above 4 is connected with an isolation layer, which is adjacent below-the interlayer dielectric layer is adjacent to the semiconductor substrate; connected to the source Λ and the electrode & Β 4: the emulsified silicon The partition wall is used to connect the k-th order region and the channel region. The capacitor is also located at the base and the mounting side, which is provided in the J: electrode in the trench and located in the isolation layer, wherein the lower layer is a dielectric layer and an upper layer. f device dielectric; i γ &, +, electricity and 1; above the isolation layer; above the dielectric layer of the electrolytic capacitor I: above; the upper electrode is located above.

483121 V. Description of the invention (5) Description of drawing number: 10—semiconductor substrate 1 3—doped region 1 6—second dielectric layer 2 0—silicon oxide spacer 2 4—gate plug 2 8—isolation layer 3 2-lower electrode

1 2-Shallow trench isolation 1 4- First dielectric layer 1 8-Trench trench 2 2- Gate dielectric layer 2 6-Source / drain extension area 3 0- Second conductive layer 3 4-Upper electrode The present invention relates to the ability to form a courtesy.

* The method of accessing memory (DRAM ce 1 1), especially the formation of dynamic random access memory with capacitors directly above a transistor with an embedded closed-gate method.

Please refer to FIG. 1 first, which is a cross-sectional view of a process for forming a shallow trench isolation, a heavily doped region, a first dielectric layer, and a second dielectric layer in the present invention. First, a P-type single crystal semiconductor substrate 10 is provided, and a shallow trench isolation regiQns · S T I) 12 is formed on the semiconductor substrate 1 Q. The following text is used to form a heavily doped region 13 using a conventional ionic layout technique, and a first dielectric layer κ and a second dielectric layer 16 are successively formed on the semiconductor substrate 10. The method of forming the shallow trench isolation 12 is to first form shallow trenches on the surface of the semiconductor substrate 100 using conventional lithography and anisotropic etching techniques. After removing the photoresist with an oxygen plasma, low pressure chemical deposition (LPCVD) or plasma enhanced CVD is used 483121

5. Description of the invention (6) The method (PECVD) forms a silicon oxide layer to fill the shallow trench, and then uses chemical mechanical polishing (CMP) to remove the oxide fragmentation layer on the surface of the semiconductor substrate 10. For an N-type metal-oxide-semiconductor field-effect transistor, the doped ions of the heavily doped region 13 are arsenic (A s) or _ (p) ions; The doped ionic boron (β) ion in the heavily doped region 3 is described. The doping concentration of the heavily doped region 1 3 is between 2 E 1 5 t 〇 9 E 1 5 ions / Ping Nai cm, and the implantation energy of the ions is between 15 and 2 5 ke V. The implantation depth of doped ions is between 1000 and 2000 Angstroms. The first dielectric layer 4 is formed by a conventional low-pressure chemical deposition method (LPCVD) or an electro-hydraulic chemical deposition method (PEC VD), and has a thickness between 50 and 2000 angstroms. The first dielectric layer 14 is a silicon dioxide layer, a titanium oxide layer (h02), or an oxide button layer (Ta205). The second dielectric layer is a sillcon nitride layer or a silicon oxynitride layer (siHcOn ΠΛ1 tride). The conventional low-pressure chemical deposition method (LPCVD) or plasma enhanced deposition method (PECVD) is used. The thickness formed is between 1000 and 1000. The first dielectric layer 14 and the first dielectric layer must have etching selectivity. % Day i Next, referring to FIG. 2, the second dielectric layers 16 and 10 are etched by using trenches formed on the semiconductor substrate 10, respectively. Lithography and anisotropic etching technology at I8 °. The anisotropic etching technology described above. The first dielectric layer 14 and the semiconductor substrate. The trench 18 are located in the heavily doped region 1 of the heavily doped portion. 3, as shown in the second two degrees ° ,,,,,, and day, extending teeth between 5 ㈣ angstroms to 15 0 0 angstroms, the depth of the dip Γ ^ Mugou 18 depth of one The degree of 大于 is greater than the heavily doped 483121 V. Description of the invention (7) The junction depth (j U ncti ο ndepth) of the region 1 3, so the anisotropic |丨 3 to form a source / drain region 13A. One of the key points of the present invention is that the depth of the trench 18 is much deeper than the trench of the conventional embedded gate, so that after the embedded gate of the transistor is formed in the present invention, the subsequent process can directly change the dynamic random The capacitor for accessing the memory is formed on the embedded gate and is located in the trench 18, which not only can save the area of the semiconductor substrate, but also can make the topology of the dynamic random access memory extremely extremely. Flat 丄 can significantly reduce process costs and improve process yield. In one embodiment of the present invention, the width of the trench is less than 0.1 micron; in another embodiment of the present invention, the width of the trench is equal to 0.1 micron. Next, please refer to FIG. 3, which is a schematic diagram of forming a silicon oxide spacer wall 20 including a dopant material and a gate dielectric layer 22 on a sidewall of the trench 8. First, a conventional PECVD technology or LPCVD technology is used to form a silicon oxide layer containing a doped material, and an anisotropic etching technique is used to carry back money engraving to form a doped material containing a doped material on the sidewall of the trench 18 Oxide stone evening wall 20. The silicon oxide spacer wall 20 contains a p-type doped material (such as a shed) or a lattice material (such as Shishen or phosphorus), so that the doped material can be diffused to the semiconductor substrate in a subsequent tempering process. in. Next, a wet after-etching process is performed, and the semiconductor substrate 10 is wet-etched with a mixed solution of NH4F and HF to remove lattice defects on the surface of the semiconductor substrate 10. Wherein, the mixed solution of NH4F and HF will only etch the silicon substrate, and will not damage the other layers. Next, a gate dielectric layer 22 is formed on the bottom wall of the trench 8 by a thermal oxidation process or a chemical vapor deposition method. Said

Page 10 ^ 3121 V. Description of the invention (8) The thickness of the leisure dielectric layer 22 is between 20 angstroms and 30 angstroms, and is composed of silicon oxide or a gaseous stone containing ^ ^. In another embodiment of the invention, the thickness of the dielectric layer 22 is less than 20 angstroms. Next, a first conductive layer is formed on the surface of the gate dielectric layer 22, the silicon oxide spacer 20, and the second dielectric layer 16 with a thickness between 100 angstroms and 300 angstroms. The first conductive layer is a polycrystalline silicon layer doped with p-type or n-type impurities, and is formed by a conventional low-pressure chemical deposition method (LPCVD) or a plasma enhanced chemical deposition method (PECVD). In one embodiment of the present invention, the impurities are simultaneously deposited in-situ during the deposition of the first conductive layer and are incorporated into the first conductive layer. In another embodiment of the present invention, the impurities An intrinsic polycrystalline silicon layer is formed, and the impurities are doped into the first conductive layer by an ion implantation technique. The anisotropic money engraving technique is then used to carry out money engraving on the first conductive layer to form a gate plug 24 in the trench 18 as a dynamic random access memory. Recessed-gate of a transistor. The top surface of the gate plug 24 must be lower than the top surface of the first dielectric layer 14 as shown in FIG. Next, referring to FIG. 5, an isolation layer 28 is formed on the surface of the gate plug 24 by using a thermal oxidation technique. Subsequently, an annealing process is performed to diffuse the doped material contained in the silicon oxide spacer 20 to form source / drain extension regions 26. The tempering process is generally performed by a rapid thermal tempering process (r a p i d t h e r in a 1 a n n a a i n g; RT A). The source / drain extension region 2 6 covers the silicon oxide 483121. V. Description of the invention (9) The partition wall 20 is used to connect the source / drain region 1 3 A and the gate electrode. The channel region under the dielectric layer 22. Next, a second conductive layer 30 is formed on the surfaces of the isolation layer 28, the silicon oxide spacer 20, and the second dielectric layer 16 with a thickness between 100 angstroms and 300 angstroms. between. The second conductive layer 30 is a polycrystalline silicon layer doped with P-type or N-type impurities, and is formed by a conventional low-pressure chemical deposition method (LPCVD) or a plasma enhanced chemical deposition method (PECVD). In one embodiment of the present invention, the impurities are simultaneously deposited in the second conductive layer 30 during the deposition process of the second conductive layer 30, and are incorporated into the second conductive layer 30. In another embodiment of the present invention, First, an intrinsic (i η rin rinsic) multicrystalline silicon layer is formed, and then the impurities are doped into the second conductive μ electric layer 30 by an ion implantation technique. Next, referring to FIG. 6, the second conductive layer 30 is defined by using conventional lithography and etching techniques to form a lower electrode 32 of a capacitor of a dynamic random access memory. Secondly, a capacitor dielectric layer (not shown in the figure) and an upper electrode 34 of the capacitor are also sequentially formed on the lower electrode 32. The main point of the present invention is that the depth of the trench 18 is much deeper than the trench of the conventional embedded gate, so that after the embedded gate of the transistor is formed in the present invention, the subsequent process can directly store the dynamic random storage. A capacitor for taking a memory is formed on the embedded gate and is located in the trench 18, which not only saves the area of the semiconductor substrate 9 but also makes the topology of the dynamic random access memory 'extremely simple. Flat, which can greatly reduce the process cost and improve the process yield. The above description uses the preferred embodiments to describe the present invention in detail, but not to limit the scope of the present invention. Those skilled in the art can also understand that it is appropriate

Page 12 483121 V. Description of the invention (ίο) Making minor changes and adjustments will still not lose the essence of the invention, nor depart from the spirit and scope of the invention. 483121 Brief description of the drawings Schematic description: FIG. 1 is a cross-sectional view of a process for forming a shallow trench isolation, a heavily doped region, a first dielectric layer, and a second dielectric layer in the present invention. FIG. 2 is a cross-sectional view of a process for forming a trench on the semiconductor substrate according to the present invention. FIG. 3 is a schematic cross-sectional view of a process for forming a silicon oxide spacer containing a doped material and a gate dielectric layer on a sidewall of the trench in the present invention. FIG. 4 is a sectional view of a process of forming a gate plug in the present invention. FIG. 5 is a cross-sectional view of a process for forming a conductive layer in the present invention. FIG. 6 is a cross-sectional view of a process for forming a capacitor in the present invention.

Claims (1)

483121 VI. Application for patent scope 1. A method for forming a dynamic random access memory, the steps include: a. Forming an isolation region and a heavily doped region on a semiconductor substrate; b. Successively forming a first on the semiconductor substrate A dielectric layer and a second dielectric layer; c. Forming a trench on the semiconductor substrate using a lithography and anisotropic etching process, and simultaneously forming a source / drain region; d. In the trench A silicon oxide spacer containing a doped material is formed on the side wall of the trench; e. A gate dielectric layer is formed on the bottom wall of the trench; f. A gate plug is formed on the gate dielectric layer U g. Forming an isolation layer on the gate plug; h. Forming a source / drain extension region; and i. Forming a capacitor over the isolation layer in the trench. 2. The method for forming a dynamic random access memory according to item 1 of the application, wherein the heavily doped region is formed by an ion implantation technique. 3. The method for forming a dynamic random access memory according to item 1 of the application, wherein the first dielectric layer and the second dielectric layer have an etching selectivity. — 4. The method for forming a dynamic random access memory according to item 1 of the patent application scope, wherein the first dielectric layer is a silicon oxide layer. Page 15 483121 6. Scope of patent application 5. The method for forming a dynamic random access memory according to the first scope of the patent application, wherein the second dielectric layer is a silicon nitride layer. 6. The method for forming a dynamic random access memory according to item 1 of the patent application scope, wherein the second dielectric layer is a silicon oxynitride layer. 7. The method for forming a dynamic random access memory according to item 1 of the patent application, wherein the depth of the bottom wall of the trench is greater than the junction depth of the heavily doped region. 1 8. The method for forming a dynamic random access memory according to item 1 of the scope of patent application, wherein the anisotropic etching process successively etches the second dielectric layer, the first dielectric layer, and the semiconductor substrate . 9. The method for forming a dynamic random access memory according to item 1 of the scope of patent application, wherein the method for forming the silicon oxide spacer is to deposit a silicon oxide layer containing a doped material first, and then use anisotropic etching Technology goes back. 10. The method f of forming a dynamic random access memory according to item 1 of the patent application scope, wherein the gate dielectric layer is formed by a thermal oxidation technique. 1 1. The method for forming a dynamic random access memory according to item 10 of the patent application, wherein the thickness of the gate dielectric layer is less than 20 angstroms. Page 16 483121 VI. Application for patent scope 1 2. The method for forming dynamic random access memory as described in the first patent application scope, wherein the method of forming the gate plug is to deposit a conductive layer first, and then use non- Isotropic etching technology etches back the conductive layer. 13. The method for forming a dynamic random access memory according to item 12 of the patent application scope, wherein the conductive layer is a polycrystalline silicon layer doped with impurities. 14. The method for forming a dynamic random access memory according to item 1 of the patent application scope, wherein the isolation layer is formed by a thermal oxidation technology. 15. The method for forming a dynamic random access memory according to item 1 of the scope of the patent application, wherein the method for forming the source / drain extension region is to use a tempering technique to contain the silicon oxide spacer The doped material inside diffuses into the semiconductor substrate. 16. The method for forming a dynamic random access memory according to item 1 of the scope of patent application, wherein the method for forming the capacitor includes: a. Forming a conductive layer; b. Defining the conductive layer to form the capacitor A lower electrode of the capacitor; c. Forming a capacitor dielectric layer over the lower electrode; and d. Forming an upper electrode of the capacitor over the capacitor dielectric layer. Page 17 483121 VI. Scope of patent application 1 7. A dynamic random access memory including: a transistor, wherein the transistor is located in a trench of a semiconductor substrate and includes a source / drain region , The gate / channel region, and the source Λ and the pole extension region ', wherein the source / drain region is separated by the gate / channel region; the gate / channel region includes a channel region and A gate region, wherein the gate region is located between silicon oxide gap walls, an upper layer of the gate region is adjacent to an isolation layer, a gate dielectric layer is adjoined below, and the gate dielectric layer is adjoined The semiconductor || substrate; the source / drain extension region covers the silicon oxide spacer to connect the source / dead region and the channel region; a capacitor, wherein the capacitor is also Located in the trench and above the isolation layer, it includes: a lower layer electrode, which is located above the isolation layer; a capacitor dielectric layer, which is located above the lower layer electrode; and an upper layer Electrode, which is located above the capacitor dielectric layer. 18. The dynamic random access memory according to item 17 of the scope of the patent application, wherein the thickness of the gate dielectric layer is between 20 angstroms and 30 angstroms. 19. The dynamic random access memory described in item 17 of the scope of patent application, Page 18 483121 6. Scope of patent application Wherein the thickness of the gate dielectric layer is less than 20 angstroms. 20. The dynamic random access memory described in item 17 of the scope of patent application, wherein the width of the trench is less than 0.1 micron.