^62132 A7 B7 五、發明說明（1 ) 發明範蜂 本發明係關於—種單電子場效電晶體及其製作方法；更 確切地說’本發明係關於以毫微米孔洞材科作為量子點或 浮閘’配合傳統積體t路製程來製作單電子場效電晶體。 先前技術背景 積體電路（1C)製程技術在過去的20年間進展神速，目前 已邁入0.15至0.18的深次微米（deep submirc〇n)世代。基於對於 電子元件體積小，更經濟及功能更強大等需求，更加快了 積體電路尺寸微縮競赛的腳步H高密度IC的傳統基 本元件场效電晶體一其製程的極限預計將於2007至2010 年來L。這是因為半導體元件電路的電子傳輸最終將面臨 物理定律中量子效應的限制，導致1C製造將無法低於0.07 微米（micrometer)。 在積體電路積集化的競賽中，另一個面臨到的主要問題 是複雜電路中的耗電量及所衍生出散熱的問題。舉例來 說’ 1毫安培(mA)電流流經截面積為200 X 200毫微米見方的 導體時，將會產生25安培/平方毫米的電流密度。傳統電 路需要傳輸非常太量的載子才可在電路中產生一最小電 流。如在記憶體dram中一個簡簡單單的位元其背後所代 表的是100,000個電子的傳輸。而元件所消耗的功率又與形 成電流之電子數目成正比。因此，在高積集化1C應用中， 進一步地降低其電流密度是必要的。 由於上述的問題，在下個世紀初1C產業近逼量子的世界 時’單電子元件是目前認為最可能於取代積體電路中的場 一 4 _ t紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝-------- 訂-------^_ _ 經濟部智慧財產局負工消費合作社印製 經濟部智慧財產局員工消費合作杜印製 ： I 3 2 A7 _B7 五、發明說明（2 ) 效電晶體元件。這些所謂的「單電子場效電晶體（Single Electron Field Effect Transistor，SEFET)」元件是基於「庫俞阻斷效 應（Coulomb Blockage Effect)」的物理學原理所發展出來的。 在傳統的場效電晶體中，閘極電極控制自源極流至汲極 的電流。而早電子場效電晶體的不同處在於一其包含一個 量子點或浮問，而僅以一穿隧位能障礙（量子井，Quantum well)連接於源極與汲極之間；即單電子場效電晶體所仰賴 的是電子電荷的量子化。倘若此浮閘夠小，因為需要充電 電能（庫侖能量）e2 / 2C，僅管只是想多加上一個電子也不 行，所以也就不會有電流的流動。電晶體可經由於閘極外 加正向電壓降低浮閘的位能而打開。若固定閘極電壓而改 變源極-汲極電壓，這會導致源極-汲極電流作階梯狀的增 加（即所謂的庫命階梯，Coulomb-staircase)。因此，當給予源 極負電壓時，使得電子位能大於e2/2C，造成浮閘近源極 侧位能障壁較低，單一個電子可穿透低能量障壁而進入此 浮閘，此時浮閘之量子井的電位能（potential energy)升高，使 第二個電子不能進入，即為所謂的「庫倫阻斷」。當浮閘 之量子井的電位能升高時，相對的右邊的位能障壁則降 低，此時電子將可從浮閘穿透右邊的位量障壁進入另一接 合線到汲極，如此反覆循環，形成在浮閘内，一次只能通 過一個電子f因之稱為卓電子電晶體。單電子場效電晶體 具低消耗功率及高密度組裝之優點，若與現今之場效電晶 體搭配使用，則可擁有高速率、低消耗功率與高元件密度 之積體電路。 -5 - 本紙張尺度適用ΐ囤國家標準（CNSM4規格（210x297公釐） ------------ ----I I I - ------— -峻 (請先閱讀背面之注意事項再填寫本頁) 2 13 2 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 Μ 子元件的量子 Α7 Β7 五、發明說明（3 ) 在應用上，由於單電予電晶體源汲極間的電流，一次只 能通過一個電子’因此其將可探討量子力學内最基礎的問 題’並能作為極佳之基礎物理研究用的元件。除了做基礎 科學之探討外’單電子電晶體亦為具應用價值的電子元 件，如其為最靈敏的電荷感應器，所以在很多情況下，它 能取代目前場效電晶體的功能，並可作低雜訊的光學感測 器。又因其電子電荷是量化的，故其線路可用來做邏輯運 算的單元’也是做記憶體元件的最佳資源。此外，單電子 電晶體因能利用加在閘極的電壓大小來「鎖住」一個一個 電子通過的頻率’故也可以作為「標準電流器」。 然而，庫侖阻斷效應只能在電容值非常低的元件中觀察 得到。這是由於熱動能（kT)會造成干擾，幫助電子穿透位 能井，減低了阻斷的效果。因此，充電能量必需遠大於熱 動能值，即 kT < < e2 / 2C 其中C為元件的電容 所以’為了要於室溫下㈣此—元件的特性需求，所涉 及的電容(C)必需低至10-1«法拉第(F)。即，物體的尺寸必需 不可超過幾個奈米（5奈米）’這是無法以傳統微影技術甚 或電子直寫（directwnte)(解析度约10至2〇奈米）所能達成的解 析度。 發明概述 本發明的目的是要利用毫微米孔洞材料 十技術（或觸媒製作 技術），並與傳統半導體製程技術梦人 P 發展出一套嶄新 的方法’製作單電子場效電晶體等半導體量 ~ 6 - 本紙張尺度朋中關家標準（CNSM4規格（210 X 297公复)— -------I I--- ------ H ^ ---!!^, 《請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明說明（ ”占或浮閘此方法可以突破現今利用微影或光束製作量子 點或浮閘在解析度上的限制，達成此元件在室溫下應用的 終極目的。 種單電子場效電晶體的製作方法，包括下列步驟：利 用薄膜沈積^化成長及微影、姓刻、熱擴散及離子佈植 等技術產生電晶體之閘極、源極及汲極；#源極與汲極之 間有一個極微小的接合線（lead)連接；在此極微小的接合線 中，利用微影及蚀刻技術製作一窗口；在此窗口利用旋轉 覆蓋法（spin coating)填入毫微米尺寸孔洞材料；將沈積在其 他位置之毫微米孔洞材料去除；沈積介電層於已形成電晶 體之晶片表面；再接著製作後段之製程如微影、蝕刻及金 屬化；最後沈積純化保護層。 本發明之優點在於： 1.毫微米孔洞材料為二氧化矽及金屬導體，均為半導體製 程常用之材料，符合積體電路元件製程之要求。 而 % 2 ·本發明所使用之旋轉覆蓋法及舉離或化學機械磨法，將 尾微米孔洞材料沈積在特定位置，此三製程技術皆為成 熟且產業量產之技術，將可改善使用電子束（E_beam)微 影技術製作次笔微米尺寸（sub_nanometer)量子點有解析度 Ο.ίμηι之極限及非常耗時之缺點，達到〇 〇IjLun(1〇nm)的境 界。故本發明乃為充份利用現有之技術予以改良，達到 全新的附加效果一即是突破了現今單電子電晶體製程上 對量子點製作解析度的限制^ —般5〇nm的量子點其操作 溫度為4K ’而目前全世界最高的報告溫度為77κ -1 - 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公釐） ."62132 經濟部智慧財產局員J-消費合作社印製 元件符號斜照类 201 矽基板 202 埋入層 203 源極 204 汲極 205 接合線 206 窗口 A7 --------B7_____ 五、發明說明（5 ) 本發明的解析度可達10nm，理論上之適用的溫度為室 溫。 3 本發明之孔洞材料可塞入原子大小的金屬或碎，又因孔 洞材料排列整齊，晶體排列完美，可進一步探討電子、 電洞的物理性質。 4 ·本發明所利用之毫微米孔洞材料可預先大量合成，再以 旋轉覆蓋法塗上，產能大，符合積體電路製程的需求。 經由以下的對應圖示與發明詳述，本發明的其他特徵及 優點將會更加地明顯。 圖式之簡軍銳明 圖1為卓電子場效電晶體結構的透视圖。 圖Μ至2D為形成本發明之量子點或浮閱的連續步驟透視 圖□ 圖3為本發明之第一種量子點或浮閘結構；其中圖认為 沿3Α-3Α直線剖面圖，而圖3Β則為沿3Β_3Β直線剖面圖。 圖4為本發明之第二種量子點或浮閘註 β m D耩，其中圖4Α為 沿3A-3A直線剖面圖，而圖4B則為沿3B_3B直線剖面圖。 -8 — 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------Μ--------訂---------峻. (請先閲讀背面之注意事項再填寫本頁)^ 62132 A7 B7 V. Description of the invention (1) Invention of the invention The invention relates to a single-electron field-effect transistor and a method for manufacturing the same; more specifically, the invention relates to the use of nanopore materials as quantum dots or The “floating gate” is used to manufacture single-electron field-effect transistor with the traditional integrated t-channel process. Prior technology background Integrated circuit (1C) process technology has made rapid progress in the past 20 years, and has now entered the deep submicron (0.15 to 0.18) generation. Based on the demand for smaller electronic components, more economical and more powerful functions, the pace of the scale-down of integrated circuit size has been accelerated. The traditional basic element field-effect transistors of high-density ICs-the limits of their processes are expected to reach 2007 to L since 2010. This is because the electronic transmission of semiconductor element circuits will eventually face the limitation of quantum effects in the laws of physics, so that 1C manufacturing will not be able to go below 0.07 micrometers. In the competition of integration of integrated circuits, another major problem is the power consumption in complex circuits and the resulting heat dissipation problems. For example, when a 1 milliampere (mA) current flows through a conductor with a cross-sectional area of 200 x 200 nanometer squares, it will produce a current density of 25 amps per square millimeter. Traditional circuits need to transmit a very large number of carriers to generate a minimum current in the circuit. A simple bit in a memory dram is represented by the transmission of 100,000 electrons. The power consumed by the component is directly proportional to the number of electrons forming the current. Therefore, in high accumulation 1C applications, it is necessary to further reduce its current density. Due to the above problems, when the 1C industry is approaching the quantum world at the beginning of the next century, 'single electronic components are currently considered to be the most likely to replace the fields in integrated circuits. A 4 _t paper scale applies the Chinese National Standard (CNS) A4 specification 210 X 297 mm) (Please read the precautions on the back before filling out this page) -------- Order --------- ^ _ _ Printed by the Ministry of Economic Affairs, Intellectual Property Office, Consumer Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation Du printed: I 3 2 A7 _B7 V. Description of the invention (2) Efficient transistor element. These so-called “Single Electron Field Effect Transistor (SEFET)” components were developed based on the physics of the “Coulomb Blockage Effect”. In traditional field effect transistors, the gate electrode controls the current flowing from the source to the drain. The early electron field-effect transistor is different in that it contains a quantum dot or float, and is only connected between the source and the drain by a tunneling potential barrier (quantum well); that is, a single electron The field effect transistor relies on the quantization of electronic charge. If the floating gate is small enough, because it needs to be charged with electric energy (Coulomb energy) e2 / 2C, it is not enough to just add one more electron, so there will be no current flowing. The transistor can be turned on by applying a forward voltage to the gate to reduce the potential of the floating gate. If the gate-voltage is fixed and the source-drain voltage is changed, this will cause the source-drain current to increase stepwise (the so-called Coulomb-staircase). Therefore, when a negative voltage is applied to the source, the potential energy of the electron is greater than e2 / 2C, resulting in a low potential barrier near the source side of the floating gate. A single electron can penetrate the low energy barrier and enter the floating gate. The potential energy of the quantum well of the gate rises, preventing the second electron from entering, which is the so-called "Coulomb block". When the potential energy of the quantum well of the floating gate rises, the potential barrier on the right side decreases. At this time, electrons can pass from the floating gate to the right barrier barrier and enter another bonding line to the drain electrode. , Formed in the floating gate, can only pass one electron f at a time, so it is called Zhuo electron transistor. Single-electron field-effect transistors have the advantages of low power consumption and high-density assembly. If used with today's field-effect transistors, they can have integrated circuits with high speed, low power consumption, and high component density. -5-This paper size applies to the national standard (CNSM4 specification (210x297 mm) ------------ ---- III----------Jun (Please read first Note on the back, please fill out this page again) 2 13 2 Quantum A7 B7 printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Co-operative Sub-components V. Description of the invention (3) In the application, due to the Electric current can only pass through one electron at a time 'so it can explore the most fundamental problems in quantum mechanics' and can be used as an excellent element for basic physics research. In addition to doing basic scientific research, single electron transistors are also Electronic components of application value, such as the most sensitive charge sensor, so in many cases, it can replace the function of the current field effect transistor and can be used as a low-noise optical sensor. Because its electronic charge is It is quantified, so its circuit can be used as a unit for logic operations. It is also the best resource for memory elements. In addition, the single-electron transistor can "lock" the voltage passed to the gate to "lock" one electron through Frequency Can be used as a "standard current device". However, the Coulomb blocking effect can only be observed in components with very low capacitance values. This is because thermal kinetic energy (kT) can cause interference, helping electrons to penetrate potential energy wells and reduce resistance. Therefore, the charging energy must be much larger than the thermal kinetic energy value, that is, kT < < e2 / 2C where C is the capacitance of the element, so 'for this at room temperature—the characteristics of the element, the capacitance involved (C) Must be as low as 10-1 «Faraday (F). That is, the size of the object must not exceed a few nanometers (5 nanometers). This is impossible to use traditional lithography technology or even electronic directwnte (analysis Resolution of about 10 to 20 nanometers). SUMMARY OF THE INVENTION The purpose of the present invention is to use nano-hole material technology (or catalyst manufacturing technology), and to develop with traditional semiconductor process technology Dreamman P A new set of methods' making single-electron field-effect transistors and other semiconductor quantities ~ 6-This paper standard Pengzhongguanjia standard (CNSM4 specification (210 X 297 public reply) — ------- I I --- ------ H ^ --- !! ^, "Please read the back Please fill in this page on the matters needing attention) A7 B7 V. Description of the invention ("occupation or floating gate" This method can break the limitation of the resolution of quantum dots or floating gates using lithography or light beams at present, and achieve the application of this element at room temperature The ultimate purpose of this invention is to produce a single-electron field-effect transistor, including the following steps: using thin-film deposition, growth, and lithography, lithography, thermal diffusion, and ion implantation to generate the gate, source, and Drain pole; # There is a very tiny bond wire connection between the source and the drain electrode; in this tiny bond wire, a window is made using lithography and etching technology; in this window, the rotation overlay method is used ( spin coating) filling nanometer-sized hole materials; removing nanometer hole materials deposited at other locations; depositing a dielectric layer on the surface of a wafer on which a transistor has been formed; and then manufacturing subsequent processes such as lithography, etching, and metallization ; Finally, a purified protective layer is deposited. The advantages of the present invention are: 1. The nanometer hole material is silicon dioxide and a metal conductor, both of which are commonly used in semiconductor manufacturing processes, and meet the requirements of integrated circuit element manufacturing processes. % 2 · The rotary covering method and lift-off or chemical mechanical grinding method used in the present invention deposit tail micron hole materials at specific locations. These three process technologies are all mature and industrial mass production technologies, which will improve the use of electronics. E-beam lithography technology produces sub-nanometer quantum dots with a resolution limit of 0.1 μm and a time-consuming disadvantage, reaching the realm of OOIjLun (10nm). Therefore, the present invention is to make full use of the existing technology to improve, to achieve a brand-new additional effect. One is to break through the limitation of the resolution of quantum dots in the current single-electron transistor manufacturing process. The operation of quantum dots in general 50nm The temperature is 4K 'and the world's highest reported temperature is 77κ -1-This paper size applies the Chinese national standard (CNSM4 specification (210 X 297 mm). 62132 J-Consumer Cooperative Co., Ltd. Printed Components Symbol oblique type 201 silicon substrate 202 buried layer 203 source 204 drain 205 bonding wire 206 window A7 -------- B7_____ V. Description of the invention (5) The resolution of the present invention can reach 10nm, in theory The applicable temperature is room temperature. 3 The pore material of the present invention can be inserted into atom-sized metal or broken, and because the pore material is arranged neatly and the crystal is perfectly arranged, the physical properties of electrons and holes can be further explored. 4 · The present invention The nano-hole material used can be synthesized in large quantities in advance, and then coated by the spin coating method, which has a large production capacity and meets the requirements of integrated circuit manufacturing processes. Through the corresponding diagrams and inventions below As mentioned above, other features and advantages of the present invention will be more apparent. Figure 1 is a sharp view of the structure of the Zhuo electron field effect transistor. Figures M to 2D are the continuous steps of forming the quantum dot or floating of the present invention. Perspective view □ Figure 3 is the first quantum dot or floating gate structure of the present invention; of which the view is taken along the line 3A-3A, and Figure 3B is taken along the line 3B_3B. Figure 4 is the second view of the present invention. A kind of quantum dot or floating gate injection β m D 耩, in which FIG. 4A is a cross-sectional view taken along a straight line 3A-3A, and FIG. 4B is a cross-sectional view taken along a straight line 3B_3B. -8 — This paper scale applies to the Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) ------------ M -------- Order --------- Jun. (Please read the precautions on the back first (Fill in this page)
A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 207 毫微米孔洞材料 208 閘極 209 介電層 401 $夕基板 402 埋入層 405 接合線 407 浮閘 408 閘極 409 介電層 發明詳述及優先實施例 基本上，本發明之單電子場效電晶體積體電路製作方法 可粗分為三段製程：前段製程為金氧半場效電晶體半導體 (MOSFET)的傳統製程；中段製程為將利用水熱法與離子= 換法所產生I晕微米孔洞材料製成電晶體中的量子點或浮 閘；而後段製程為則為多層金屬化與最外層鈍化製程。因 前段與後段製程為習知技術，在此僅針對本發明特有之技 術加以描述，以使熟悉此項技術者能夠據以實施。 實例1 本發明疋單電子電晶體元件結構與金氧半場效應電晶體 類似，具有源極（Source)，汲極（Drain)及閘極（Gatep除此之 外’此單電子電晶體尚含有一浮閘（Fi〇ating讲拉），見圖I。 本發明製作此浮閘的步驟為，首先藉由傳統之m〇sfe丁製程 (如薄膜沈積、氧化成長及微影、蝕刻、熱擴散及離子佈 植等技術），先在矽基板（substrate) 2〇ι與埋入層（buried layer) 2〇2 ----- _ 9 - 本鄕家標準（CNSM4規格 (21CU297 公釐） fl^i n n n I a^l r ^-OJ tf ί J ί I I (請先閱讀背面之注意事項再填寫本頁) 4 1 3 2 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 上形成源極203與汲極2〇4，並且於源極203與汲極204間留 下一細微的矽質接合線（lead) 2〇5 (圖2A )。接著，如圖2B所 不’利用微影及蝕刻技術，在此接合線2〇5中製作一窗口 206。 然後’利用旋轉覆蓋法（spjn c〇ating)填入預先製成的毫 微米孔洞材料，以形成圖2C中的毫微米孔洞材料薄膜 207。 而圖2D則顯示於浮閘或量子點製成後，其上閘極2〇8 所形成的位置。圖中所填入之孔洞材料高度、接合線等之 比例並不代表其實際相關的尺寸。 圖3為本例中所形成之多量子點浮閘2〇7的剖面圖。圖3A 疋沿圖1中《3A - A直線的剖面圖，而圖3B則為沿3B _ 3B直 線的剖面圖。所形成之浮閘2〇7上已顯示有介電層2〇9 (未示 於圖1與圖2D中）及閘極208，而圖3B中尚可見到矽質接合 線205。而填入之毫微米孔洞材料可包含兩類材料：微孔 洞（micr〇P〇職）材料（孔洞直徑約〇 3〜丨唧）及中孔洞（mes〇p〇麵) 材料（孔洞直徑約2-10mn)。此兩類材料的合成機構是不同 的，而目前多以粉末的型式合成。微孔洞材料可先以水熱 法製作出含亳微米顆粒的溶液，再以旋轉覆蓋法製作薄 膜，但t孔洞材料則在室溫下就可以K匕碎㈣㈣薄膜 的模板化聚合作用加以合成0s|ature，39〇, 674_676, 1997)。 實例2 圖4顯示本發明之單電子場效電晶體浮閘的另一種可能 結構。於圖4中，同圖丨及圖2所示，其底層結構為矽基板 401及埋入層402，而浮閘407的上方也同樣具有介電層4〇9 及閘極408。不同的是，此例中的亳微米孔洞材料薄膜是 -10 - 本纸張尺度適用中國國家標準（CNSM4規格（210 X 297公髮) --------- ---------- I --------訂----- 1 1 · . (請先閱讀背面之注咅？事項再填寫本頁) 462132 經濟部智慧財產局員工消费合作社印製 A7 五、發明說明（8 )A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6 207 nanometer hole material 208 gate 209 dielectric layer 401 $ evening substrate 402 buried layer 405 bonding wire 407 floating gate 408 gate 409 dielectric Detailed description of the invention and preferred embodiments Basically, the method for manufacturing the single-electron field-effect transistor bulk body circuit of the present invention can be roughly divided into three stages: the front stage is a traditional process of metal-oxide-semiconductor field-effect transistor (MOSFET); The mid-stage process is to make quantum dots or floating gates in transistors using the I-halo micron hole material produced by the hydrothermal method and the ion = exchange method; the latter stage is a multi-layer metallization and outermost passivation process. The latter process is a conventional technology, and only the technology unique to the present invention will be described here so that those skilled in the art can implement it. Example 1 The structure of a single electron transistor of the present invention is similar to that of a metal-oxide half-field effect transistor. It has a source, a drain, and a gate (other than Gatep). This single-electron transistor also contains a floating gate (FiOating), see Figure I. The steps for making the floating gate according to the present invention are: firstly, using a traditional mOsfe process (such as thin film deposition, oxidative growth and lithography, etching, thermal diffusion, and ion implantation), first on a silicon substrate (substrate) 2〇ι and buried layer 2〇2 ----- _ 9-Original standard (CNSM4 specification (21CU297 mm) fl ^ innn I a ^ lr ^ -OJ tf ί J ί II ( Please read the notes on the back before filling this page) 4 1 3 2 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (source 203 and drain 208 are formed on A minute silicon lead (205) is left between the drain electrodes 204 (FIG. 2A). Then, as shown in FIG. 2B, a window is formed in this bond wire 205 using lithography and etching techniques. 206. Then 'spjn coating' is used to fill the pre-made nano-hole material to form the nano-hole material film 207 in FIG. 2C. And FIG. 2D is shown in a floating gate or quantum dot system. After it is completed, the position of the gate electrode 208 formed by it. The height of the hole material filled in the picture, the bonding line, etc. The example does not represent its actual related dimensions. Figure 3 is a cross-sectional view of the multiple quantum dot floating gate 207 formed in this example. Figure 3A 的 A cross-sectional view taken along the line 3A-A in Figure 1, and Figure 3B It is a cross-sectional view taken along the line 3B _ 3B. A dielectric layer 209 (not shown in FIG. 1 and FIG. 2D) and a gate electrode 208 have been shown on the floating gate 207 formed. A silicon bonding wire 205 is visible. The filled nano-hole material can include two types of materials: micro-hole (micr0P0) material (hole diameter of about 03 ~ 丨 〜) and middle-hole (mesop0 surface) material (hole diameter of about 2-10mn). The synthesis mechanisms of these two types of materials are different, and most of them are currently synthesized in powder form. Microporous materials can be hydrothermally made into solutions containing 亳 micron particles, and then spin-coated to make films, but t-hole materials can be synthesized by templating polymerization of ㈣㈣ films at room temperature. 0s | ature, 39〇, 674_676, 1997). Example 2 Fig. 4 shows another possible structure of the single-electron field effect transistor floating gate of the present invention. In FIG. 4, as shown in FIG. 1 and FIG. 2, the underlying structure is a silicon substrate 401 and a buried layer 402, and a dielectric layer 409 and a gate electrode 408 are also provided above the floating gate 407. The difference is that the 亳 micron hole material film in this example is -10-This paper size applies to the Chinese national standard (CNSM4 specification (210 X 297)) --------- ------ ---- I -------- Order ----- 1 1 ·. (Please read the note on the back? Matters before filling out this page) 462132 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (8)
直接塗佈於接合線4〇5之上，而沒有於接線中蝕刻出窗口 的步驟。圖4A與圖4B分別為類似圖卜沿中3Α·3Α與3B_3B 直線的剖面圖。 利用笔微米孔洞材料薄膜中的亳微米孔洞’再藉由離子 交換的方式，可填入鈀（Pd)、鉑（pt)等導電性的金屬材料， 進而各別形成量子點。毫微米尺寸的金屬也可以在合成毫 微米孔洞材料的配方中就直接添加。中孔洞材料則直接以 配方旋轉覆蓋製成薄膜。上述之水熱法、離子交換法等製 作毫微米孔洞材料均為已知的技術，在此就不多作贅述。 藉孔洞材料（為絕緣體silica)形成能障咖㈣制bajTier)，而以 其内填入之金屬構成量子點。因為無論是以直接合成或是 離子夂換法，毫械米尺寸金屬的長度都可控制在毫微米以 下，所以，毫微米孔洞材料的位向就不必控制。而且，因 其孔洞材料中之金屬尺寸均可控制在毫微米以下，所以藉 由此法所形成之量子點或浮閘其電容就極小。一般來說， 為了要產生庫倫阻斷效應，則必需避免熱能幫助電子穿透 而減弱了庫倫阻斷的特性，或造成多餘電子數的熱波動。 因此充電能I必須遠大於載子（Carrier)的熱能。理論上，若 想要將操作溫度提高至室溫，其電容必須要小於i(rl8法拉 第（F)，而；&要使電容降低，則浮閘尺寸必須小於直徑 1〇mn甚至更小》利用本發明之製造單電子場效電晶體之方 法及其製造出之元件，正足以解決因解析度的不足而無法 產生夠小疋量子點或浮閘的瓶頸，突破了現今製程上的障It is directly coated on the bonding wire 405 without the step of etching the window in the wiring. 4A and 4B are cross-sectional views taken along lines 3A · 3A and 3B_3B, respectively, similar to FIG. By using the 亳 micron holes in the pen-micron hole material film 'and then ion-exchange, conductive metal materials such as palladium (Pd) and platinum (pt) can be filled to form quantum dots. Nanometer-sized metals can also be added directly into the formulation of nanometer-sized hole materials. The mesoporous material is directly formed into a thin film by rotary coating. The above-mentioned hydrothermal method, ion exchange method and the like for making nanometer hole materials are known techniques, and will not be described in detail here. A hole material (for insulator silica) is used to form a bajTier, and the metal filled in it constitutes a quantum dot. Because the length of millimeter metal can be controlled below nanometers no matter by direct synthesis or ion exchange method, the orientation of nanometer hole materials need not be controlled. Moreover, because the metal size in the hole material can be controlled below nanometers, the capacitance of quantum dots or floating gates formed by this method is extremely small. In general, in order to produce the Coulomb blocking effect, it is necessary to avoid thermal energy to help electrons penetrate and weaken the characteristics of Coulomb blocking, or cause thermal fluctuations in the number of excess electrons. Therefore, the charging energy I must be much larger than the thermal energy of the carrier. In theory, if you want to increase the operating temperature to room temperature, its capacitance must be smaller than i (rl8 Faraday (F), and; & To reduce the capacitance, the size of the floating gate must be less than 10mm or smaller in diameter. " The method for manufacturing single-electron field-effect transistor and the component manufactured by the invention are enough to solve the bottleneck of failing to generate a small quantum dot or floating gate due to the lack of resolution, and break through the obstacles in the current process.
礙D 一 11 - 本紙張聽賴巾s國家標準（CNS)A4規格（210 X 297公餐） -n I— I n n n n t— ^-eJ· n n V f (請先閱讀背面之泫意事項再填寫本頁) 4 6 2 T 3 2 A7 B7 五、發明說明（ 本發明之技㈣容及技術特點已揭示如上，然而孰采本 項技術之士仍彳基於本發明之教示及揭示而作種種不背離 本發明精神之替換及修飾；因此，本發明之保護範圍應不 限於實施例所揭示者，而應包括各種不背離本發明精神之 替換及修飾。 --I II--III— — I —訂·—！！ — —^^ <請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 2 1 本紙張尺度適用中®國家棵準<CNS>A4規格（210 * 297公釐）Obstacle D-1 11-This paper listens to the national standard (CNS) A4 specification (210 X 297 meals) -n I— I nnnnt— ^ -eJ · nn V f (Please read the notice on the back before filling This page) 4 6 2 T 3 2 A7 B7 V. Description of the invention (The technical and technical features and technical features of the present invention have been disclosed as above. However, those who have adopted this technology still make various changes based on the teaching and disclosure of the present invention. Substitutions and modifications that deviate from the spirit of the invention; therefore, the scope of protection of the invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the spirit of the invention. --I II--III--I- Order · —— ！！ — — ^^ < Please read the notes on the back before filling out this page} Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 1 This paper is applicable in the national standard of China < CNS > A4 (210 * 297 mm)