TW564505B - Single electron transistor and fabrication method thereof - Google Patents

Abstract

The single electron transistor (SET) of the present invention is fabricated by using electron beam lithography. After many times of photolithography, etching and oxidation processes, a silicon island with very small dimension is formed as the quantum well, two mutually isolated silicides or doped polysilicon spacers on both sides of the silicon island are utilized as the drain and source of the single electron transistor respectively. The silicon substrate functions as the bottom gate, so as to form a single electron transistor comprising a silicon substrate; a quantum well; a first dielectric layer; a silicon nitride layer and two spacers. The surface of the silicon substrate is an oxide layer. The quantum well is located on the oxide layer. The dielectric layer is passivated on the quantum well. The silicon nitride layer is passivated on the first dielectric layer. The two spacers are located on both sides of the quantum well. The two second dielectric layers are located between the quantum well and the spacer, which functions as the potential barrier layer between the source, drain and the quantum well of the single electron transistor.

Description

564505 A7 p —_______ B7___ V. Description of the Invention (i) MAN February Field The present invention relates to a semiconductor transistor and a method for manufacturing the same, and particularly to a method for manufacturing a single electron transistor. The background The integrated circuit (1C) process technology has made rapid progress in the past 20 years, and has now entered the nanometer (nm) generation of 0.15, 0.13, and even 0.1 micrometers (micrometers). Based on the demand for smaller electronic components, more economical and more powerful functions, the pace of the miniaturization of integrated circuit size has been accelerated. However, the high-density IC's traditional elementary field effect transistor and its process limit are expected to come from 2007 to 2010. This is because the electronic transmission of semiconductor element circuits will eventually face the limitation of quantum effects in the laws of physics, resulting in the gate width or line width of 1C cannot be lower than 0.07 μm. In the competition of integration of integrated circuits, another major problem is the power consumption in complex circuits and the resulting heat dissipation problems. For example, a current of 1 milliampere (mA) flowing through a conductor with a cross-sectional area of 200 nanometers square will result in a current density of 25 amperes per square millimeter. Traditional circuits need to transmit a very large number of carriers to generate a minimum current in the circuit. For example, a simple bit in the memory DRAM is represented by a transmission of 100, 000 electrons. The power consumed by the component is directly proportional to the number of electrons forming the current. Therefore, in high accumulation IC applications, it is necessary to further reduce its current density. Because of the above problems, when the IC industry is approaching the quantum world at the beginning of the next century, single-electronic components are currently considered to be the most likely to replace field-effect transistor components in integrated circuits. These so-called "Single Electron Transistors (Single H: \ Hu \ tys \ NDL said \ 80766 \ 80766.doc-4-This paper size applies to China National Standard (CNS) A4 (210X 297 mm) '~ Pei Ding 564505 A7 B7 V. Description of Invention (2)

"Electron Transistor (SET)" element is developed based on the physics principle of "Coulomb Blockage Effect". In traditional field effect transistors, the gate electrode controls the current flowing from the source to the drain. The single electron transistor is different in that it contains a quantum dot or a floating gate, and is only connected between the source and the drain with a tunneling potential barrier (quantum well); that is, a single electron field effect The transistor relies on the quantization of electronic charge. If this floating gate is small enough, because it needs to be charged with electric energy (Coulomb energy) e2 / 2C, it just won't work just to add one more electron, so there will be no current flowing. The transistor can be turned on by applying a forward voltage to the gate to reduce the potential of the floating gate. If the gate-voltage is fixed and the source-drain voltage is changed, this will cause the source-drain current to increase stepwise (the so-called Coulomb-staircase). Therefore, when a negative voltage is applied to the source, the potential energy of the electron is greater than e2 / 2C, resulting in a low potential barrier near the source side of the floating gate. A single electron can penetrate the low energy barrier and enter the floating gate. The potential energy of the quantum well of the gate rises, making the second electron inaccessible, which is the so-called "Coulomb block". When the potential energy of the quantum well of the floating gate rises, the potential barrier on the right side decreases. At this time, electrons can pass from the floating gate to the right barrier barrier and enter another bonding line to the drain electrode. , Formed in the floating gate, can only pass one electron at a time, so it is called a single electron transistor. Single-electron field-effect transistors have the advantages of low power consumption and high-density assembly. If used with today's field-effect transistors, they can have integrated circuits with high speed, low power consumption, and high component density. In application, due to the current between the drains of the single electron transistor source, only H: \ Hu \ tys \ NDL says \ 80766 \ 80766.doc at a time-a paper size applies to the Chinese National Standard (CNS) A4 specification ( 210X297 mm) 564505 A7 _____ B7 V. Description of the invention (3 ~ T '" Can pass an electron, so it will be able to explore the most basic problems in quantum mechanics' and can be used as an excellent element for basic physical research. In addition to discussing basic science, 'single-electron transistors are also valuable electronic components', as they are the most sensitive charge sensors, so in many cases, they can replace the current field-effect transistors and can be used as Low-noise optical sensor. Because its electronic charge is quantified, its circuit can be used as a unit for logical operations, and it is also the best resource for memory components. In addition, single-electron crystals can be used to add The voltage r of the gate “locks” the frequency at which one electron passes, so it can also be used as a “standard current”. However, the Coulomb blocking effect can only be observed in components with very low capacitance values. This It is because the thermal kinetic energy (Kt) will cause interference, help the electrons penetrate the potential energy well, and reduce the blocking effect. Therefore, the charging energy must be much larger than the thermal kinetic energy value, that is, kT < < e2 / 2C where C is the element Therefore, in order to meet the characteristics of this component at room temperature, the capacitance (C) involved must be as low as 10-18 Faraday (F). That is, the size of the object must not exceed a few nanometers ( 5 nanometers), which is a resolution that cannot be achieved with traditional lithographic techniques or even electronic direct write (resolutions of about 10 to 20 nanometers). In recent years Choi et al. "Semicond, Sci. Technol." Published "Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure". The article discloses an electron beam lithography process to make a single electron controlled by a gate. Transistor structure. However, if two discrete gates are produced by this method, the electron beam lithography H: \ Hu \ tys \ NDL says \ 80766 \ 80766.doc-6-This paper standard is applicable to Chinese national standard (CNS ) A4 size (210X297 male ) Binding line 564505 A7 _B7_ V. Description of the invention (4) The effect of the proximity effect (Proximity Effect) will cause the two gates to be too far apart (about 100nm), which will cause the quantum well capacitance of the charge to be too large, which can only be The single-charge effect was measured at a very low temperature of 1 5 X 1 (Γ 3 ° K. In addition, the gate patterns made by electron beam lithography and etching are extremely prone to asymmetry, which can cause electrical distortion. Brief description of the invention In view of this, the present invention also uses the electron beam lithography method to form a silicon island with a very small size after multiple lithography, etching and oxidation processes, with a length of less than 50 nm, a width of less than 30 nm, The height is less than 30 nm. Using metal silicide or doped polysilicon spacers isolated on both sides as the drain and source of the transistor, respectively, this method can obtain a smaller and clearer quantum well capacitor to increase the operating temperature. . Supplemented with a silicon on insulator (SOI) wafer at the bottom of the substrate as the bottom gate, or a metal or polysilicon gate on the top of it to adjust the silicon island potential to form a complete Single electron transistor. The overall process is in line with the current ultra-large integrated circuit process. It can be applied to the production of single electron transistors in the future, so it has great industrial application value. The single-electron transistor of a preferred embodiment of the present invention includes a silicon substrate, a quantum well, a first dielectric layer, a nitrided layer, and two spacers. The surface of the broken substrate is an oxide layer. The quantum well system is located on the oxide layer. The first dielectric layer covers the quantum well. The silicon nitride layer is overlying the first dielectric layer. The two spacers are located on both sides of the quantum well and serve as the source and drain of the single electron transistor, respectively. The two second dielectric layers are located between the quantum well and the gap wall, and serve as the source of the single-electron transistor. H: \ Hu \ tys \ NDL says \ 80766 \ 80766.doc " 7-This Paper size applies to China National Standard (CNS) A4 (210X 297 mm) 564505

An energy barrier between the sum pole and the gate. The f-well mentioned above may be a silicon island composed of silicon, and the two spacers may be composed of metal silicides such as titanium compounds, group silicides, or lead silicides, or doped polycrystalline silicon doped with boron, scale, or silicon. A method for manufacturing a single electron transistor according to a preferred embodiment of the present invention includes the following steps: (1) providing a silicon substrate including an oxide layer and a silicon layer on its surface; (2) using electron beam lithography and etching techniques, Make the silicon layer long; (3) Generate a first dielectric layer on the surface of the silicon layer; (4) Cover a nitride layer on the first dielectric layer; (5) Use electron beam lithography And etching technology, the silicon layer is formed into a silicon island as a quantum well of the single electron transistor; (6) two second dielectric layers are generated, which are respectively located on both sides of the silicon island; (7) covering one A polycrystalline hard layer; (8) etching the polycrystalline silicon layer to form two polycrystalline silicon spacers on both sides of the silicon island, which serve as a source and an electrode of the single electron transistor, respectively; (9) covering a metal layer; and (10) Tempering is performed to make the polycrystalline second spacer wall a metal silicide spacer wall to reduce its electrical resistance. The polycrystalline silicon spacer can also be doped with boron, phosphorus or arsenic to form a doped polycrystalline silicon spacer to reduce the resistance value to replace the metal silicide spacer. Brief description of the Phoenix style The present invention will be described in accordance with the following drawings, in which: Figure 1U), Figure 2 (a), Figure 3 (a), Figure 4, Figure 5, Figure 6 (a), Figure 7, Fig. 8 (a), Fig. 9 and Fig. 10 show the manufacturing process of the single electron transistor of the present invention; and Fig. 1 (b), Fig. 2 (b), Fig. 3 (b), Fig. 6 (b) and Fig. 8 (b) Top views of Figs. 1 (a), 2 (a), 3 (a), 6 (a), and 8 (a), respectively. H: \ Hu \ tys \ NDL says \ 80766 \ 80766.doc-8 _ This paper size is applicable to China National Standard (CNS) A4 (210X297 public love) " '' -------- 564505 V. DESCRIPTION OF THE INVENTION (Qian 10 Semiconductor element 12 SOI substrate 101 Silicon substrate 102 Buried oxide layer 103 Fragment layer 103, Silicon island 104 First dielectric layer 105 Silicon nitride layer 106 Second dielectric layer 107 Polycrystalline second layer 107 ' Polycrystalline silicon spacers 107, • spacers 108, metal layers 109, polysilicon gates 110, polycrystalline silicon pads 110, and silicide pads. Fortunately, this description will be based on the steps of the single-electron crystal process and its corresponding diagrams as follows: Referring to FIG. 1 (a), first, an oxidation second is grown on a silicon layer 10 of a SOI substrate 12 to thereby reduce the thickness of the silicon layer 10, which is originally about 50 nm, to less than 30 nm. Electron beam lithography technology etched the silicon layer 10 into long thin lines with a line width of less than 50 nm, and then used diluted hydrofluoric acid (hf) to remove the oxidized debris on the silicon layer 103 surface. The line width of layer 103 was further reduced to less than 30 nm, and a silicon substrate 101 and an embedded oxygen layer were formed. The semiconductor element 10 of the layer 102 and a silicon layer 103 is shown in the top view of FIG. 1 (^). In order to obtain clarity of the diagram and facilitate comparison with subsequent diagrams, FIG. 1 (b) Only the silicon layer 10 that is long after the etching is shown, and the broken substrate 101 and the buried oxide layer 102 are not shown. Referring to FIG. 2 (a), then the furnace tube is thermally oxidized. A first dielectric layer 104 having a thickness of 5-10 nm is formed on the surface of the silicon layer 103. H: \ Hu \ tys \ NDL says 8080 \ 80766.doc-9 ~ This paper is applicable to China National Standard (CNS) A4 (210X297 mm) 564505 A7

A silicon nitride sand layer 105 is deposited on the surface of the dielectric layer 104 to a thickness of 50 to 150 nm. Fig. 2 (b) is the top view of Fig. 2 (b). Similarly, for the sake of clarity, only the second layer 103 and the nitrided sand layer 105 covered thereon are listed. Positional relationship. Referring to FIG. 3 (b) and FIG. 3 (b) of the top view, using the electron beam lithography technology, the silicon nitride layer 105 and the first dielectric The stacked structure composed of the layer 104 and the silicon layer 103 is etched into a thin line with a length of less than 50 nanometers. At this time, the silicon layer 10 has been buried under the silicon nitride layer i 05 after these two etchings. The small block made of polycrystalline silicon is called silicon island 103, as a quantum well for a single electron crystal. The length of the Zhendao 103 ′ is less than 50nm, the width is less than 30nm or between 10-20nm, and the height is the thickness of the silicon layer 103, which is less than 30nm. FIG. 4, then enter the furnace tube again, so that the exposed silicon particles of the silicon island 〇 03 form a second dielectric layer 106 with a thickness of about 2-5 nm. Due to the principle of thermal oxidation, the second dielectric layer is formed by combining silicon on the silicon island 103 and silicon on the surface by introducing oxygen into the furnace tube. Therefore, the silicon island on the surface will be silicon After being consumed, it is necessary to further reduce the silicon island i 〇3, the volume, that is, shorten the length of the silicon island i 0 3, and form an energy barrier for electron tunneling on both sides of the silicon island 103 ′. Referring to FIG. 5, a polycrystalline silicon layer i 07 having a thickness of about 100 nm to about 300 nm is deposited. 6 (a) and 6 (b), FIG. 6 (b) is a top view of FIG. 6 (a). The polycrystalline silicon layer 10 is etched, and two polycrystalline silicon spacers 1 0 7 ′ are formed on both sides of the silicon island. Because the polycrystalline silicon layer 〇〇7 itself has a topography, the film thickness is relatively thick near the silicon island 〇〇3, so after appropriate H: \ Hu \ tys \ NDL said \ 80766 \ 80766.doc- 10 _: Wood and Paper Standards (CNS) Μ Specifications (, which public love) ~ ----------- 564505 A7

Etching over time can naturally form the polycrystalline silicon spacer wall 107. Because it does not require photoresist, and the etched structure is symmetrical, it is also called self-aligned etching *. In addition, a photoresist pattern can also be defined in advance using lithography technology, and when the polycrystalline silicon layer 107 is etched to form a polycrystalline silicon barrier wall i 0 7, two polycrystalline shattered solder pads are simultaneously formed (b 〇nding pad) 110. Because the pad 110 and the silicon island 1031 are relative positions in the lateral direction, for the convenience of explanation, they are only shown in FIG. 6 (b). Referring to FIG. 7, a physical vapor deposition method (physkal deposition (PVD)) is then used to sputter a metal layer 108 with a thickness of about 50 nm, which may be composed of metals such as titanium, hafnium, or cobalt. 8 (a) and 8 (b), FIG. 8 (b) is a top view of FIG. 8 (a). Next, a tempering process is performed, and through the diffusion and bonding of atoms between the polycrystalline silicon spacer wall 107 and the metal layer 108, a metal silicide is formed to become the spacer wall 107 as a source and a sink. This pad is used to form a silicide pad 1 1 10, which is a so-called self-aligned silicide ("aligned Sihcide 'Salicide") process to further reduce the resistance of the structure. Then, the metal layer i 08 embedded in the oxide layer 02 is removed by wet etching using a mixed solution of hydrogen peroxide (out 02) and ammonia (NH 4 0h). In addition, the partition wall 107 may also be composed of doped polysilicon. That is, the polycrystalline broken partition wall 107 is formed into doped polycrystalline silicon by using doping technology. It is not necessary to deposit the metal layer 108. The polycrystalline silicon spacers 107 can be doped with phosphorus or arsenic to form n-type silicon or boron to form p-type silicon according to the design requirements of the device. So far, the structure of the single electron transistor of the present invention has been completed, and the following is the main binding

564505

To belong to the connection process of the source, drain, and gate, it is mainly related to the mutual relationship of each element or wire on the plane of the S o substrate i 2, so the top view of the semiconductor device 10 is used to explain it directly. Referring to FIG. 9, a lithography and subsequent etching steps will be used as the source and drain of the silicon island! The spacers on both sides of 〇 3 ′ are isolated, and the source and drain of the transistor are respectively connected to the silicide pad 1 1 ′ ′ lacking a conductive path to avoid a short circuit. Referring to FIG. 10, finally, a conventional semiconductor process technology is used to fabricate an upper polysilicon gate 109, a contact, and a subsequent metal wire connection process. The terminals of the semiconductor element 10 are externally connected with metal wires. , And complete the production of a single electron transistor. In fact, the silicon substrate can also be directly used as a gate electrode to adjust the potential of the silicon island. The above embodiment uses a S 0 I substrate to make a single electron transistor. In fact, it can also be replaced by a silicon substrate formed by directly growing an oxide layer with a thickness of 200.300 nm on a silicon wafer, in other words As long as it is a silicon substrate with an oxide layer on the surface, it can be used. The first dielectric layer 104 and the second dielectric layer 106 may be composed of silicon oxide. The technical content and technical features of the present invention are disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and are covered by the following patent application scope. H: \ Hu \ tys \ NDL says \ 80766 \ 80766.doc-12- 7 Paper size is suitable for financial affairs and family (⑽) ^ Specifications

Claims (1)

564505 A8 B8 C8 D8 VI. Patent application scope 1 · A single electron transistor including: Shi Xi substrate 'the surface of which is an oxide layer; a quantity of wells located on the oxide layer; a first dielectric layer, covering On the quantum well; a silicon nitride layer covering the first dielectric layer; two gap walls, located on both sides of the quantum well, respectively serving as a source and a drain of the single electron transistor; and two second A dielectric layer is located between the quantum well and the gap wall, and serves as an energy barrier layer between the source and the drain of the single electron transistor and the quantum well, respectively. 2. The single-electron transistor according to item 丨 of the patent application, wherein the silicon substrate is a S 0 I substrate. 3. The single-electron transistor according to item 1 of the patent application, wherein the quantum well is a silicon island composed of silicon. 4. The single-electron transistor according to item 3 of the patent application, wherein the silicon island has a length of less than 5 Onm, a width of less than 3 Onm, and a height of less than 30 nm. 5. The single electron transistor of claim 1 in the patent scope, wherein the spacer is composed of a metal silicide. 6. The single-electron transistor according to item 1 of the application, wherein the spacer comprises one of titanium silicide, tantalum silicide, and cobalt silicide. 7. The single-electron transistor according to item 1 of the application, wherein the spacer is composed of doped polycrystalline silicon. 8. The single-electron transistor according to item 7 of the application, wherein the doped polycrystalline silicon is doped with one of phosphorus, arsenic, and boron. H: \ Hu \ tysVNDL says \ 80766 \ 8〇766d〇e-13 _ This paper size applies to the fii ^ _ (CNS) A4 specification 4χ Norwegian & 'Please read M. Cautions on the back before filling this page )-------- ^ --------- ^ I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 564505 8888 ABCD VI. Scope of patent application 9 · If the list of item 1 of the scope of patent application An electronic transistor in which the electrical layer is composed of silicon oxide. 10. The single electric pre-transistor according to item 1 of the patent application, wherein the thickness of the electric layer is between 5 and 100 nm. ii. The single-electron transistor according to item i of the patent application, wherein the thickness of the nitride layer is between 50-150 nm. For example, the single-electron transistor of the scope of application for item i, wherein the second electrical layer is composed of silicon oxide. 13. The single-electron transistor according to item i of the application, wherein the thickness of the second electrical layer is between 2-5 nm. 1 4 · A method for manufacturing a single electron transistor, including the following steps: · Provide a broken substrate including an oxide layer and a silicon layer on the surface. The electron beam lithography and etching technology are used to make the silicon layer a dielectric silicon dielectric. ('Please read the note on the back? Matters and then fill out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Makes a long strip of a first dielectric layer on the surface of the silicon layer; Layer on the first dielectric layer; using electron beam lithography and etching technology to form the silicon layer-island; y silicon generates two second dielectric layers, which are located on both sides of the silicon island, respectively, covering one Polycrystalline silicon layer; contacting the polycrystalline stone layer to form two polycrystalline broken spacers on both sides of the sand island; covering a metal layer; and tempering the polycrystalline silicon spacer into a metal silicide gap H: \ Hu \ tys \ NDL says \ 80766 \ 80766.doc _ _ 14 · Private paper standards are applicable to China National Standard (CNS) A4 (210 X 297 public) Α »Β8 C8 D8 Scope of patent application Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 15 · The method for manufacturing a single-electron crystal according to item 14 of the scope of patent application, wherein the thickness of the polycrystalline silicon layer is between 100 and 30 () nm. 16. The method for manufacturing a single electron transistor according to item 14 of the application, wherein the metal layer is formed by a physical vapor deposition method. 17. The method for manufacturing a single-electron crystal according to item 14 of the application, wherein the metal layer is composed of one of titanium, a button, and cobalt. 18 · The method for manufacturing a single electron transistor according to item i 4 of the scope of patent application, wherein the thickness of the metal layer is greater than 50 nm. 19 · The method for manufacturing a single-electron crystal according to item 4 of the patent application, wherein the thickness of the silicon layer is less than 30 nm. 20 · The method for manufacturing a single-electron transistor according to item 4 of the patent application, wherein the silicon layer is further subjected to a surface oxidation step to reduce its thickness. 21. The method for manufacturing a single-electron crystal according to item 14 of the patent application, wherein the silicon layer is further subjected to a hydrofluoric acid etching step to reduce its width. …, 22 · The method for manufacturing a single electron transistor according to item 14 of the application, wherein when the polycrystalline broken layer is etched to form the polycrystalline intercrystalline broken wall, two solder pads are also formed at the same time. 23. The method for fabricating a single electron transistor according to item 14 of the application, further comprising a wet etching step to remove the metal layer from the hafnium oxide layer. 24_ If the method for manufacturing a single electron transistor according to item 14 of the scope of the patent application, it further comprises-lithography and etching steps to separate the two conductive walls of the conductive H: \ Hu \ tys \ NDL said \ 80766 \ 80766 .dnr. _ ^-This paper size _ top _ fresh (CNS) A4 inspection (become a Norwegian ^ (Please read the precautions on the back before filling in this page) 564505 Sixth, the scope of application for patents is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A. The production of a single electric transistor in the scope of the patent No. 14 is required. , Floor. < ^ Silicon 26. If the producer of the single-electron crystal of item 14 of the patent application, where the thickness of the first dielectric layer is between, 27. Among the crystals, the second dielectric layer is an oxidative oxidation method formed by thermal oxidation. 28. For example, the method for manufacturing a single-electron crystal in the scope of application for patent No. 14 is a method in which the thickness of the second dielectric layer is At 2_5nm.彳 '29. The method for manufacturing a single-electron transistor according to item 14 of the application, wherein the polycrystalline silicon spacer is made by a self-aligned etching method. 3 0 · — A method for manufacturing a single electron transistor, including the following steps: providing a silicon substrate including an oxide layer and a silicon layer on the surface; using electron beam lithography and etching technology to form the broken layer into a shape; generating A first dielectric layer on the surface of the silicon layer; covering a silicon nitride layer on the first dielectric layer; using electron beam lithography and etching technology to form the silicon layer—Miao Island; generating two second dielectrics Electrical layers, which are located on the two sides of the silicon island, respectively, and covered with a polycrystalline debris layer; I engraved the polycrystalline layer to form two polycrystalline sand barriers on both sides of the dream island; and -16-_H : \ Hu \ tys \ NDL said \ 80766 \ 80766.doc-16 _ This paper size applies the Zhongguanjia standard (CN $ A4 specification (21 () x297)) (please read the note P on the back before filling (This page) ¾. ------- Order --------- I 564505 B8 C8 D8 Sixth, the scope of the patent application is doped with the polycrystalline silicon spacer, making it a doped polycrystalline silicon gap 031. For example, a method for manufacturing a single-electron transistor in the scope of patent application No. 30, wherein the doped polycrystalline silicon spacer is doped with one of boron, phosphorus, and arsenic. 0 Γ • Read the first reading of the Notes on the back to fill out this page) book --------- line! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs H: \ Hu \ tvs \ NDL said 8080 \ 80766.doc 17- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)