A7 B7 461041 五、發明説明（） 發明領域 本發明是有關於一種半導體元件之製造方法，且特別 是有關於一種無邊界接觸窗(Borderless Contact)的形成方 法。 發明背景 在以往半導體尙未進入深次微米(Deep Sub-Micron)的 製程時，半導體製程之臨界尺寸(Critical Dimension; CD) 較大。因此在形成接觸窗（Contact)或插塞(Plug)時，即使 晶片在微影（Photo Lithography)製程發生對位誤差，但仍 能使接觸窗或插塞落於（Landing)其原先所要形成之位置 上。亦即即使考慮對準誤差，插塞仍可完全位於下層之金 屬線上，因此對元件的工作能力並不會有影響。 經濟部智慧財產局員工消費合作社印製 然而當半導體製程進入深次微米級，元件製程的臨界 尺寸逐漸縮小之時，同時亦使得對位問題越來越不能被忽 視，尤其當設計出之元件尺寸大小所能容許的誤差 (Tolerance)已接近製程儀器本身所產生的誤差或甚至更小 時。所以要像以往一樣，要使所形成的接觸窗或插塞完全 落於其預定位置上，以符合深次微米級元件尺寸規範 (Specification)是相當困難的。 因此無邊界接觸窗或插塞之製造方法，已成了所有深 次微米級元件製造者競相硏發的主題之一。尤其是當多重 金屬內連線(Multi-Level Metal Interconnect)製程所堆積的 本紙張尺度適用中國國家標準（cns ) A4規格（210χ297公釐） 6 104 A7 B7 五、發明説明（） 層數愈來愈多時，如何讓每層之金屬導線與插塞能互相對 準連接，以使積體電路可以發揮功效。 習知之無邊界接觸窗之製作流程，只有使用一層氮化 .矽層做爲蝕刻停止層，但是發現電晶體之閥値電壓 (Threshold Voltage ; Vt)與汲極飽和電流（Isat)的大小常會 胃生變化。使得後續必須增加一些調整電晶體特性之製程 步驟’例如離子植入步驟，以使電晶體具有統一穩定之電 氣特性。 發里.目的駔槪沭 因此本發明的目的就是在提供一種無邊界接觸窗的形 成方法，以提升電晶體之使用壽命與穩定性__。 ..... .... ...........—. .................... 本發明之另一目的爲提供一種具有蝕刻停止複層的無 邊界接觸窗之製造方法，以使電晶體之閥値電壓與汲極飽 奧電流更加穩定且提高其均一性。 本發明所提供之方法包括在已形成有電晶體之基底上 依序形成第一蝕刻停止層、第二蝕刻停止層與介電層。然 後於介電層中形成開口，暴露出位於電晶體的其中之一源 極/汲極上之第二蝕刻停止層，接著去除暴露出之第二蝕 刻停止層與其下之第一蝕刻停止層以暴露出位於開口下之 源極/汲極。 其中上述之第一餓刻停止層例如可爲氧化砂層或氮氧 化矽層，而第二蝕刻停止層例如可爲氮化矽層。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） :---------'W ，(請先W讀背面之注意事項再填寫本頁) 4βA7 B7 461041 V. Description of the Invention (1) Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a borderless contact window. BACKGROUND OF THE INVENTION In the past, when semiconductors did not enter the deep sub-micron process, the critical dimension (CD) of the semiconductor process was large. Therefore, when a contact window or a plug is formed, even if the wafer is misaligned during the photolithography process, the contact window or the plug can still be landed in the original formation. Location. That is to say, even if the alignment error is considered, the plug can still be completely located on the underlying metal line, so it will not affect the working ability of the component. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, when the semiconductor process enters the sub-micron level and the critical dimension of the component process is gradually shrinking, the alignment problem can no longer be ignored, especially when the component size is designed. The tolerance allowed by the size is close to the error produced by the process instrument itself or even smaller. Therefore, as in the past, it is quite difficult to make the formed contact window or plug completely fall into its predetermined position to meet the deep sub-micron component size specification. Therefore, the method of manufacturing borderless contact windows or plugs has become one of the themes of all manufacturers of deep sub-micron components. Especially when the paper size accumulated in the Multi-Level Metal Interconnect process is applicable to the Chinese National Standard (cns) A4 specification (210x297 mm) 6 104 A7 B7 V. Description of the invention () The number of layers is increasing More and more, how to make the metal wires and plugs of each layer aligned and connected to each other, so that the integrated circuit can play a role. The manufacturing process of the conventional borderless contact window only uses a layer of nitride. The silicon layer is used as an etch stop layer, but the threshold voltage (Vt) and the saturation current (Isat) of the transistor are often found in the stomach.生 Change. Therefore, it is necessary to add some process steps for adjusting the characteristics of the transistor, such as an ion implantation step, so that the transistor has uniform and stable electrical characteristics. The purpose of the invention is therefore to provide a method for forming a borderless contact window to improve the lifetime and stability of a transistor. ..... .... ....................... Another purpose of the present invention is to provide A method for manufacturing a borderless contact window with an etch-stop cladding layer is used to make the valve voltage and the drain saturation current of a transistor more stable and improve its uniformity. The method provided by the present invention includes sequentially forming a first etch stop layer, a second etch stop layer and a dielectric layer on a substrate on which a transistor has been formed. An opening is then formed in the dielectric layer, exposing a second etch stop layer on one of the source / drain of the transistor, and then removing the exposed second etch stop layer and the first etch stop layer below it to expose A source / drain located under the opening. The first etch stop layer may be, for example, an oxide sand layer or a silicon nitride oxide layer, and the second etch stop layer may be, for example, a silicon nitride layer. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm): --------- 'W, (Please read the precautions on the back before filling this page) 4β
T 經濟部智慧財產局員工消費合作社印製 46 1 t A7 B7 經濟部智慧財產局員工消費合作杜印製+ 五、發明説明（） 本發明所提供之另一方法包括在至少已形成有一電晶 體基底上依序形成蝕刻停止複層、介電層。然後蝕刻介！I 層形成開口，暴露出位於電晶體其中之一源極/汲極上之 蝕刻停止複層。接著去除暴露出之蝕刻停止複層，以暴露 出位於開口下之源極/汲極。 其中上述之蝕刻停止複層包括以化學氣相沈積法所依 序形成之氮氧化矽層與氮化矽層，或者是以化學氣相沈積 法所依序形成之氧化砂層與氮化砂層。 圖式之簡單說明 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下：_ _ 第1A - 1C圖是依照本發明一較佳實施例的一種無邊 界接觸窗之製造流程剖面圖； 第2圖係繪示對以習知方法與本發明所提供方法所形 成之電晶體汲極飽和電流的測試結果； 第3圖係繪示對以習知方法與本發明所提供方法所形 成之電晶體閥値電壓的測試結果；以及 第4圖係繪示對以習知方法與本發明所提供方法所形 成之電晶體在極端惡劣環境下使用壽命之量測結果。 圖忒之標記說明_ 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公董） ----------' 裝丨I-^----丨訂 ../IV 、(請先».讀背面之注意事項再填寫本頁} 46 104 1 at B7 五、發明説明（) 100 :基底 110 :元件隔離結構， 120 :閘極 130 :源極/汲極 140 :第一触刻停止層 150 :第二蝕刻停止層 160 :介電層 170 :開口 180:導電插塞 發明之詳細說明_ 請參照第1A - 1C圖，其繪示是依照本發明一較佳實 施例的一種無邊界接觸窗之製造流程剖面圖。 經濟部智慧財產局員工消費合作社印製 請參照第1A圖，在基底100中先形成元件隔離結構 110，再於基底100上形成閘極120，並於閘極100兩側之 基底100中形成源極/汲極130。上述之元件隔離結構110 例如可爲淺溝渠隔離結構（Shallow Trench Isolation ; STI)。 接著，在基底100上依序形成第一蝕刻停止層140與 第二蝕刻停止層15〇。其中第一鈾刻停止層140之材質例 如可爲氧化砂或氮氧化砂(silicon oxynitride)，而其形成方 法例如可爲化學氣相沈積法。第二蝕刻停止層150 .之材質 例如可爲氮化矽，而其形成方法例如可爲化學氣相沈積 本紙張尺度適用中國國家標準（.CNS ) A4规格（210X297公嫠） 4 6 104 A7 B7 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明説明( 法 請參照第1B圖’在基底100上形成介電餍16〇。然 後蝕刻介電層16〇形成開口 1?0，暴露出第二触刻停止層 150。其中介電層100的材質例如可爲氧化矽，其形成方 法例如可爲化學氣相沈稹法。蝕刻介電層的方法，例如可 使用乾蝕刻法，如反應性離子蝕刻法（Reactive IQn Etching ; RIE)。在此蝕刻步驟中，利甩介電層160的材質 與第二鈾刻停止層150的材質不同，選擇對介電層16〇鈾 刻選擇率高之蝕刻劑來進行蝕刻介電層100，以使此鈾亥|| 步驟可以輕易停在第二蝕刻停止層150上。 請參照第1C圖，接著去除暴露出之第二蝕刻停止層 150與位於其下之第一蝕刻停止層140，暴露出源極/汲極 130。因爲有可能發生對準誤差之關係，所以部分之元件 隔離結構110也會暴露出來’這是無邊界接觸窗常有的現 象。然後於開口 170中沈積導電材質’例如金屬鎢、金屬 銅、摻雜多晶矽等等，形成導電插塞180。如此可使電晶 體其中之一的源極/汲極130可以經由此導電插塞180和 另一元件或電路彼此電性連接起來。 其中上述之第二蝕刻停止層15〇與第一鈾刻停止層 140之去除方法例如可爲乾蝕刻法，控制好蝕刻時間，以 免發生過度之過鈾刻(over etching)。後續完成此積體電路 之製程爲熟悉此技藝者所熟知，因此不再贅述之。· 另外還對習知之無邊界接觸窗製程與本發明所提供之 H- II 1 ------- II I IL----1 ! - I— I— I- 1: ,1T ^請先鯓讀背面之注意事項再填寫本頁} 纽劍t關家標準(CNS )以綠（210X297公釐） 4 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 無邊界接觸窗製程所完成之電晶體之電氣特性進行測試， 並將所得數據繪製在第2 - 4圖上。 請參照第2圖，第2圖係繪示對以習知方法與本發明 .所提供方法所形成之電晶體汲極飽和電流的測試結果。橫 .軸爲電晶體之汲極飽和電流（μΑ)，縱軸之單位爲累積機率 (%)。實心圓圏爲習知無邊界接觸窗製程中只使用400埃 厚的氮化矽層爲蝕刻無邊界接觸窗之蝕刻停止層之數據， 空心圓圈爲利用本發明方法以400埃厚之氧化矽/氮化矽 複層做爲蝕刻無邊界接觸窗之蝕刻停止層之數據，而#爲 利用本發明方法以400埃厚之氮氧化矽/氮化矽複層做爲 鈾刻無邊界接觸窗之蝕刻停止層之數據。 從第2圖上可以看到習知以氮化矽層爲鈾刻無邊界接 觸窗之蝕刻停止層時，電晶體之汲極飽和電流之分佈範圍 約爲1.90 - 2.40 μΑ。而以本發明所提供之方法以氧化矽/ 氮化矽複層或是氮氧化矽/氮化矽複層爲鈾刻無邊界接觸 窗之蝕刻停止層時，電晶體之汲極飽和電流之分佈範圍約 爲2.06 - 2.41 μΑ或是2·12 - 2.42 μΑ，皆比習知之分佈範 圍要小多了，而且也比較集中於較高之電流値。因此可知 應用本發明可使汲極飽和電流之均一性(uniformity)提升， 並可提升汲極飽和電流値，使電晶體的運作速度更快。 請參照第3圖，第3圖係繪示對以習知方法與本發明 所提供方法所形成之電晶體閥値電壓的測試結果。橫軸爲 電晶體之閥値電壓(V)，縱軸之單位爲累積機率(％)。實心 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I__— 111 — —' I - n ϋ I—-—訂 '(請先路讀背面之注意事項再填寫本頁) A7 B7 46 1 〇4 1 一·· " '~~ 五、發明説明（） 圓圏爲習知無邊界接觸窗製程中只使用4〇〇埃厚的氮化矽 層爲蝕刻無邊界接觸窗之蝕刻停止層之數據，空心圓圈爲 利用本發明方法以400埃厚之氧化矽/氮化矽複層做爲蝕 刻無邊界接觸窗之飩刻停止層之數據，而#爲利用本發明 方法以400埃厚之氮氧化矽/氮化矽複層做爲鈾刻無邊界 接觸窗之蝕刻停止層之數據。 從第3圖上可以看到習知以氮化矽層爲蝕刻無邊界接 觸窗之餓刻停止層時，電晶體之閥値電壓之分佈範圍約爲 0.468 - 0.562 V。而以本發明所提供之方法以氧化矽/氮化 矽複層或是氮氧化矽/氮化矽複層爲蝕刻無邊界接觸窗之 蝕刻停止層時，電晶體之汲極飽和電流之分佈範圍約爲 0.475 - 0.518 V或是0.483 - 0.514 V，皆比習和之分佈範 圍要小多了。因此可知應用本發明可使閥値電壓更爲均 一，使電晶體之電器特性更容易調整。 請參照第'4圖，第4圖係繪示對以習知方法與本發明 所提供方法所形成之電晶體在極端惡劣環境下使用壽命& 量測結果。縱軸爲電晶體之使用壽命(Lifetime ’ min)，橫 軸爲基底電流（Isub ’ ΜΑ)。實心方塊爲習知無邊界接觸窗 製程中只使用400埃厚的氮化矽層爲蝕刻無邊界接觸窗之 貪虫刻停止層之數據，實心圓圈爲利用本發明方法以400埃 厚之氮氧化矽/氮化矽複層做爲蝕刻無邊界接觸窗之蝕刻 停止層之數據。 由第4圖上可以看出，習知只有氮化矽層爲鈾刻停止 I--------'装 — -------.訂 (請先吣讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製. 度適用國家標準（CNS)M規格（210>^297公Θ ' 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 4 6 1 04 1 Α7 Β7 五、發明説明（ 層之數據直線斜率爲2.73，而依據本發明之以氮化矽/氮 氧化矽複層爲蝕刻停止層之數據斜率爲3.02。因此當電晶 體使用一段時間之後，基底電流爲臨界電流値(It，在此爲 25 μΑ )時，習知以氮化矽層爲蝕刻停止層之數據直線與臨 .界電流値之交叉點得到電晶體在極端惡劣環境下使用壽命 爲0.166年，而本發明以氮化矽/氮氧化矽複層爲蝕刻停止 層之電晶體在極端惡劣環境下使用壽命可高達0.612年， 約爲習知之3.7倍。因此可知應用本發明可以大幅提升電 晶體之使用壽命。 由上述本發明較佳實施例可知，應用本發明至少具有 下列優點。第一、可使汲極飽和電流之均一性提升，並可 提升汲極飽和電流値，使電晶體的運作速度更快。第二、 可使閥値電壓更爲均一，使電晶體之電器特性更容易調 整。第三、可以大幅提升電晶體之使用壽命。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 I. I is I! I El - — 1-- · — ml s-r V - - HI .1 HI :----=--. - -^9ί ^請先盹讀背面之注意事項再填寫本頁) ^^1適用中國國家標準（〇挪）八4規格（210父297公釐）T Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 46 1 t A7 B7 Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs + Printing 5. Description of the invention () Another method provided by the present invention includes forming at least one transistor An etching stop layer and a dielectric layer are sequentially formed on the substrate. Then etch the introduction! The I layer forms an opening, exposing an etch stop cladding layer on one of the source / drain electrodes of the transistor. The exposed etch stop layer is then removed to expose the source / drain electrodes under the opening. The above-mentioned etching stop multi-layer includes a silicon oxynitride layer and a silicon nitride layer sequentially formed by a chemical vapor deposition method, or an oxide sand layer and a nitrided sand layer sequentially formed by a chemical vapor deposition method. Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the attached drawings, the detailed description is as follows: _ _ Section 1A -Figure 1C is a cross-sectional view of the manufacturing process of a borderless contact window according to a preferred embodiment of the present invention; Figure 2 is a diagram showing the saturation current of the transistor drain formed by the conventional method and the method provided by the present invention FIG. 3 is a graph showing a test result of a transistor threshold voltage formed by a conventional method and the method provided by the present invention; and FIG. 4 is a graph showing a test result by a conventional method and the present invention. The measurement results of the service life of the transistor formed in the method under the extremely harsh environment. Explanation of the mark in Figure _ This paper size is applicable to China National Standard (CNS) A4 specification (210X297 public director) ---------- 'Installation 丨 I-^ ---- 丨 Order ../ IV 、 (Please read ». Read the notes on the back before filling in this page} 46 104 1 at B7 V. Description of the invention () 100: substrate 110: element isolation structure, 120: gate 130: source / drain 140: first The etching stop layer 150: the second etch stop layer 160: the dielectric layer 170: the opening 180: the detailed description of the invention of the conductive plug _ please refer to FIGS. 1A-1C, which are shown according to a preferred embodiment of the present invention A cross-sectional view of the manufacturing process of a borderless contact window. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics, please refer to Figure 1A. First, an element isolation structure 110 is formed in the substrate 100, and then a gate electrode 120 is formed on the substrate 100. A source / drain 130 is formed in the substrate 100 on both sides of the gate electrode 100. The aforementioned element isolation structure 110 may be, for example, a shallow trench isolation structure (Shallow Trench Isolation; STI). Next, a first etch is sequentially formed on the substrate 100. The stop layer 140 and the second etch stop layer 15. Among them, the material of the first uranium stop stop layer 140 For example, it can be oxidized sand or silicon oxynitride, and its formation method can be, for example, chemical vapor deposition. The second etching stop layer 150 can be made of silicon nitride, and its formation method can be, for example, Chemical Vapor Deposition This paper is in accordance with Chinese National Standard (.CNS) A4 specification (210X297 cm) 4 6 104 A7 B7 Ministry of Intellectual Property Bureau Printed by Consumer Cooperatives V. Description of the invention (Please refer to Figure 1B for the method. A dielectric layer 160 is formed on 100. Then, the dielectric layer 160 is etched to form an opening 1-0, and the second contact stop layer 150 is exposed. The material of the dielectric layer 100 may be, for example, silicon oxide, and a method for forming the dielectric layer 100 may be, for example, silicon oxide. It is a chemical vapor deposition method. A method of etching the dielectric layer may be, for example, a dry etching method, such as a reactive ion etching method (Reactive IQn Etching; RIE). In this etching step, the material of the dielectric layer 160 and the first layer are removed. The material of the second uranium etch stop layer 150 is different. An etching agent with a high selectivity to the uranium etch of the dielectric layer 160 is selected to etch the dielectric layer 100, so that this uranium seam can be easily stopped at the second etch stop. Layer 150. Please refer to FIG. 1C, and then remove the exposed second etch stop layer 150 and the first etch stop layer 140 below it to expose the source / drain 130. Because alignment errors may occur Relationship, so part of the element isolation structure 110 will also be exposed. 'This is a common phenomenon for borderless contact windows. A conductive material such as metal tungsten, metal copper, doped polycrystalline silicon, etc. is then deposited in the opening 170 to form a conductive plug 180. In this way, the source / drain 130 of one of the electric crystals can be electrically connected to each other through the conductive plug 180 and the other component or circuit. The method for removing the second etch stop layer 150 and the first uranium etch stop layer 140 may be, for example, a dry etching method, and the etching time is controlled so as not to cause excessive over etching. The subsequent process of completing this integrated circuit is well known to those skilled in this art, so it will not be described again. · In addition, the conventional borderless contact window process and the H-II 1 ------- II I IL ---- 1 provided by the present invention!-I- I- I- 1:, 1T ^ Please Read the notes on the back first and then fill out this page} New Swords Family Standard (CNS) in green (210X297 mm) 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Borderless contact window process The electrical characteristics of the completed transistor were tested, and the resulting data was plotted on Figures 2-4. Please refer to FIG. 2. FIG. 2 shows test results of the drain saturation current of the transistor formed by the conventional method and the present invention. The horizontal axis is the drain saturation current (μA) of the transistor, and the vertical axis is the cumulative probability (%). The solid circles are data for the conventional borderless contact window manufacturing process using only 400 angstroms of silicon nitride as an etch stop for etching borderless contact windows. The hollow circles are 400 angstroms of silicon oxide / The silicon nitride layer is used as the data of the etch stop layer for etching the borderless contact window, and # is the etching of the uranium-etched borderless contact window using the 400 Angstrom silicon oxynitride / silicon nitride layer using the method of the present invention. Stop layer data. It can be seen from Fig. 2 that when the conventional silicon nitride layer is used as an etch stop layer for a uranium-etched borderless contact window, the distribution range of the transistor's drain saturation current is about 1.90-2.40 μA. In the method provided by the present invention, when the silicon oxide / silicon nitride multilayer or silicon oxynitride / silicon nitride multilayer is used as the etching stop layer of the uranium-etched borderless contact window, the drain saturation current of the transistor is distributed. The range is about 2.06-2.41 μA or 2.12-2.42 μA, which are much smaller than the conventional distribution range, and they are more concentrated on higher currents. Therefore, it can be known that the uniformity of the drain saturation current can be improved by applying the present invention, and the drain saturation current 値 can be improved, so that the operation speed of the transistor is faster. Please refer to FIG. 3. FIG. 3 shows the test results of the voltage of the transistor valve formed by the conventional method and the method provided by the present invention. The horizontal axis is the valve voltage (V) of the transistor, and the vertical axis is the cumulative probability (%). The size of the solid paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I __— 111 — — 'I-n ϋ I —-— Order' (please read the precautions on the back before filling this page) A7 B7 46 1 〇4 1 I. " '~~ V. Description of the invention () Yuan is a conventional borderless contact window manufacturing process using only a 400 Angstrom thick silicon nitride layer for etching borderless contact windows. The data of the stop layer, the hollow circle is the data of 400 Angstrom thick silicon oxide / silicon nitride multi-layer as the etched stop layer for etching the borderless contact window by the method of the present invention, and # is 400 Angstrom of the method of the present invention. Thick silicon oxynitride / silicon nitride cladding is used as the data for the etch stop layer of the uranium-etched borderless contact window. From Figure 3, it can be seen that when the conventional silicon nitride layer is used as the etch stop layer for the borderless contact window, the valve voltage distribution of the transistor is about 0.468-0.562 V. In the method provided by the present invention, when the silicon oxide / silicon nitride multiple layer or the silicon oxynitride / silicon nitride multiple layer is used as the etching stop layer for etching the boundaryless contact window, the distribution range of the drain saturation current of the transistor About 0.475-0.518 V or 0.483-0.514 V, which are much smaller than the distribution range of Xi He. Therefore, it can be known that the application of the present invention can make the valve voltage more uniform, and make the electrical characteristics of the transistor easier to adjust. Please refer to FIG. 4. FIG. 4 shows the measurement results of the service life & of the transistor formed by the conventional method and the method provided by the present invention in an extremely harsh environment. The vertical axis is the lifetime of the transistor (Lifetime ′ min), and the horizontal axis is the substrate current (Isub ′ ΜA). The solid square is the data of the conventional borderless contact window process using only 400 angstroms of silicon nitride layer as the etch stop layer for etching the borderless contact windows. The solid circles are oxidized with 400 angstroms of nitrogen by the method of the present invention. The silicon / silicon nitride multiple layer is used as the data of the etch stop layer for etching the borderless contact window. As can be seen from Figure 4, it is known that only the silicon nitride layer is engraved with uranium. I -------- 'install — -------. Order (please read the precautions on the back first) (Please fill in this page again) Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Applicable to the National Standard (CNS) M specification (210 > ^ 297) V. Description of the invention (The straight line slope of the layer data is 2.73, and the slope of the data using the silicon nitride / silicon oxynitride multilayer as the etch stop layer according to the present invention is 3.02. Therefore, when the transistor is used for a period of time, the substrate current is When the critical current 値 (It, here 25 μΑ), it is known that the data line with the silicon nitride layer as the etch stop layer is straight and pro. The intersection point of the boundary current 得到 is obtained. The service life of the transistor is 0.166 years in extreme harsh environments. In the present invention, the transistor using the silicon nitride / silicon oxynitride multiple layer as an etch stop layer can have a service life of up to 0.612 years in an extremely harsh environment, which is about 3.7 times the conventional one. Therefore, it can be known that the application of the present invention can greatly improve the transistor Service life. It can be seen from the preferred embodiments of the invention that the application of the present invention has at least the following advantages. First, the uniformity of the drain saturation current can be improved, and the drain saturation current can be increased, so that the transistor operates faster. Second, The valve voltage can be made more uniform, and the electrical characteristics of the transistor can be adjusted more easily. Third, the service life of the transistor can be greatly improved. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit Anyone skilled in the art of this invention can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. . I is I! I El-— 1-- · — ml sr V--HI .1 HI: ---- =-.--^ 9ί ^ Please read the notes on the back before filling this page) ^^ 1 Applicable to China National Standard (〇 Norwegian) 8 4 specifications (210 father 297 mm)