經濟部央標準局員工消費合作社印製 460992 C7 I------ D7 五、創作説明（] ) ' ---— 創作領域 本創作係關於-種在微電子晶片上連接複數個電壓源/ 地源打線塾和一内部電路之佈局結構，特別是關於一種利 用多層金屬電壓源/地源匯流排以連接最外圈之複數個電 壓源/地源打線墊和一内部電路之佈局結構。 創作背景 口 隨著系統單晶片（System 〇n a chip)設計方式的盛 行，-個晶片上往往具有數百個打綠塾。由於該複數個打 線勢係以機械式打線（Wlre b〇nding)的方式連接至一導 線架或-基板，其所佔據之面積不易隨半導體製程技術的 進步而予以縮小。當製程技術進入〇 25謂、〇 18請或更 精密之階段時，該數百個打線塾之寬度及其連接至該晶片 内1内部t路的複數個輸入/輸出電路之連線寬度往往是 造成該晶片整體面積無法縮小之瓶頸，該現象一般稱為打 線墊限制（pad limit)。 圖1係習知疋微電子晶片之連接該複數個打線墊和其 相對應·^内邵電路的輸入/輸出電路之佈局結構。大體而 言，一晶片1 1包含一内部電路丨3及複數個打線墊丨2，且 β内4私路1 3包含一核心電路（c 〇 r e )及對應至該複數個 打線墊12之複數個輸入/輸出電路（1/〇以“…丨）。該複數 個打線塾依其功能又可分為輸入/輸出打線塾（I / 〇 p & d )及 電壓源/地源打線墊（power/gr〇und pad)，其中該輸入/ 輸出打’’·泉塾係作為傳遞該晶片信號，而該電壓源/地源打 線墊係提供該内部電路〗3内所需之電壓源及地源。該複數Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 460992 C7 I ------ D7 V. Creative Instructions (])' ----- Creative Fields This creative department is about a kind of micro-electronic chip connected with multiple voltage sources / Layout structure of ground source wiring and an internal circuit, especially about a layout structure using a multilayer metal voltage source / ground source bus to connect the outermost circle of multiple voltage source / ground source wiring pads and an internal circuit. Creative background: With the popularization of System On Chip design, there are often hundreds of green dots on a chip. Since the plurality of bonding potentials are connected to a lead frame or a substrate in a mechanical bonding manner, the area occupied by the plurality of bonding potentials cannot be easily reduced with the advancement of semiconductor process technology. When the process technology enters the stage of 〇25, 〇18, or more precise, the width of the hundreds of wirings and the wiring width of the plurality of input / output circuits connected to the 1 internal t circuit in the chip are often This is a bottleneck that causes the overall area of the chip to not shrink. This phenomenon is commonly referred to as a pad limit. Figure 1 shows the layout structure of the input / output circuit of the conventional microelectronic chip connecting the plurality of wire bonding pads and their corresponding internal circuit. Generally speaking, a chip 11 includes an internal circuit 3 and a plurality of wire bonding pads 2 and 4 in the β private circuit 13 includes a core circuit (c ore) and a plurality of numbers corresponding to the plurality of wire bonding pads 12 Input / output circuits (1 / 〇 to "... 丨". The plurality of wire bonding wires can be further divided into input / output wire bonding wires (I / 〇p & d) and voltage source / ground source wire bonding pads ( power / grund pad), where the input / output connection is used to transmit the chip signal, and the voltage source / ground source wiring pad provides the voltage source and ground required in the internal circuit. Source. The plural
_ OP 本紙張功4用中賴多揉準（CNS ) A__ ( 21QX^U----- .訂 線、 (請先閱讀背面之注意事項再填寫本頁) .! 09 9 2_ OP This paper has 4 functions (CNS) A__ (21QX ^ U -----. Thread setting, (Please read the precautions on the back before filling this page).! 09 9 2
五、創作説明（ 經濟部中央標準局負工消费合作社印製 個打線墊1 2 士 、〇> < —端以導線電氣連接至該内部電路1 3，且 其上方以機姑士 ’娜式打線的方式連接至一導線架或一基板（圖 出）圖1之複數個打線墊係以三圈打線墊之結構（3 -tier bonding , g P a d s c h e m a t i c s)為例，即一單位打線塾 15包含三個打線墊，分別位於第一圈17、第二圈18及第 — 而任—打線墊1 2均連接.至該内部電路1 3之一輸 /出電路1 6。當—單位打線整所佔據的寬度1 4越小 時’代表在相同的晶片周長下可以容納較多的打線墊，或 疋說在相同之打線墊個數下可有效縮小該晶片之面積。換 句話說’如何有效地降低一單位打線墊所佔據之寬度1 4或 孩複數個打線墊和其相對應之内部電路13的輸入/輸出電 路之間之連線寬度，將可在看打線蟄限制的情況下有效地 縮小整個晶片之面積且降低成本。 此外’若該複數個打線墊在第一至第三圈1 7〜i 9之排 列過於緊密，該複數僻打線蟄丨2和該内部電路丨3之輸入/ 輸出卷路1 6之連.接線路之寬度將難以避免地被縮小，造成 電子遷移（electromigration)效應而影響該晶片之可靠 度（r e 1 i ab i 1 i ty )。此外’該内部電路i 3之輸入/輸出電路 1 6之寬度亦將受限’而増加其内部之實體佈局和靜電防護 在設計上之困難度。 釗作之簡要說明 本創作之第一目的係為消除目前在打線墊限制的情況 下，一晶片内之複數個打線墊會佔據該晶片較大周長之缺 點。 -5- 本紙張尺度適用中國國家揉準（CNS ) A4規格（21〇X297公釐〉 ----：---_-----' ^-------.訂------線 1 -/V- ·./( (請先閲讀背面之注意事項再填寫本頁) 6 0 9 9 2 C7 D7 經濟部中央標準局員工消費合作社印製 五、創作説明（ 本創作之第二目的係為消除目前在打線墊限制的情況 下 曰9片内之複數個打線墊和其相對應之内部電路的輸 入/輸出電路之連線線路之寬度太小之缺點。 本創作之第三目的係為消除目前在有打線墊限制的情 况下 3曰片之内邵電路的複數個輸入/輸出電路因寬度 太小而不易彀計之缺點。 為了達到上述目的，本創作提供一種在微電子晶片上 用以連接該内部電路及複數個電壓源/地源打線墊之多層 金屬私壓源/地源匯流排之饰局結橡。該你局結構係將大 多數的電壓源/地源打線墊放置於所有打線墊之最外圈， 且將該複數個電壓源/地源打線墊以至少一多層金屬電壓 源/地源匯流排予以電氣連接，再電氣連接至該内部電 路。該多層金屬電壓源/地源匯流排可被分段為複數個電 壓源/地源外部匯流排，且任一電壓源/地源外部匯流排以 至少一電壓源/地源橋接匯流排電氣連接至該晶片之内部 电路°由於該複數個電壓源/地源打線勢不須個別連接至 該内部電路，而係以至少一多層金屬電壓源/地源匯流排 集中並電氣連接至該内部電路，因此可以降低該複數個輸 入/輸出電路所需之晶片周長’進而達到縮小整個晶片面 積且降低成本之目的。以目前習用之高頻電路而言，往往 每兩個輸入/輸出打線墊即須搭配一個電壓源/地源打線 塾’甚至每一個輸入/輸出打線塾即須搭配一個電壓源/地 源打線墊。由於本創作係將該複數個電壓源/地源打線塑· 以至少一多層金屬電壓源/地源匯流排集中並電氣連接至 -6- + 適財賴家轉（CNS)从胁（2丨G χ 297公羡） ----^---r---------訂------0 — ( /.V (請先閱讀背面之注意事項再填寫本頁) 460992 經濟部中央棵準局貝工消費合作社印製 C7 D7 五、創作説明（4 ) 該内部電路，因此該輸入/輸出電路平均所佔據之實體佈 局寬度便·可以增加，亦即該複數個輸入/輸出電路在實體 佈局和靜電防護之設計上便保有較大之彈性。此外，因該 複數個輸入/輸出電路和該輸入/.輸出打線塾之連線寬度可 以增加’因此降低了該連線線路之電阻值，而增進該晶片 之可靠度。本創作可適用於N圈數（N>1)之打線墊結構。 本創作之多層金屬電壓源/地源匯流排之佈局結構，包 含一内邵電路、至少一多層金屬電壓源/地源匯流排.、複 數個電壓源/地源打線塾及複數個輸入/.輸出打線I。該内 部電路包含一核心電路及複數個輸入/輸出電路。該核心 電路為整個晶片功能之核心，.包含各種數位電路、類比電 路或混合電路（mixed -mode circuit)。該多層金屬電壓 源/地源匯流排包含至少一電壓源/地源外部匯流排及至少 一電壓源/地源橋接匯流排。該電壓源/地源外部匯流排用 於電氣連接該複數個電壓源/地源打線塾，該電壓源/地源 橋接匯流排用於電氣連接該電壓源/地源外部匯流排至該 内部電路。該電壓源/地源外部匯流排可串接為一環形結 構（ring structure)、分段直線結構或其它結構，本創作 對此並未作任何限制。該複數個電壓源/地源打線塾電氣 連接至該多層金屬電壓源/地源匯流排，用於提供該内部 電路所需之電壓源及地源。該複數個輸入/輸出打線整電 氣連接至該内部電路的複數個輪入/輸.出電路，用於傳遞 該晶片之運算偉號。 圖式之簡單說明 (請先閱讀背面之注意事項再填寫本頁)V. Creation instructions (The Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs printed a wire pad 12 士, 〇 > < —The terminal is electrically connected to the internal circuit 1 3 with a wire, and the upper side is a machine ' The wire bonding method is to connect to a lead frame or a substrate (pictured). The plurality of wire bonding pads in Figure 1 are based on the structure of three-tier wire bonding pads (3-tier bonding, g P adschematics). Contains three wire bonding pads, which are located in the first circle 17, the second circle 18 and the first-and any-the wire bonding pads 12 are connected to one of the internal circuit 1 3 output / output circuit 16. When the unit wire is integrated The smaller the occupied width is, the smaller the width of the chip is. It means that more wire pads can be accommodated under the same wafer perimeter, or that the area of the chip can be effectively reduced with the same number of wire pads. In other words, 'how effective To reduce the width occupied by a unit wire pad 14 or the width of the wiring between the multiple wire pads and the corresponding input / output circuits of the internal circuit 13, it can be effectively seen when the wire pad is limited. Reduce the area of the entire wafer and Reduce costs. In addition, 'If the plurality of wire bonding pads are arranged too closely in the first to third turns 1 7 to i 9, the plurality of wire bonding wires 蛰 2 and the internal circuit 丨 3 of the input / output winding circuit 16 The width of the connection line will be inevitably reduced, which will cause the electromigration effect and affect the reliability of the chip (re 1 i ab i 1 i ty). In addition, the input / output circuit of the internal circuit i 3 The width of 16 will also be limited, adding to the difficulty in designing the internal physical layout and electrostatic protection. Zhao Zuo's brief description of the first purpose of this creation is to eliminate the current restrictions on wire pads. A plurality of wire bonding pads in the chip will occupy the shortcomings of the larger circumference of the chip. -5- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X297 mm> ----: ---_ ----- '^ -------. Order ------ Line 1-/ V- · ./ ((Please read the notes on the back before filling this page) 6 0 9 9 2 C7 D7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Creation Instructions (The second purpose of this creation is to eliminate the current restrictions on wire bonding pads In the case of a number of wire pads within 9 pieces and the corresponding internal circuit's input / output circuit, the width of the wiring is too small. The third purpose of this creation is to eliminate the current restrictions on wire pads. In the case of multiple circuits, the shortcomings of the multiple input / output circuits in the chip are too small to be easily calculated. In order to achieve the above purpose, the author provides a microelectronic chip for connecting the internal circuit and the complex number. The multi-layer metal private voltage source / ground source busbar of the voltage source / ground source wire pad is finished. The structure of your office is to place most voltage source / ground source wire pads on the outermost circle of all wire pads, and combine the plurality of voltage source / ground source wire pads with at least one multilayer metal voltage source / ground source It is electrically connected to the internal circuit. The multilayer metal voltage source / ground source bus can be segmented into a plurality of voltage source / ground source external buses, and any voltage source / ground source external bus is electrically connected to at least one voltage source / ground source bridge bus The internal circuit to the chip is not required to be individually connected to the internal circuit due to the plurality of voltage source / ground source wiring potentials, but is concentrated and electrically connected to the internal circuit by at least one multilayer metal voltage source / ground source bus Therefore, the perimeter of the wafer required for the plurality of input / output circuits can be reduced, thereby achieving the purpose of reducing the entire wafer area and reducing the cost. As far as the current high-frequency circuits are used, often every two input / output wiring pads must be matched with a voltage source / ground source wiring pad. Even every input / output wiring pad must be matched with a voltage source / ground source wiring pad . Because this creative system is to wire the multiple voltage sources / ground sources · Concentrate and electrically connect at least one multilayer metal voltage source / ground source bus to -6- +丨 G χ 297 public envy) ---- ^ --- r --------- order ------ 0 — (/.V (Please read the notes on the back before filling this page ) 460992 Printed by C7 D7, Shellfish Consumer Cooperative of the Central Kezhun Bureau of the Ministry of Economic Affairs 5. Creation instructions (4) The internal circuit, so the width of the physical layout occupied by the input / output circuit on average can be increased, that is, the multiple The input / output circuit has greater flexibility in the physical layout and electrostatic protection design. In addition, the connection width of the plurality of input / output circuits and the input / output wiring can be increased, thus reducing the connection. The resistance value of the line circuit improves the reliability of the chip. This creation can be applied to the wire pad structure of N turns (N > 1). The layout structure of the multilayer metal voltage source / ground source bus in this creation includes a Inner circuit, at least one multilayer metal voltage source / ground source bus, multiple voltage / ground sources塾 and a plurality of input / output lines I. The internal circuit includes a core circuit and a plurality of input / output circuits. The core circuit is the core of the entire chip function, and includes various digital circuits, analog circuits or mixed circuits (mixed- mode circuit). The multilayer metal voltage source / ground source bus includes at least one voltage source / ground source external bus and at least one voltage source / ground source bridge bus. The voltage source / ground source external bus is used for electrical connection The plurality of voltage / ground sources are wired, and the voltage / ground source bridge bus is used to electrically connect the voltage / ground source external bus to the internal circuit. The voltage / ground source external bus can be connected in series It is a ring structure, a segmented linear structure, or other structures, and there are no restrictions on this work. The voltage source / ground source wire is electrically connected to the multilayer metal voltage source / ground source busbar. , Used to provide the voltage source and ground source required by the internal circuit. The plurality of input / output wires are electrically connected to the plurality of wheel input / output. Output circuits of the internal circuit for transmitting Submit the calculation number of the chip. Brief description of the diagram (please read the precautions on the back before filling this page)
+.1T 線-+ .1T line-
460992 C7 --------------D7 _ 五、創作説^77""Γ — ~ 本創作將依照後附圖式來說明，其中： 圖1係έι知之微電子晶片之複數假打線勢和其相對應之内 邵電路的輪入/輸出電路之佈局結構； 圖2係本創作之多層金屬電壓源/地源匯流排之第一較佳實 施例之佈局結構； 圖3係本創作之多層金屬電壓源/地源匯流排之第二較佳實 施例之佈局結構； 圖4係本創作之多層金屬電壓源/地源匯流排之第三較隹實 ‘施例之侔局結構；及 圖5係本創作之多層金屬 '電壓源/地源匯流排之第四較佳實 施例乏佈局結構。 元件符號說明 1 1晶片 12打線墊 1 3内部電路 1 4 一單位打線墊所佔據的寬度 1 5 —單位打線墊 1 6輸入/輸出電路 17第一圈 18第二圈 1 9第三圈 經濟部中央標隼局—工消费合作社印裝 21 —單位打線墊所佔據的寬度 2 2電壓源/地源外部匯流排 2 3 .電壓源/地源打線整 2 4輸入/輸出打線# 25 —單位打線墊 26電壓源7地源橋接匯流排 較佳實施例說明 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210X297公釐） 4 6 09 92 C7 D7 經濟部中央標準局負工消費合作社印^ 五、創作説明（6 ) 圖2係本創作之多層金屬電壓源/地源匯流排之第一較 佳實施例之佈局結構’其中係以三圈打線墊之結構為例， 即所有打線蟄分別位於第一圈i 7、第二圈1 8及第三圈1 9 内’且任一輸入/輸出打線墊24均以一連線電氣連接至該 内邵電路1 3。該佈局結構係將複數個電壓源/地源打線墊 2 3放置於所有打線墊之最外圈，即第三圈1 9之内，而該 複數個輸入/輸出打線墊24放置於所有打線墊之内圈，即 第一圈1 7及第二圈1 8之内。該複數個電壓源/地源打線墊 2 3 0 —導線電氣連接至一多層金屬電壓源/地源匯流排， 且遠多層金屬電壓源/地'源匯流排再電氣連接至該内部電 路13以提供各金屬層之電蜃源及地源。該多層金屬電壓源 /地源匯流排包含至少一電壓源/地源外部匯流排2 2及至少 —電壓源/地源橋接匯流排2 6。該電壓源/地源外部匯流排 2 2連接該複數個電壓源/地源打線塾2 3，並以至少一.電.壓 源/地源橋接匯流排2 6電氣連接至該晶片之内部電路J 3。 由於該複數個電壓源/地源打線墊2 3不須個別連接至該内 部電路1 3，而係以一多層金屬電壓源/地源匯流排集中地 電氣連接至該内部電路，因此可以降低該複數個輸入/輸 出電路所需之晶片周長，進而達到縮小整個晶片面積且降 低成本之目的。該複數個輸入/輸出打線墊24之間僅須安 插少許之連接空隙讓該電壓源/地源橋接匯流排26得以通 過並電氣連接至該内部電路1 3。圖2之結構在實際應用 時，該電壓源/.地源外部匯流排22亦可以兩條以上之電壓 源/地源橋接匯流排26電氣連接至該内部電路13，以平衡 ----^---^----------訂------線 (請先閱讀背面之注意事項再填寫本頁.)460992 C7 -------------- D7 _ V. Creation ^ 77 " " Γ — ~ This creation will be explained in accordance with the following drawings, where: Figure 1 is the microelectronics known by hand The layout of the multiple pseudo-hitting potentials of the chip and its corresponding internal input / output circuit of the internal circuit; Figure 2 is the layout structure of the first preferred embodiment of the multilayer metal voltage source / ground source bus of this creation; 3 is the layout structure of the second preferred embodiment of the multilayer metal voltage source / ground source bus of this creation; FIG. 4 is the third example of the third embodiment of the multilayer metal voltage source / ground source bus of this creation The structure of the bureau; and FIG. 5 is a layout structure of the fourth preferred embodiment of the multilayer metal 'voltage source / ground source bus of the present invention. Component symbol description 1 1 chip 12 wire pads 1 3 internal circuit 1 4 width occupied by a unit wire pad 1 5 —unit wire pad 1 6 input / output circuit 17 first circle 18 second circle 1 9 third circle Ministry of Economic Affairs Central Bureau of Standards—Printed by Industrial and Consumer Cooperatives 21—Width occupied by unit wiring pads 2 2 Voltage source / ground source external busbar 2 3 .Voltage source / ground source wiring 2 4 Input / output wiring # 25 —Unit wiring Pad 26 Voltage source 7 Ground source bridge bus The preferred embodiment explains that this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 4 6 09 92 C7 D7 Printed by the Offshore Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ V. Creation description (6) Figure 2 is the layout structure of the first preferred embodiment of the multilayer metal voltage source / ground source busbar of this creation, where the structure of a three-circle wire pad is used as an example, that is, all the wires are separately It is located within the first circle i 7, the second circle 18, and the third circle 1 9 ', and any one of the input / output wire bonding pads 24 is electrically connected to the internal circuit 13 by a wire. The layout structure is that a plurality of voltage source / ground source wire bonding pads 2 3 are placed in the outermost circle of all wire bonding pads, that is, within the third circle 19, and the plurality of input / output wire bonding pads 24 are placed in all wire bonding pads. The inner circle is within the first circle 17 and the second circle 18. The plurality of voltage source / ground source wiring pads 2 3 0—the wires are electrically connected to a multilayer metal voltage source / ground source bus, and the far multilayer metal voltage source / ground 'source bus is then electrically connected to the internal circuit 13 In order to provide electrical source and ground source for each metal layer. The multilayer metal voltage source / ground source bus comprises at least one voltage source / ground source external bus 22 and at least a voltage source / ground source bridge bus 26. The voltage source / ground source external bus bar 2 2 is connected to the plurality of voltage source / ground source wire buses 2 3 and is electrically connected to the chip's internal circuit with at least one .electricity. The voltage source / ground source bridge bus bar 2 6 J 3. Since the plurality of voltage source / ground source wiring pads 2 3 do not need to be individually connected to the internal circuit 1 3, but are electrically connected to the internal circuit collectively by a multilayer metal voltage source / ground source bus bar, it can reduce the The perimeter of the wafer required by the plurality of input / output circuits can further reduce the area of the entire wafer and reduce the cost. Only a few connection gaps need to be inserted between the plurality of input / output wiring pads 24 to allow the voltage source / ground source bridge bus 26 to pass through and be electrically connected to the internal circuit 13. When the structure of FIG. 2 is applied in practice, the voltage source / ground source external bus 22 may also be electrically connected to the internal circuit 13 by two or more voltage sources / ground source bridge buses 26 to balance ---- ^ --- ^ ---------- Order ------ line (Please read the notes on the back before filling in this page.)
460992 C7 D7 五、創作説明（7 ) 電流密度的为佈。本創作之一單位打線墊2 5内僅包含二個 輸入/輸出打線墊24，因此該一單位打線墊25所佔據的寬 度2 1較習知技藝之—單位打線墊的寬度丨4.來的小，代表 在相同的晶片周長下可以容納較多的打線墊，或是說在相 同之打線墊個數下可縮小該晶片面積。 圖3係本創作之多層金屬電壓源/地源匯流排之第二 較佳實施例之佈局結構，其係將該電壓源/地源外部匯流 排2 2串接成一個環形（r丨n g )，再以至少一電壓源/地源橋 接單流排2 6電氣連接至該内部電路.1 3。 圖4係本創作之多層金屬電壓源/地源匯流排之第三 較佳實施例 < 佈局結構，其偉將該電壓源/地源外部匯流 排2 2置於该晶片1 1之最外圈，而核複數個輸入/輸出打線 墊2 4和该複數個電壓源/地源打線墊2 3可集中於同一區 域’以方便後續之製程。. 圖5係本創作之多層金屬電壓源/地源匯流排之第四較 佳實施例 < 佈局結構，其係將該電壓源/地源外部匯流排 2 2分成許多段（可稱為分段直線結構），每一段均經由至少 經濟部中央標準局貝工消費合作社印袋 (請先閲讀背面之注意事項再填寫本頁) %壓源/地源橋接匯流排2 6連接至該内部電路丨3。該怖 局結構可分散各個電壓源/地源橋接匯流排2 6之電流密 度’且將適當個數的電壓源/地源打線墊2 3予以組合而分 散地連接至該電壓源/地源外部匯流排22之複數個段，可 避免琢複數個電壓源/地源打線墊2 3彼此間有電性干擾的 情形產生。 本創作之佈局結構對於該内部電路丨3之複數個輸入/ 4 6 09 92 C7 _ D7 五、創作説明（8 ) 輸出電路1 6而言，僅須對應至該複數個輸入/輸出打線勢 2 4和少數個電壓源/地源橋接匯流排2 6，因此可使用之晶 片周長必較習知技藝來得寬V換言之，該複數個輸入/輸 出打線墊2 4和該内部電路1 3的複數個輸入/輸出電路1 6之 連線線路將可使用較寬之金屬連線，而減少電阻值且降低 電子遷移效應的機率，進而提高該晶片1 1之可靠度。此 外，本創作之一單位打線墊所佔據之寬度2 1較習知技藝來 得短’因此在相同之打線整個數下，該内部電路丨6之複數 個輸入/輸出’電路1 6平均所佔據之寬度便可以增加。換句 話說，該複數個輸入/輸出電路丨6可保有較大的實體佈局 寬度，因此可以降低其實體体局和靜電防護之設計難度。 本創作之技術内容及技術特點巳揭示如上，然而熟悉 本項技術之人士仍可能基於本創作之教示及揭示而作種種 不背離本創作精神之替換及修飾；因此，本創作之保護範 圍應不限於實施例所揭示者，而應包括各種不背離本創作 之替換及修飾，並為以下之申請專利範圍所涵蓋。 經濟部中央梯準局身工消費合作社印製.460992 C7 D7 V. Creative Instructions (7) The current density is cloth. One of the unit's wire bonding pads 25 includes only two input / output wire bonding pads 24, so the width occupied by the unit wire bonding pads 25 1 is better than the conventional technique—the width of the unit wire bonding pads. 4. Small, which means that more wire pads can be accommodated under the same wafer perimeter, or the area of the chip can be reduced with the same number of wire pads. FIG. 3 is the layout structure of the second preferred embodiment of the multilayer metal voltage source / ground source bus bar of this creation, which is a series connection of the voltage source / ground source external bus bar 2 2 into a ring (r 丨 ng) , And then at least one voltage source / ground source bridges the single current source 2 6 to be electrically connected to the internal circuit. 1 3. FIG. 4 is a third preferred embodiment of the multilayer metal voltage source / ground source busbar of the present invention < layout structure, which places the voltage source / ground source external busbar 2 2 on the outermost part of the wafer 1 1 And the plurality of input / output wire bonding pads 24 and the plurality of voltage source / ground source wire bonding pads 2 3 can be concentrated in the same area to facilitate subsequent processes. Fig. 5 is the fourth preferred embodiment of the multilayer metal voltage source / ground source bus of the present invention < layout structure, which divides the voltage source / ground source external bus 22 into a plurality of sections (can be referred to as Segment straight structure), each segment is at least printed through the printed bag of the Peugeot Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page)% voltage source / ground source bridge bus 2 6 connected to the internal circuit丨 3. This structure can decentralize the current density of each voltage source / ground source bridge bus 26 and combine the appropriate number of voltage source / ground source wire pads 2 3 to connect to this voltage source / ground source externally. The plurality of segments of the bus bar 22 can avoid the situation where there is electrical interference between the multiple voltage source / ground source wire pads 2 3. The layout structure of this creation is for the multiple inputs of the internal circuit 丨 3/4 6 09 92 C7 _ D7 V. Creation instructions (8) Output circuit 1 6 only needs to correspond to the multiple input / output wiring potential 2 4 and a few voltage source / ground source bridge buses 2 6 so the perimeter of the chip that can be used must be wider than conventional techniques. In other words, the plurality of input / output wire pads 2 4 and the plurality of inputs of the internal circuit 1 3 The wiring of the output circuit 16 can use a wider metal connection, which reduces the resistance value and the probability of the electron migration effect, thereby improving the reliability of the chip 11. In addition, the width 21 occupied by a wire pad of one unit of this creation is shorter than the conventional technique. Therefore, under the same number of wires, the multiple input / output circuits of the internal circuit 6 and the circuit 16 occupy an average. The width can be increased. In other words, the plurality of input / output circuits 6 can maintain a large physical layout width, so that it can reduce the design difficulty of the physical body and electrostatic protection. The technical content and technical characteristics of this creation are disclosed above. However, those familiar with this technology may still make various substitutions and modifications without departing from the spirit of this creation based on the teaching and disclosure of this creation; therefore, the scope of protection of this creation should not be changed. It is limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from this creation, and are covered by the following patent application scope. Printed by the Central Laboratories of the Ministry of Economic Affairs, Consumer Cooperatives.