經濟部智慧財產局員工消費合作社印製 6 0 9 5 5 6763twf. doc/006 A7 __ _B7__ 五、發明說明（f ) 本發明是關於積體電路元件之製造方法，且特別是有 關於一種金氧半導體（Metal-Oxide Semiconductor，M0S)之 結構與製造方法。 目前絕緣層上有砍（Silicon on Insulation，SOI)結構， 常應用在金氧半導體上，係在基底結構中形成一層絕緣層 (insulator)以及在絕緣層上方形成結晶砍(crystalline Silicon) 層，之後再於此結晶矽層上製作元件。與傳統一般矽基底 上的金氧半導體(metal oxide semiconductor ; M0S)相較，絕 緣層上有矽金氧半導體(S0I-M0S)具有結晶矽層很薄、結 晶矽層下方絕緣層可防止漏電以及源極/汲極區的寄生電容 (parasitic capacitance)很小等特徵，而具有啓始電壓 (threshold voltage ; VT)較低、耗電量較低、操作速率 (performance)較高等優點，使得元件可靠度上升。 一般習知的絕緣層上有矽金氧半導體結構如第1圖所 示。其在一基底100中先形成一層埋入式絕緣層102。之 後，在基底中依序形成隔離結構104以及源極/汲極區106。 在源極/汲極區106之間且在基底100上爲閘氧化層112與 閘極114，其被一間隙壁110所包圍。電晶體的通道區爲 108。 然而，在上述之絕緣層上有矽結構中，爲提高元件操 作效能，則必須形成較淺之通道區108，然而形成較淺之 通道區108則同時會使其源極/汲極106也會變淺，而造成 源極/汲極106阻値越高，如此會降低驅動電流（driving current)。因此，想要同時具有淺的通道區與深的源極/汲 3 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- 線 6 0 9 5 5 6763twf.doc/006 A7 ___ B7____ 五、發明說明（2_) 極區，使電晶體同時具有急遽升降的次臨限電壓（steep subthreshold)、低漏電流與高驅動電流（driving current)等特 性是非常困難的。 因此，本發明係提出一種金氧半導體之結構與製造方 法，其在基底中形成空洞，此空洞位於絕緣層和通道區之 間，可以同時獲得淺的通道區與深的源極/汲極區。 本發明係提出一種金氧半導體之結構與製造方法，其 可以降低源極/汲極區的阻値，以增加驅動電流。 本發明所提出一種金氧半導體之製造方法，包括提供 一基底，於基底中形成一空洞，接著於空洞下方形成一埋 入式絕緣層，之後在空洞上方之基底表面形成一閘極結 構，最後以閘極結構爲罩幕於基底中形成一源極/汲極區。 上述之空洞之形成方法，係在基底上形成數個柱狀空 洞之後，將基底置於無氧之環境下，進行回火製程，使柱 狀空洞於基底中融合成一空洞。形成矽中有空的空間 (Empty Space in Silicon，ESS)。 上述之絕緣層係對含有空洞之基底，植入摻質後，施 加回火製程而在空洞下方形成一層絕緣層。藉此，可以同 時獲得淺的通道區與深的源極/汲極區，使其具有陡峭的次 臨限電壓、高驅動電流與低漏電流等功效。 本發明係提出一種金氧半導體之結構包括一基底，基 底中具有一空洞。一層埋入式絕緣層位於此空洞下方之基 底中。一閘極結構位於空洞上方之基底表面上。一源極/汲 極區位於該閘極結構兩側下方之基底中。以及一通道區位 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- 經濟部智慧財產局員工消費合作社印製 0 95 5 6763twf.doc/006 A7 _B7___._ 五、發明說明（> ) 於空洞上方且於源極/汲極之間。 (請先閱讀背面之注意事項再填寫本頁) 上述之金氧半導體之結構，包括一淺的通道區以及一 深的源極/汲極區。 上述之閘極結構則可以爲一般的結構，包括閘氧化 層，位於閘氧化層上之閘極，以及包圍閘氧化層與閘極之 間隙壁。 上述之源極/汲極區，可包括一輕微摻雜汲極 讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，並進一步提供發明專利範圍之解釋，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明 第1圖爲習知之絕緣層上有矽金氧半導體剖面圖。 第2A圖至第2E圖爲根據本發明較佳實施例之場效電 晶體結構與製造流程剖面圖。 經濟部智慧財產局員工消費合作社印製 圖式標號之簡單說明 100、200 :基底 102、204 :埋入式絕緣層 104 :隔離區 106、212 :源極/汲極區 108、214 :通道區 110、206 :閘氧化層 112、208 :閘極 114、210 :間隙壁 202、202a :空洞 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 6〇95 5 67 63twf. doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（+) 202b :空洞頂部開口 實施例 第2A圖至第2H圖所繪製爲根據本發明之一較佳實 施例之一種金氧半導體的製造流程剖面簡圖。 首先，參照第2A圖至第2C圖。提供一具有第一導 電型之基底200。在基底200上，形成數個柱狀空洞202a (如第2A圖所示）。此空洞202a形成方法例如是微影蝕 刻技術。之後，將此包含數個空洞202a之基底200，置於 無氧之環境下例如是含氫的環境下，進行回火（annealing) 處理，而使空洞口 202a之頂部開口 202b逐漸收縮減小（如 第2B圖所示）。這是利用矽表面會自行重整排列（self-organizing migration)之特性，即表面之砍原子爲了降低表 面能量，逐漸在基底200表面上遷移，將空洞202a之頂部 開口 202b塡滿，而此時數個柱狀空洞202a逐漸於基底200 中融合成空洞202 (如第2C圖所示）。此種結構稱爲矽中 有空的空間（Empty Space in Silicon，ESS)。此空洞 202 與 基底200表面之距離約爲0.1至0.2微米之間。 接著參照第2D圖。形成一層埋入式絕緣層204於基 底200中。此埋入式絕緣層204位於空洞202下方。埋入 式絕緣層204材質例如是氧化矽，形成方法包括離子植入 法，將摻質例如是氧離子植入（implanting)基底200中，之 後進行回火（annealing)處理。回火處理包括雷射、快速熱 製程(rapid thermal process，RTP)或爐管（furnace)等方式來 進行。先前所植入的摻質在經由回火處理後，摻質便會產 6 本紙張尺度適用申國國家標準（CNS)A4規格（210 X 297公釐） -------------------^---------A (請先閱讀背面之注意事項再填寫本頁) A7 B7 460955 6763twf-doc/006 五、發明說明（，） 生氧化反應而形成一層埋入式絕緣層204。摻質植入電壓 約1·5χ 105電子伏特，植入劑量1〇17原子/立方公分。 最後參照第2D圖在空洞202上方之基底200上形成 閘極結構，此閘極結構包括一層閘氧化層206，閘氧化層 206上方之閘極208，以及包圍閘極208之間隙壁210。之 後，以閘極結構爲罩幕於基底中形成源極/汲極212，此源 極/汲極包含一輕微摻雜汲極（Lightly Doped Drain，LDD)， 形成源極/汲極212的方法爲離子植入法。 依上述之製造方法，可形成本發明所提供之金氧半導 體結構。本發明所提供之金氧半導體結構，也適用形成於 各式用途金氧半導體的製程，可在不改變製程精神之條件 下，可視需要增減之金氧半導體組成與結構，即可形成其 他用途金氧半導體。 由本發明一較佳實施例提供一場效電晶體，其包括一 基底200中具有空洞202，埋入式絕緣層204位於空洞202 下方之基底200中。閘極208在空洞202上方的基底200 表面上，閘極208和基底200間有閘氧化層206，並且間 隙壁210包圍閘極208。在閘極結構兩側下方之基底200 有源極/汲極212。在源極/汲極212之間及空洞202與閘極 208之間有通道區214。因此通道區214可以很淺且同時具 有深的源極/汲極區212。 根據上述，在基底中形成一空洞，此空洞位於閘極下 方且左右兩側鄰接源極/汲極’可以防止源極/汲極間之漏 電流，且可以降低接合電容。並形成淺的通道區且同時具 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-----; 7裝--—丨！ I訂-!丨—丨！^、 /L ,/c (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 460955 6763twf.doc/006 五、發明說明（<) 有深的源極/汲極區，越淺的通道區可以使電晶體具有急遽 升降的次臨限電壓與低漏電流等特性，而深的源極/汲極區 則可以降低阻値而不會造成漏電流，因此可以獲得較大的 電流驅動力。因而，在本發明所提出之金氧半導體結構具 有急遽升降的次臨限電壓、低漏電流與高驅動電流等優良 特性。 根據上述，本發明提供一種場效電晶體之結構與製造 方法，有下列優點： 依據本發明之場效電晶體之結構與製造方法，淺的通 道區可增加閘極控制能力，進而改善元件特性。較深的源 極/汲極區，可降低電阻。因此本發明具有較佳之短通道效 應。在絕緣層上方兩源極/汲極之間的空洞，隔離兩源極/ 汲極區’可防止漏電流，並且可降低接合電容。具有起始 電壓低、低漏電流與寄生電容小等優良特性。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 Μ----------------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公楚）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 0 9 5 5 6763twf. Doc / 006 A7 __ _B7__ V. Description of the Invention (f) The invention relates to a method for manufacturing integrated circuit components, and in particular to a metal oxide Structure and manufacturing method of Metal-Oxide Semiconductor (MOS). At present, there is a Silicon on Insulation (SOI) structure on the insulating layer, which is often applied to metal-oxide semiconductors. It forms an insulating layer in the base structure and a crystalline silicon layer over the insulating layer. Components are then fabricated on this crystalline silicon layer. Compared with the traditional metal oxide semiconductor (MOS) on a conventional silicon substrate, the silicon oxide semiconductor (S0I-M0S) on the insulating layer has a thin crystalline silicon layer, and the insulating layer under the crystalline silicon layer can prevent leakage and The parasitic capacitance in the source / drain region is small, and it has the advantages of lower threshold voltage (VT), lower power consumption, and higher performance, making the component reliable. Degrees rise. The conventional known insulating layer has a silicon gold oxide semiconductor structure as shown in FIG. It first forms a buried insulating layer 102 in a substrate 100. Thereafter, an isolation structure 104 and a source / drain region 106 are sequentially formed in the substrate. Between the source / drain regions 106 and on the substrate 100 are a gate oxide layer 112 and a gate electrode 114, which are surrounded by a gap wall 110. The channel area of the transistor is 108. However, in the above-mentioned silicon structure on the insulating layer, in order to improve the operation efficiency of the device, a shallower channel region 108 must be formed. However, forming a shallower channel region 108 will also cause its source / drain 106 to also It becomes shallower, causing the source / drain 106 resistance to be higher, which reduces the driving current. Therefore, if you want to have a shallow channel area and a deep source / drain at the same time, this paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please read the precautions on the back before filling this page ) Install -------- Order ----- Line 6 0 9 5 5 6763twf.doc / 006 A7 ___ B7____ V. Description of the invention (2_) The polar region makes the transistor have a secondary lift that rises and falls at the same time. It is very difficult to have characteristics such as a deep subthreshold, low leakage current, and high driving current. Therefore, the present invention proposes a structure and manufacturing method of a metal-oxide semiconductor, which forms a cavity in the substrate. The cavity is located between the insulating layer and the channel region, and a shallow channel region and a deep source / drain region can be obtained at the same time. . The invention proposes a structure and a manufacturing method of a metal-oxide semiconductor, which can reduce the resistance of the source / drain region to increase the driving current. The invention provides a method for manufacturing a metal-oxide semiconductor, which includes providing a substrate, forming a cavity in the substrate, forming a buried insulating layer under the cavity, forming a gate structure on the substrate surface above the cavity, and finally A gate structure is used as a mask to form a source / drain region in the substrate. The method for forming the above-mentioned cavity is that after forming several columnar holes on the substrate, the substrate is placed in an oxygen-free environment and a tempering process is performed to fuse the columnar holes into a cavity in the substrate. Formation of Empty Space in Silicon (ESS). The above-mentioned insulating layer is a substrate containing a cavity. After implantation of a dopant, a tempering process is performed to form an insulating layer under the cavity. In this way, a shallow channel region and a deep source / drain region can be obtained at the same time, so that it has the effects of steep sub-threshold voltage, high driving current, and low leakage current. The present invention proposes a structure of a gold-oxide semiconductor including a substrate having a cavity therein. A buried insulating layer is located in the substrate below this cavity. A gate structure is located on the substrate surface above the cavity. A source / drain region is located in a substrate below both sides of the gate structure. And one channel location 4 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Loading -------- Order --- -Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 0 95 5 6763twf.doc / 006 A7 _B7 ___._ V. Description of the invention (>) Above the cavity and between the source / drain. (Please read the precautions on the back before filling out this page) The structure of the metal-oxide semiconductor mentioned above includes a shallow channel region and a deep source / drain region. The above gate structure may be a general structure, including a gate oxide layer, a gate electrode located on the gate oxide layer, and a barrier wall surrounding the gate oxide layer and the gate electrode. The above source / drain region may include a slightly doped drain to make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, and further provide an explanation of the scope of the invention patent. The preferred embodiment and the accompanying drawings are described in detail as follows: Brief Description of the Drawings Figure 1 is a cross-sectional view of a conventional silicon-oxygen semiconductor on an insulating layer. 2A to 2E are cross-sectional views of a field effect transistor structure and a manufacturing process according to a preferred embodiment of the present invention. Brief description of printed labeling for employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs 100, 200: Substrate 102, 204: Embedded insulation layer 104: Isolation area 106, 212: Source / drain area 108, 214: Channel area 110, 206: Gate oxide layer 112, 208: Gate electrode 114, 210: Spacer wall 202, 202a: Hollow 5 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 6095 5 67 63twf. Doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (+) 202b: Hollow top opening embodiment Figures 2A to 2H are drawn according to a preferred embodiment of the present invention A simplified cross-sectional view of the manufacturing process of a metal-oxide semiconductor. First, refer to FIGS. 2A to 2C. A substrate 200 having a first conductivity type is provided. On the substrate 200, a plurality of columnar cavities 202a are formed (as shown in FIG. 2A). The method for forming the cavity 202a is, for example, a photolithography technique. After that, the substrate 200 containing a plurality of cavities 202a is placed in an oxygen-free environment, such as a hydrogen-containing environment, and subjected to an annealing treatment, so that the top opening 202b of the cavity opening 202a gradually shrinks and reduces (As shown in Figure 2B). This is to take advantage of the self-organizing migration characteristic of the silicon surface, that is, the atoms on the surface gradually move on the surface of the substrate 200 in order to reduce the surface energy, and the top opening 202b of the cavity 202a is filled. A plurality of columnar cavities 202a gradually merge into cavities 202 in the base 200 (as shown in FIG. 2C). This structure is called Empty Space in Silicon (ESS). The distance between the cavity 202 and the surface of the substrate 200 is about 0.1 to 0.2 microns. Next, refer to FIG. 2D. A buried insulating layer 204 is formed in the substrate 200. The buried insulating layer 204 is located under the cavity 202. The material of the buried insulating layer 204 is, for example, silicon oxide, and a formation method includes an ion implantation method, and dopants such as oxygen ions are implanted into the substrate 200 and then annealed. Tempering is performed by laser, rapid thermal process (RTP) or furnace. The previously implanted dopants will be processed after tempering, and the dopants will produce 6 paper sizes applicable to the National Standard for China (CNS) A4 (210 X 297 mm) ---------- --------- ^ --------- A (Please read the precautions on the back before filling this page) A7 B7 460955 6763twf-doc / 006 V. Description of the invention (,) The reaction forms a buried insulating layer 204. The implanted implantation voltage is about 1.5 x 105 electron volts, and the implantation dose is 1017 atoms / cm3. Finally, referring to FIG. 2D, a gate structure is formed on the substrate 200 above the cavity 202. The gate structure includes a gate oxide layer 206, a gate electrode 208 above the gate oxide layer 206, and a spacer 210 surrounding the gate electrode 208. Then, a source / drain 212 is formed in the substrate by using the gate structure as a mask. The source / drain includes a lightly doped drain (LDD) to form the source / drain 212. For ion implantation. According to the above-mentioned manufacturing method, the metal-oxide semiconductor structure provided by the present invention can be formed. The metal-oxide semiconductor structure provided by the present invention is also suitable for forming metal-oxide semiconductor processes of various uses. Without changing the spirit of the process, the metal-oxide semiconductor composition and structure can be increased or decreased as required to form other applications. Gold Oxide Semiconductor. According to a preferred embodiment of the present invention, a field effect transistor is provided, which includes a substrate 200 having a cavity 202 therein, and a buried insulating layer 204 is located in the substrate 200 below the cavity 202. The gate electrode 208 is on the surface of the substrate 200 above the cavity 202. There is a gate oxide layer 206 between the gate electrode 208 and the substrate 200, and a gap wall 210 surrounds the gate electrode 208. Substrate 200 source / drain 212 below both sides of the gate structure. There are channel regions 214 between the source / drain 212 and between the cavity 202 and the gate 208. Therefore, the channel region 214 may be shallow and at the same time have a deep source / drain region 212. According to the above, a cavity is formed in the substrate, and the cavity is located below the gate and adjacent to the source / drain on the left and right sides to prevent leakage current between the source / drain and reduce the junction capacitance. And form a shallow channel area with 7 paper sizes at the same time applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) I -----; 7 packs --- 丨! I order-! 丨 — 丨! ^, / L, / c (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 460955 6763twf.doc / 006 V. Description of the invention (<) has deep sources The drain / drain region, the shallower the channel region can make the transistor have the characteristics of sharp rise and fall of the secondary threshold voltage and low leakage current, and the deep source / drain region can reduce the resistance without causing leakage current Therefore, a larger current driving force can be obtained. Therefore, the metal-oxide-semiconductor structure proposed in the present invention has excellent characteristics such as a sharply rising and falling sub-threshold voltage, low leakage current, and high driving current. According to the above, the present invention provides a structure and manufacturing method of a field effect transistor, which has the following advantages: According to the structure and manufacturing method of the field effect transistor of the present invention, the shallow channel region can increase the gate control ability, thereby improving the characteristics of the device . Deeper source / drain regions reduce resistance. Therefore, the present invention has a better short channel effect. In the space between the two source / drain electrodes above the insulation layer, isolating the two source / drain regions' can prevent leakage current and reduce the junction capacitance. It has excellent characteristics such as low initial voltage, low leakage current and small parasitic capacitance. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Μ ----------------- (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 This paper size applies to Chinese national standards ( CNS) A4 specification (21〇X 297)