Α7 Β7 425609 五、發明説明（ 1. 發明領域： 本發明係有關於一種半導體元件特別是一種製造極短 通道η型金氧半場效電晶體（nM〇SFET)之方法。 2. 發明背景： 在現今半導體技術領域，金氧半場效電晶體（MOSFET) 特別是CMOS已廣泛的被應用，並且在極超大型積體電路 (ULSI)時代，元件的尺寸也是日益縮小以達到更高的性能。 然而在元件尺寸日益縮小的同時’寄生電路像RC延遲和源 /没極間串聯電阻报容易使得電路的性能衰退。一如M τΑ7 Β7 425609 V. Description of the invention (1. Field of the invention: The present invention relates to a semiconductor device, particularly a method for manufacturing a very short channel n-type metal-oxide-semiconductor field-effect transistor (nMOS). 2. Background of the invention: In the field of semiconductor technology today, metal-oxide-semiconductor field-effect transistors (MOSFETs), especially CMOS, have been widely used, and in the era of ultra-large integrated circuits (ULSI), the size of components has been increasingly reduced to achieve higher performance. While component sizes are shrinking, parasitic circuits like RC delays and series resistances between source and non-electrodes can easily degrade the performance of the circuit. As M τ
Takagi 等人在’’IEDM Tech. Dig. ρ.4455,1 996” 提出在閘極 上傳遞延遲是通道寬度和閘極片電阻的函數。因此在閘極某 一定值的片電阻值將限制可用於ULSI之最大的通道寬度。 在源極和 >及極之歐米接觸（Ohmic contacts)與閘極製程 自我射準Ti *夕化物對要求低的閘極片電阻阻值與低源極和 ΐ及極之阻值是一個不錯的選擇，製造深短通道金氧半場效電 晶體以符合高速電路卻一如Μ, Ono等人在”IEDM Tech. Dig p. 1 1 9,1 993”所提出’’由於時下光學微影技術的限制要定義 小於0 · 1 μιη的閘極長度是很困難的。 (請先閲讀背面之注意事項再填寫本頁) .裝 線 經濟部智慧財產局員工消費合作社印製 2 本紙張尺度適用中國國家標準（CNS ) Α4规格（2Ι0Χ297公釐） 4 256 09 五、發明説明（ A7 B7 3. 發明目的及概述： 鑒於上述之發明背景中，傳統的製造極短通道金氧半場 效電晶體技術有光學微影技術的瓶頸，本發明的方法提供利 用簡單的製程以製作具有自我對準矽化物接觸之極短通道 金氧半場效電晶體元仵。以下將概述如下β首先在梦基材上 長一層薄的閘極氧化層，然後以LPCVD方法沉積一無摻雜 的複晶矽層或者非晶質矽（α-Si)膜。接著沉積第一介電層和 光阻層。然後定義閘極區於此光阻層上接著蚀刻光阻層之 閘極區以使其寬度縮減，而使閘極寬度可以減少到傳統之微 影製程所無法達到的尺寸。 再以殘留之光阻層當做罩幕蝕刻第一介電層。接著我們 使用殘留之光阻層和第一介電層當做罩幕、蝕刻無摻雜的複 晶矽層以形成一極短通道閘極》其次以化學氣相沉積一磷;5夕 玻璃（PSG)膜沉積再以回蝕刻以形成PSG側間隙壁。去除第 一介電層。緊接著一貴金屬或耐高溫金屬沉積於所有的區 域。高劑量的砷或磷離子佈植穿越金屬層至基材以形成源/ 汲極區。接著施以兩階段快速熱退火（RTP)製程形成自我對 準矽化物接觸以製造極短通道η型金氧丰場效電晶體。 4. 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述： 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ2.97公釐） (請先閲讀背面之注意事項再镇寫本頁} .裝. 經濟部智慧財產局員工消費合作社印製 五、發明説明（ A7 B7 '形此 形 形 定 在 後 用.，形 蝕材 是在 是 是 是 是 減 是層是 是基 驟層 驟 驟 驟 驟 縮 驟4驟 驟和 步梦 步 步 步 步 寸 步晶步 步極 的晶 的 的 的 的J1尺 的複的 的閘 程複 程 程 程 程 在 程雜程 程在 製的 製 製 製 製I區 製掺製 製屬 ， ， ， ， ，電 ，無- ，、 _ _·-極 __ n ___ 金 圖穿 圖；圖 圖 圖介！ 圖亥圖 圖 參 閘 t &皿 意赛 意上意 意 意一 意刻意 意 ί 示無 示層示 示 示第丨 示缺示 示高 面一 面矽面 面 面在夕 面，面 面* 截且 截晶截 截 載層1 截幕截 截或 橫並 橫複橫·，橫 橫矽k 橫罩橫 橫屬 一上 一的一上一 一二， 一式一 一金 之材 之雜之層之 之第中 之硬之 之貴 明基 明掺明電明 明在之 明做明，明鍍 發矽 發無發介發 發膜明 發當發壁發藏 本一 本此本一本 本化發。本層本Φ本後 據層。據在據第據 據氧本圖據矽據]^1據然 根化上根層根在根。根熱在意根二根#根層 為氧層為電為層為區為成為示為第為化為電 1 極化 2 介 3梦4 極 5 形 6 面 7 的 8 氧 9 介 圖閘氧圊一圖二圖閘圖溫圖載圖留圖SG圖一 一 極第第 { 低橫殘 P 第 成閘 成成 義較的 該成刻 (請先閲讀背面之注意事項再填寫本頁) -裝- -" 經濟部智慧財產局R工消費合作社印製 上； 圖10為根據本發明之一橫截面示意圖，製程的步驟是 實施離子佈植以形成源極和 >及極區， 圖11為根據本發明之一橫載面示意圖，製程的步驟是 實施兩階段的快速熱退火製程以形成SALICIDE和延伸的 4 本紙張尺度適用中國國家標準（CNS ) A4規格（2!0X297公釐） 經濟部智慧財產局員工消費合作社印製 425609 五、發明説明（） 源極和沒極區； 圖1 2為在本發明之另一實施例中，使用電漿擴散或低 能量離子植入方式以直接形成延伸之源極和汲極區的橫截 面示意圖； 圖1 3為在本發明之另—實施例中，形成側壁間隙壁於 第一矽層閘極結構上的橫截面示意圖； 圖14為根據本發明另一實施例中之—橫截面示意圖， 製程的步驟是實施離子佈植以形成源極和汲極區；以及 圖15為根據本發明另一實施例中之一橫截面示意圖， 製程的步驟是實施兩階段的快速熱退火製程以形成 SALICIDE和延伸的源極和沒極區。 5.發明詳細說明： 本發明的細節可參照圖示來加以詳細說明。本發明之目 的在提供一種方法，用以製作自我對準矽化物接觸極短通道 η型金氧半場效電晶體高速元件。以下將詳細說明製程的細 節如下：Takagi et al. In "IEDM Tech. Dig. Ρ.4455,1 996" proposed that the propagation delay on the gate is a function of the channel width and the gate chip resistance. Therefore, a certain value of the chip resistance at the gate will limit the available The largest channel width of ULSI. Self-emission at Ti source and Ohmic contacts and the gate process. Ti * The material requires low gate resistance and low source resistance. Extreme resistance is a good choice. Manufacturing deep-short-channel metal-oxide-semiconductor half-field-effect transistors to meet high-speed circuits is the same as that proposed by M, Ono, and others in "IEDM Tech. Dig p. 1 1 9,1 993". 'Due to the limitations of current optical lithography technology, it is difficult to define a gate length less than 0 · 1 μιη. (Please read the precautions on the back before filling this page.) Printed 2 This paper size applies Chinese National Standard (CNS) A4 specification (2IO × 297 mm) 4 256 09 V. Description of the invention (A7 B7 3. Object and summary of the invention: In view of the above background of the invention, the traditional manufacturing of very short channels Metal Oxide Half Field Effect Transistor The technology has the bottleneck of optical lithography technology. The method of the present invention provides the use of a simple process to fabricate a very short-channel metal-oxide-semiconductor field-effect transistor with self-aligned silicide contact. The following will be summarized as follows. A thin gate oxide layer is grown thereon, and then an undoped polycrystalline silicon layer or an amorphous silicon (α-Si) film is deposited by LPCVD. Next, a first dielectric layer and a photoresist layer are deposited. Then, a gate is defined. The electrode area is then etched on the photoresist layer to etch the gate area of the photoresist layer to reduce its width, so that the gate width can be reduced to a size that cannot be achieved by the traditional lithography process. The remaining photoresist layer is used as The first dielectric layer is etched by the mask. Next, we use the remaining photoresist layer and the first dielectric layer as the mask, and etch the undoped polycrystalline silicon layer to form a very short channel gate. Deposition of a phosphorous; PSG film was deposited and etched back to form a PSG side barrier. The first dielectric layer was removed. A precious metal or a refractory metal was then deposited in all areas. High doses of arsenic or phosphorus Ion implantation through metal To the substrate to form the source / drain region. Then a two-stage rapid thermal annealing (RTP) process is performed to form a self-aligned silicide contact to produce a very short channel n-type metal oxide field effect transistor. 4. The diagram is simple Note: The preferred embodiment of the present invention will be described in more detail in the following explanatory texts with the following figures: This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 2.97 mm) (Please read first Note on the back, write this page again}. Packing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (A7 B7 'This shape is set for later use. The minus layer is the base layer, the layer, the step, the step, the step, the step, the step, the step, the step, the step, the step, and the step. Miscellaneous process in-process system manufacturing system I zone system blending system,,,,,, electricity, no-,, _ _ · -pole__ n ___ Gold picture through picture; picture picture introduction! Tu Haitu Tushen gate t & wares intentionally intentionally intentionally deliberately deliberately show no display layer display display section 丨 show lack of display high surface side silicon surface surface surface surface, surface surface * truncated crystal Intercepting layer 1 Intercepting or crosswise and horizontally horizontally, horizontally and horizontally, silicon, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, vertically, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally, horizontally. The most precious, the brightest, the brightest, the brightest, the brightest, the brightest, the brightest, the brightest, the most beautiful, the brightest, the most beautiful, the brightest, the most beautiful, the best, the best, the best, the best, the best. This layer is the current data layer. According to the data, according to the oxygen map, the silicon data] ^ 1 It is true that the roots are rooted. The root heat cares about the root two roots #the root layer is an oxygen layer is an electric layer and a zone is a zone which is shown as the first change into electricity 1 polarization 2 dielectric 3 dream 4 pole 5 shape 6 face 7 8 oxygen 9 dielectric gate oxide A picture, two pictures, brake map, temperature map, leave map, SG picture, one pole, {the low transverse residual P, the gate into the righteousness of the moment (please read the precautions on the back before filling this page) -install- -"Printed by the R Industrial Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; Figure 10 is a schematic cross-sectional view according to the present invention. The process steps are to implement ion implantation to form the source and > and polar regions, and Figure 11 is According to a schematic diagram of the cross section of the present invention, the process step is to implement a two-stage rapid thermal annealing process to form SALICIDE and extended 4 paper sizes that apply Chinese National Standard (CNS) A4 specifications (2! 0X297 mm) Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 425609 V. Description of the invention () Source and non-polar regions; Figure 12 shows another embodiment of the present invention, using plasma diffusion or low energy ion implantation to directly form Schematic cross-section of extended source and drain regions; Figure 1 3 In another embodiment of the present invention, a schematic cross-sectional view of forming a sidewall spacer on the first silicon layer gate structure is shown. FIG. 14 is a schematic cross-sectional view according to another embodiment of the present invention. The process steps are: Ion implantation is performed to form source and drain regions; and FIG. 15 is a schematic cross-sectional view of another embodiment of the present invention. The steps of the process are a two-stage rapid thermal annealing process to form SALICIDE and extended sources. Polar and non-polar regions. 5. Detailed description of the invention: The details of the present invention can be described in detail with reference to the drawings. It is an object of the present invention to provide a method for fabricating a self-aligned silicide contacting an extremely short channel n-type metal-oxide half field effect transistor high-speed device. The details of the process will be described as follows:
參考圖1，在較佳實施例裡，首先提供一 <1〇〇>晶體方 向矽單晶基材2«先形成複數個厚場氧化層（fieid 〇xide簡 稱F 0 X)區4於此矽晶上做為元件彼此間的區隔之用。例如 F 0 X區4可經由微影和蝕刻步驟來蝕刻氮化矽、二氧化矽 複合層，在去光阻、濕式清潔後，在氧蒸氣環境下以熱氧化 法（thermal oxidation)長 FOX 區 4 至約 3000-8000 埃。FOX 5 本紙張尺度適用中囤國家標準（CNS ) A4規格（210X297公釐） J Γ裝------訂---Ί ----隸 ( I J (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 區4。 一如習知技術所熟悉，其也可用複數個淺溝渠（shallow trench)隔絕取代之《接著在基材2上形成一二氧化矽層1 2 以做為閘極之氧化層。一般，二氧化矽層6是在含氧的氣氛 在約7 0 〇 _ 11 〇 〇。c下來形成。在本實施例裡二氧化矽層的厚 度約1 5-250埃。其次*二氧化矽層6也可以用任何適當的 氧化方式和步驟來形成。 然後用低壓化學氣相沉積製程沉積一無摻雜的複晶矽 層8沉積在F Ο X區4和二氧化矽層6上。無摻雜的複晶矽 層8可用非晶石夕（amorphous-silicon)層取代之，在一較佳實 施例裡無摻雜的複晶矽層8的厚度大約500-3000埃。 參考圖2，接著形成第一介電層1〇復蓋在無摻雜的複 晶矽層8之上。在較佳實施例裡，第一介電層10可使用如 氮氧化矽、氧化矽、以及氮化矽等的材質，以氮氧化矽所形 成之第一介電層10而言，即可做為一抗反射層，以增加後 續製程中定義圖案時的精確度，第一介電層10本例中的厚 度約為100-2000埃》 參考圖3，第二矽層12接著沉稍在第一介電層1〇上。 在一較佳實施例裡第二矽層12的厚度大約是500-3000埃， 第二矽層12可為一未摻雜之矽層、亦可使用摻雜之矽層， 例如一 N型摻雜之多晶矽層。 接著如圖4所示，可利用習知的微影製程，以光阻層當 做罩幕’蝕刻第二矽層12以定義閘極區12a，以氮氧化矽 所形成之第一介電層10而言，即可於應用微影製程定義閘 (請先Μ讀背面之注意事項再填寫本頁} -裝- 訂 1 2 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇><297公釐） 425609五、發明説明（） A7 B7 經濟部智慧財產局員工消費合作社印製 極區12a時’做為底部的抗反射層，以增加定蠤 確度。 義圖案時的精 然後如圖5，一低溫蒸氣氧化製程用以氧 千L 1匕第二錄展 12。在此一氧化製程實施後，在殘餘之第二 m ^ 1 2 .，卜i生異_ 一熱氧化膜14。在一較佳實施例裡，低溫蒸氣氣化製 β 在約7〇0-9〇0 〇C下持續5-60分鐘來達成程是 ^之外，低溫 蒸氣氧化製程也可以用低溫乾氧製程來做。參去 ' > T圃6，熱氣 化膜14可由BOE或豨釋的氫氟酸溶液加以去昤 „ 7 ^友除，以留下 寬度較為縮減的殘留之第二矽層12。 在另一實施例之中，可應用不同的方法來達到縮減第二 矽層1 2閘極區1 2 a的效果，以較佳實施例而言，可直接對 圖4之中、第二矽層12的閘極區12a直接進行蝕刻，本例 中傾向使用具等向性的乾触刻製程，例如使用電渡敍刻的方 式，利用含氯氣體做為主要的反應氣體，以達到所需的等向 性乾蝕刻特性，而使第二矽層1 2的閘極區1 2a寬度縮減成 圖6中所示之較窄的殘留之第二矽層12。 此外，在另一個不同的實施例之中，第二矽層可使用一 光阻層加以取代之，並直接應用微影製程於光阻層上即可定 義閘極區，而不需使用蝕刻的製程，並於閘極區定義後使用 乾蝕刻的方式使其寬度縮減，例如可應用氧氣電漿等的光阻 剝除製程，去除部分的光阻而使其寬度與高度同時縮減。 因此，藉由上述三種不同方式，即可使第二矽層或光阻 層上所定義的閘極區寬度得到縮減，例如目前微影製程所能 精確定義的尺寸寬度，約在1微米至0.1微米左右，而應用 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁} -裝* .線. 2 〇 π 〇 A7 B7 五、發明説明（） 經濟部智慧財產局員工消費合作社印製 本發明中的製程，則可使閘極區定義的寬度縮減到約〇. 1微 米至10奈米（nanometer)、甚至是更小的尺寸範圍之内，而 能突破傳統微影及蝕刻製程的尺寸限制’應用以形成極窄通 道的金氧半場效電晶體。 之後即以尺寸縮減後的殘留第二矽層或光阻層12做為 硬罩幕（hard mask)、蚀刻第一介電層1〇’如圖6所示。在 一較佳實施例裡，第一介電層1 〇可以用乾性蝕刻法去除。 電漿蝕刻劑可選自CF4/02，CHF3，C2F6 ’ SFs/He族群。接 著我們使用第二矽層12和氮化矽層1〇覆蓋層當做罩幕蝕 刻無#雜的複晶*夕層8以形成一極短通道閘極，如圖7所 示。蝕刻劑可選自 SiCl4/Cl2，BC13/C12，Br2/SF6。 其次參考圖 8，以化學氣相沉積一磷矽玻璃 (phosphosilicate glass 簡稱 PSG)氧化膜 16 沉積在 FOX 區 4 上（對pMOSFET而言則是硼矽玻璃BSG氡化膜）無摻雜的複 晶矽層8與基材2上面。接著非等向性蝕法使用於PSG氧 化膜16以形成PSG氧化側隙壁 （side-wall spacer)16於閘 極8的侧壁上。在本較佳實施例裡，P S G氧化膜1 6所形成 之PSG氧化侧隙壁是當做擴散源以形成延伸的源汲極接面 (junction)，以使其符合最小接面深度的要求》 在其他的較佳實施例之中，亦可使用不同的應用方式來 形成較淺的延伸的源汲極接面區，參見圖12所示，可不使 用上述的P S G氧化侧隙壁，而利用電漿擴散（或稱電漿浸入， plasmaimmersion)、或是低能量離子植入的方式直接形成延 伸的源汲極接面區28於基材2之内。以形成nMOSFET而Referring to FIG. 1, in a preferred embodiment, a <1〇〇> crystal-oriented silicon single crystal substrate 2 is first provided, and a plurality of thick field oxide layers (fieid 0xide, referred to as F 0 X) are first formed. This silicon is used as a separation between the components. For example, the F 0 X region 4 can be used to etch the silicon nitride and silicon dioxide composite layers through lithography and etching steps. After photoresist removal and wet cleaning, FOX can be grown by thermal oxidation in an oxygen vapor environment. Zone 4 to about 3000-8000 Angstroms. FOX 5 This paper size is applicable to the national standard (CNS) A4 specification (210X297 mm) J Γ installed ------ ordered --- Ί ---- li (IJ (Please read the precautions on the back before (Fill in this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description () Zone 4. As is familiar with the conventional technology, it can also be replaced by a plurality of shallow trenches. A silicon dioxide layer 1 2 is formed on the substrate 2 as an oxide layer of the gate. Generally, the silicon dioxide layer 6 is formed in an oxygen-containing atmosphere at about 700-1100. C. The thickness of the silicon dioxide layer in the embodiment is about 1 to 250 Angstroms. Secondly, the silicon dioxide layer 6 can also be formed by any appropriate oxidation method and step. Then, an undoped layer is deposited by a low-pressure chemical vapor deposition process. A polycrystalline silicon layer 8 is deposited on the F 0 X region 4 and the silicon dioxide layer 6. The undoped polycrystalline silicon layer 8 may be replaced by an amorphous-silicon layer, in a preferred embodiment The thickness of the undoped polycrystalline silicon layer 8 is about 500-3000 Angstroms. Referring to FIG. 2, a first dielectric layer 10 is then formed and covered with On the undoped polycrystalline silicon layer 8. In a preferred embodiment, the first dielectric layer 10 can be made of materials such as silicon oxynitride, silicon oxide, and silicon nitride, and is formed of silicon oxynitride. As for the first dielectric layer 10, it can be used as an anti-reflection layer to increase the accuracy of the pattern definition in subsequent processes. The thickness of the first dielectric layer 10 in this example is about 100-2000 Angstroms. 3. The second silicon layer 12 is then sunk slightly on the first dielectric layer 10. In a preferred embodiment, the thickness of the second silicon layer 12 is about 500-3000 angstroms, and the second silicon layer 12 may be a thin layer. A doped silicon layer can also be used, such as an N-type doped polycrystalline silicon layer. Then, as shown in FIG. 4, a conventional photolithography process can be used to use a photoresist layer as a mask for etching. The second silicon layer 12 defines the gate region 12a. For the first dielectric layer 10 formed by silicon oxynitride, the gate can be defined in the lithography process (please read the precautions on the back before filling this page) }-Binding-Order 1 2 This paper size applies to China National Standard (CNS) A4 specification (21〇 > < 297mm) 425609 V. Description of invention () A7 B7 When the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the polar region 12a, it was used as an anti-reflection layer at the bottom to increase the accuracy of the pattern. The precision of the pattern is then shown in Figure 5. A low-temperature steam oxidation process uses oxygen 1000 L 1 The second recording exhibition 12. After the implementation of this oxidation process, the remaining second m ^ 1 2, a different thermal oxide film 14. In a preferred embodiment, the low temperature vapor gasification system β is about 5-60 minutes at about 7000-900 ° C to achieve the process. In addition, the low-temperature steam oxidation process can also be performed by a low-temperature dry oxygen process. Refer to '> T 6, the thermal vaporization film 14 can be removed by BOE or the release of hydrofluoric acid solution 7 to remove it to leave a second silicon layer 12 with a narrower width. In another In the embodiment, different methods may be applied to achieve the effect of reducing the gate region 12 a of the second silicon layer 12 2. In a preferred embodiment, the second silicon layer 12 in FIG. 4 may be directly The gate region 12a is directly etched. In this example, an isotropic dry-contact etch process is preferred. For example, electro-etching is used. Chlorine-containing gas is used as the main reaction gas to achieve the required isotropy. Dry etching characteristics, so that the width of the gate region 12a of the second silicon layer 12 is reduced to the narrower residual second silicon layer 12 shown in Fig. 6. In addition, in another different embodiment The second silicon layer can be replaced by a photoresist layer, and the lithography process can be used directly on the photoresist layer to define the gate region, instead of using an etching process, and after the gate region is defined, a dry region is used. The etching method reduces its width. For example, a photoresist stripping process such as oxygen plasma can be applied to remove a part. The width and height of the photoresist are reduced at the same time. Therefore, the width of the gate region defined on the second silicon layer or the photoresist layer can be reduced by the above three different methods, for example, the current lithography process can accurately The defined size width is about 1 micron to 0.1 micron, and the application of this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page} -Install * Line. 2 〇π 〇A7 B7 V. Description of the invention () The process of printing the present invention printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs can reduce the width of the gate region definition to about 0.1 micron to 10 nanometers. Meter (nanometer), or even smaller size range, and can break through the size limitation of traditional lithography and etching process' application to form a very narrow channel of gold-oxygen half field effect transistor. Residue after size reduction The second silicon layer or photoresist layer 12 is used as a hard mask to etch the first dielectric layer 10 ′ as shown in FIG. 6. In a preferred embodiment, the first dielectric layer 10 may be Remove by dry etching. The etchant can be selected from the CF4 / 02, CHF3, C2F6 'SFs / He groups. Next, we use the second silicon layer 12 and the silicon nitride layer 10 as the cover layer as the mask etch. A very short channel gate is formed, as shown in Fig. 7. The etchant may be selected from SiCl4 / Cl2, BC13 / C12, Br2 / SF6. Next, referring to Fig. 8, a chemical vapor deposition of a phosphosilicate glass (referred to as PSG) ) An oxide film 16 is deposited on the FOX region 4 (for pMOSFET, it is a borosilicate glass BSG film) and the undoped polycrystalline silicon layer 8 and the substrate 2 are deposited thereon. An anisotropic etching method is then applied to the PSG oxide film 16 to form a PSG oxide side-wall spacer 16 on the sidewall of the gate electrode 8. In this preferred embodiment, the PSG oxide side wall formed by the PSG oxide film 16 is used as a diffusion source to form an extended source-drain junction to meet the minimum junction depth requirement. In other preferred embodiments, different application methods can also be used to form a shallower extended source-drain junction area. As shown in FIG. 12, instead of using the PSG oxidized side wall, plasma can be used. Diffusion (or plasma immersion) or low-energy ion implantation directly forms an extended source-drain junction area 28 within the substrate 2. To form an nMOSFET
S 本紙張尺度適用中國國家標準（CNS > Α4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁} .裝· 訂 .… ' '八 一 ；J A7 --- ------B7五、發明説明（） 經濟部智慧財產局員工消費合作社印製 言，電漿擴散的製程，可於使基材2曝露於具有磷離子或砷 離子的電漿環境之中，而使所需的離入進入基材2的表面 處•而若使用低能量離子植入的製程，可直接植入磷離子或 砷離子，以本例而言，其植入之能量約為〇1至5KeV，所 形成之摻雜濃度約為1E13至1E15i〇ns/cm2。，以形成 pMOSFETs的應用而言’上述中電漿擴散的製程及低能量離 子植入的製程中的磷離子或砷離子，則可使用硼離子加以 代之。 而以使用上的方式形成延伸的源汲極接面區而言，即可 形成未摻雜的側壁結構3 0於閘極結構8之侧壁上，如圖j 3 所示’未摻雜的側壁結構3 0可使用如氧化矽、氮氧化梦、 以及氣化矽等的材質，利用沈積及回蝕的製程加以形成，在 未摻雜的侧壁結構30形成之後，其後續形成矽化金屬接觸 的製輕與上述使用P s G氧化側隙壁之實施例大致相同，其 細節可參照后述之步驟介紹。 如圖9所示，在上述的PSG氧化側隙壁16、或是未摻 雜的側壁結構3 0形成之後，第一介電層1 〇即可利用溼蝕刻 的方式將之去除，例如使用熱H?P〇4溶液去除氮化矽的第 一介電層10〇緊接著使貴金屬或耐高溫金屬l8(refractory raetal)沉積於所有的區域β在本較佳實施例裡貴金屬或耐高 溫金屬18可選自1丨，评，（：〇，1>1，>^，0等金屬族群的其 中之一種》 參考圖1 0，可藉由閘極8和P S G側間隙璧1 6做為罩幕， 高劑量的砷或磷離子佈植穿越金屬層18至基材2以形成源 9 本紙張尺度適用中國國家標準（CNS) A4规格（210X2S>7公釐） .1------^--Ί 裝--. ( f請先閲讀背面之注意事項再填寫本頁} .訂 425609 A7 B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) /汲極區20 (source/drain regions)在一較佳實施例裡，離子 佈植的能量約 5-150 keV，劑量約 5xl014-5xl016ions/cm2, 以形成pMOSFETs的應用而言，則可使用硼離子來取代上 述的珅或磷離子。以應用未摻雜的側壁結構3 0的實施例而 言，其示意圖如圊14。 參考圖11’為了形成自我對準矽化物接觸22 (sal icided contact)與延伸源/汲極接面 24，接著施以兩階段快速熱退 火（RTP)製程。第一段的RTP製程是用來形成金屬矽化物在 閘極8的上面。在本較佳實施例裡，第一道的RTP製程的 溫度約300-700 °C，時間約30- 1 80秒，PSG侧間隙壁16内 部分的離子即會於溫度的效應下擴散進入其下方的基材2 之内。 接著使用蝕刻製程去除任何未被反應的金屬材質，而僅 於閘極8、源極和汲極區20的上方留下金屬矽化物22。並 於去除金屬層之後’進行第二道的RTP製程，以使金屬矽 化物在經過熱處理之後進行另一相態（phase)，以提供較佳 的電性，並使PSG側間隙壁1 6的雜質進一步被驅入基材2 之内，形成所需的延伸源極和汲極區接面24。在較佳實施 例裡，第二道的RTP製程的溫度約700- 1 1 50 °c，時間約 1 0-1 00秒。以應用未摻雜的侧壁結構30的實施例而言，其 示意圖如圖1 5。 經濟部智慧財產局員工消費合作社印製 藉由上述步驟中利用P S G側間隙壁1 6、電漿擴散、或 是低能量離子植入的方式’可形成極淺的延伸源極和汲極區 接面β 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐）S This paper size applies to Chinese national standards (CNS > Α4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page}. Binding and binding .... '' Bayi; J A7 --- ------ B7 V. Description of Invention () The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a statement that the plasma diffusion process can be used to expose the substrate 2 to the plasma environment with phosphorus ions or arsenic ions. In order to make the required ionization enter the surface of the substrate 2, and if a low-energy ion implantation process is used, phosphorus ions or arsenic ions can be directly implanted. In this case, the implanted energy is about It is 〇1 to 5KeV, and the doping concentration formed is about 1E13 to 1E15ions / cm2. For the application of forming pMOSFETs, the phosphorous ions in the above-mentioned plasma diffusion process and low-energy ion implantation process Or arsenic ions, boron ions can be used instead. In terms of using the extended source-drain junction area, an undoped sidewall structure 30 can be formed on the sidewall of the gate structure 8 As shown in Figure 3, 'un-doped sidewall structure 3 0 can be used such as silicon oxide, nitrogen oxide The materials such as silicon and silicon carbide are formed by a process of deposition and etch-back. After the undoped sidewall structure 30 is formed, the subsequent fabrication of silicon silicide contacts and the use of P s G oxidation side wall The embodiments are substantially the same, and the details thereof can be introduced with reference to the steps described below. As shown in FIG. 9, after the PSG oxide sidewall spacer 16 or the undoped sidewall structure 30 is formed, the first dielectric layer is formed. 10 can be removed by wet etching, for example, the first dielectric layer of silicon nitride is removed using a hot H? P04 solution. Then a precious metal or refractory metal 18 (refractory raetal) is deposited on all In the preferred embodiment, the region β of the precious metal or the high-temperature-resistant metal 18 may be selected from 1 丨, comment, (: 0, 1 > 1, > ^, 0 and one of the metal groups). Referring to FIG. 10, The gate 8 and PSG side gap 璧 16 can be used as a cover. High-dose arsenic or phosphorus ions are implanted through the metal layer 18 to the substrate 2 to form the source 9. This paper size applies to Chinese National Standard (CNS) A4 Specifications (210X2S > 7mm) .1 ------ ^-Ί 装-. (F Please read first Please note this page before filling in this page}. Order 425609 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) / Drain Region 20 (source / drain regions) in a preferred embodiment Here, the energy of ion implantation is about 5-150 keV, and the dosage is about 5xl014-5xl016ions / cm2. For the application of forming pMOSFETs, boron ions can be used instead of the above-mentioned thorium or phosphorus ions. For an embodiment in which an undoped sidewall structure 30 is applied, a schematic diagram is shown as 圊 14. Referring to FIG. 11 ', in order to form a salicide contact 22 and an extended source / drain interface 24, a two-stage rapid thermal annealing (RTP) process is performed. The first RTP process is used to form a metal silicide on the gate 8. In this preferred embodiment, the temperature of the first RTP process is about 300-700 ° C, and the time is about 30-1 80 seconds. The ions in the PSG-side spacer 16 will diffuse into it under the effect of temperature. Underneath substrate 2. An etching process is then used to remove any unreacted metal materials, leaving metal silicide 22 only above the gate 8, source, and drain regions 20. After the metal layer is removed, a second RTP process is performed to make the metal silicide undergo another phase after heat treatment to provide better electrical properties and make the PSG side spacer 16 The impurities are further driven into the substrate 2 to form the required extended source and drain interface 24. In a preferred embodiment, the temperature of the second RTP process is about 700-1150 ° C, and the time is about 10-1 00 seconds. For an embodiment in which an undoped sidewall structure 30 is applied, its schematic diagram is shown in FIG. 15. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. By using the PSG side spacer 16 in the above steps, plasma diffusion, or low-energy ion implantation, a very shallow extended source and drain region can be formed. Surface β This paper size applies to Chinese National Standard (CNS) Α4 specification (210 X 297 mm)
4 256 09 - 五、發明説明（ 明古藉.由上述之各個實施例與方法步驟，可形成本發 明中之具冑自我對準石夕化物接罙短通道金氧半場效 晶體’如圖十一所示，其可包含：閉極結構8、側間隙壁16、 源極錢極區域20、硬化金屬接觸22、以及延伸源極與沒 極區域24 ;閘極結構8係形成於基材2上，以較佳例而言， 閘極結構8之寬度約為〇」微米至j 〇奈米之間；侧間隙壁 16則形成於閘極結構之側壁上；源極與汲極區域則形成 於基材2之内；矽化金屬接觸22則形成於閛極結構8與源 極與汲極區域20之上；而延伸源極與汲極區域24則形成於 基材2之内，側間隙壁16下方處。在較佳實施例之中，矽 化金屬22於閘極結構2〇上方處係可具有相對於側間隙壁 16下凹之結構。 本發明的優點是（1)自我對準矽化物接觸方法製造極短 通道η型金氧半場效電晶體之製程可用時下的微影製程技 術來達成；並且（2)延伸的源極/汲極區接面可以上述的多種 不同技術提供極淺的深度，以改善短通道效應。 經濟部智慧財產局員工消費合作社印製 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神 下所完成之等效改變或修飾，均應包含在下述之申請專利範 圍内°例如，本發明之方法提到自我對準矽化物接觸方法製 造深短通道η型金氧半場效電晶體之製程也同樣適用於ρ 型金氧半場效電晶體之製程而PSG則代換以BSG，另外互 補式金氧半場效電晶體之製程也同時包括在内。 11 本紙張尺度適财_家橾準（CNS ) Α4規格（21())<;297公董4 256 09-V. Description of the invention (Bengu borrowed. From the above embodiments and method steps, a self-aligned lithium oxide-connected short-channel metal-oxygen half-field-effect crystal in the present invention can be formed. As shown in the figure, it may include: a closed electrode structure 8, a side spacer 16, a source electrode region 20, a hardened metal contact 22, and an extended source and non-electrode region 24; the gate electrode structure 8 is formed on the substrate 2 Above, in a preferred example, the width of the gate structure 8 is between about 0 "micrometers and j 0 nanometers; the side gap 16 is formed on the side wall of the gate structure; the source and drain regions are formed Within the substrate 2; the silicided metal contact 22 is formed on the ytterbium structure 8 and the source and drain regions 20; and the extended source and drain regions 24 are formed on the substrate 2 with side gaps 16 below. In a preferred embodiment, the silicided metal 22 may have a structure recessed relative to the side spacer 16 above the gate structure 20. The advantages of the present invention are (1) self-aligned silicide The contact lithography process for manufacturing extremely short-channel n-type metal-oxide half-field-effect transistors And (2) the extended source / drain region interface can provide a very shallow depth with a variety of different technologies as described above to improve the short channel effect. This is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below For example, the method of the present invention mentions the self-aligned silicide contact method for manufacturing deep and short channel n-type metal-oxide-semiconductor field-effect transistors. The process is also applicable to the process of p-type metal-oxide-semiconductor half-effect transistors. PSG is replaced. With BSG, the manufacturing process of complementary metal-oxide-semiconductor half-effect transistors is also included. 11 Paper sizes are suitable for financial purposes_ 家 橾 准 (CNS) Α4 size (21 ()) < 297 public directors