TW457725B - Thin film transistor device structure and the manufacturing method thereof - Google Patents

Abstract

A thin film transistor device structure and the manufacturing method thereof are disclosed, wherein the data line and the scanning line are completed on the same photomask. This method comprises: form an active layer on the silicon substrate, then form a gate insulating layer to cover the active layer, then form a conductive layer and define the gate and conductive wire, then do self-alignment using this gate, form source/drain on this active layer, and form a passivation layer on this gate insulating layer to cover the gate and metal line. Next, define the via hole to pass through this passivation layer to the source/drain and conductive wire, fill ITO into the via hole, electrically connect the source/drain and the conductive wire, then, define this conductive material.

Description

457725 V. Description of the invention (1) The present invention relates to a thin film transistor (TFT) element structure and manufacturing method thereof, and more particularly to a thin film transistor with a reduced photomask Element structure and manufacturing method: In terms of current displays, Liquid Crystal Display (LCD) is a display with great potential. Due to the advantages of low radiation and small size, LCD monitors can be used in many applications, such as screens used in notebook computers. Due to the low radiation of LCDs, which are relatively harmless to the human body, some desktop computers have also begun to use liquid crystal displays to replace traditional cathode ray tube (CRT) displays. According to the components used in liquid crystal displays, they include: Super-Twisted Nematic (STN) -LCD and Thin Film Transistor (TFT) -LCD. In terms of viewing angle breadth, since STN-LCD systems are more restricted, they are gradually being replaced by TFT-LCDs with larger viewing angle breadths. Please refer to FIGS. 1A to 1C, which are cross-sectional views showing a structure of a conventional thin film transistor (Th 丄 n Film Transistor 'TFT) device manufacturing process. First, as shown in FIG. 1A, the TFT element structure of the present invention is formed on a dream substrate 101 and a buffer layer 102. Therefore, the material of the substrate 1 0 1 may be polycrystalline stone (ρ ο 1 y s i 1 i c ο η, p-S i), or non- | crystalline silicon (a-Si). An active layer 1 2 0 is formed on the buffer layer 102, and then a source / non-polar (50111 ^ 6 / (^ & 丨 11) 3/1) is formed on the active layer 1 2 0 by ion implantation, where , The active layer is used as a 1 ^ component

Page 4 4S7725 V. Channel Region of the Invention Description (2). Next, a gate insulating layer (_ gateinsu 1 at 〇r) 103 is formed on the buffer layer 102. For example, a gate insulating layer is formed by a plasma enhanced chemical vapor deposition (PECVD) method. 103. The gate insulating layer 103 covers both the source / drain S / D and the active layer 120 at the same time. The material of the gate insulating layer 103 may be silicon oxide (SiOx) or silicon nitride (SiNx). As shown in FIG. 1A, the step coverage formed by the gate insulating layer 103 covering the source / drain S / D and the active layer 120 is to provide a good dielectric layer for subsequent formation. Ladder coverage effect. Then, a gate G is formed on the gate insulating layer 103. The gate G is formed on the step of the gate insulating layer 103. This structure is called an upper gate (τ0p Gate) structure. In addition, the gate G is used to form a Scan Line of the LCD panel as shown in FIG. 1. Next, as shown in FIG. 1B, a dielectric layer 104 is formed on the gate insulating layer 103 and the gate G. The manufacturing process of the dielectric layer 104 may be the following two methods: (1) Shi Xi oxide (310) and 117 (^ 〇2611 plasma hydrogenation) 1¾ #; or (2) Shi Xi atmosphere (SiNx) is deposited by PECVD, and then obtained by high temperature annealing. Because the dielectric constant of the south molecular material will affect the capacitance of the cross capacitor, if the dielectric constant of the polymer material is larger, the cross The capacitance value of the capacitor will also be larger. As mentioned above, the larger the capacitance value of the cross capacitor will also affect the delay time of the LCD panel. That is, the dielectric B number of the polymer material will affect the LCD panel Delay time. 457725 V. Description of the invention (3) Next, it is necessary to form a via hole (via ho 1 e) 1 0 6, 1 0 7 »For example, to form a via hole 1 by lithography and etching. 6, 107, to the source / drain S / D, as shown in Figure 1B. Of course, using photolithography and etching methods to form the photoresist material required for the vias 106 and 107, It can be positive photoresistor or negative photoresistor. For example, when using positive photoresistor, you can use the lithography process to directly Positive photoresist can be patterned. After that, as shown in FIG. 1C, a metal layer is deposited to fill the via holes 106 and 107, and source / drain metal wires 108 and 109 are defined. Next, a passivation layer 110 is formed over the dielectric layer 104 and covers the source / drain metal wires 108 and 109 at the same time. Finally, a conductive layer 111 is formed to connect the source / drain metal wires. 1 0 9, for example, define an opening on the protective layer 1 10 to the source / drain metal wire 109, and then fill in a conductive material to form a conductive layer m, as the data line of the LCd panel. Indiuin Tin Oxide (IT0). The thin film transistor structure and its manufacturing method according to the above method 'includes at least seven photomasks, although the process of five photomasks has also been proposed', but the process is still It is rather inconvenient. In view of this, the object of the present invention is to provide a thin film transistor element structure with four photomasks and a method for manufacturing the same. According to the object of the present invention, 'proposing a thin film transistor element structure includes' a A silicon substrate, a first source / drain is located on the silicon substrate; a first source / and electrode is located on the silicon substrate; an active layer is located here

Page 6 15 7 72 5 V. Description of the invention (4) Between the first source / drain and the second source / drain of the silicon substrate; a gate insulating layer 'covers this first source / no-pole , The second source / non-electrode and the active layer;-the gate and a plurality of metal wires, which are located on the pseudo-insulating layer; a protective layer 'located on the gate insulating layer and covers the gate and the metal wires And a wire, which is located above the protection layer and connected to the first source / > and the bottom, the second source / non-electrode region, and the metal lines below. According to another object of the present invention, a manufacturing method for forming a thin film transistor element junction is provided. The manufacturing method includes forming a data line and a scanning line on the same light. Then form the gate insulating layer to cover the active layer, and then form Morey to be equal to ~ μ, 嫂 to follow, ^ Dan to form a conductive layer and define the gate and silver conduction 'Then, use this gate to automatically seat, ^ ^ , ^ Eye on the active layer to form the source electrode / 'Reformation — the protective layer in the gate insulation layer * ^ ρ., And the metal' line, and then define the interstitial hole, on top of 'to cover the gate Electrodes and wires, and then fill it with ITO through the two temples: protective layer to source / line electrical connection 'Next, define this conductive: material; source / drain and guide for the above purpose of the invention' The following is a special example-the preferred embodiment, ^; ^ advantages can be more obvious and easy to clarify the following: θ The attached drawings, a brief description of the drawings in detail: Figure 1A ~ 1C of the junction of the process of olfactory crystal elements, It shows the traditional structure cross-section; Figures 2A ~ 2B, which show the power generation crystal according to this FIG sectional structural elements of the process. β — The thin film of the preferred embodiment

^ 57726 V. Description of the invention (5) 1 0 1: Silicon substrate 1 0 2: Buffer layer 1 0 3, 2 0 3: Gate insulating layer 1 04: Dielectric layer

106, 107, 20 6a, 20 6b, 207a, 20 7b: via hole 108, 109, 208, 209: metal wire 110: protective layer m: conductive layer 120, 220: active layer 201: substrate 204: protective layer 210 : Conductive material restoration example

First, as shown in FIG. 2A, the TFT element structure of the present invention is formed on a substrate 201, preferably, polysilicon 'p-Si, or amorphous silicon (a-Si) ) And then laser to form polycrystalline silicon. Next, an active layer 220 is formed. The formation of the active layer 220 requires the first photomask to define the pattern of the active layer, and then, for example, silver engraving to remove unnecessary portions. Next, a gate insulator 203 is formed. For example, the gate insulating layer 203 is formed by a plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method. The gate insulating layer 203 covers at least the active layer 220. The material of the gate insulating layer 203 may be

Page 8 457725 V. Description of the invention (6) Silicon oxide (SiOx) or silicon nitride (SiNx). A conductive layer is then formed on the gate insulating layer 203, preferably by sputtering. Then, a second photomask is used to define the gate electrode G and the metal line 208 and the metal line 209 above the active layer 220. The gate G is formed on the step of the gate insulating layer 203, and this structure is called an upper gate structure. In addition, the gate G is used to form a scanning line (Scari Line) of the LCD panel. Then 'preferably, an ion implantation method is used to form a source / drain S / D on the active layer 220 by using self-alignment of the gate, wherein the active layer is used as Channel Region of TFT device. Therefore, it is clear that the formation of the gate electrode G and the metal wires 208 and 209 can be completed by a single photomask and a single yellow light process using the thin film transistor element forming method of the present invention, while the traditional method requires two photomasks. And two yellow light processes. Next, as shown in FIG. 2B, a passivation layer 204 is formed on the gate insulating layer 203, the gate G, and the metal lines 208 and 209. The protective layer 204 may be (1) a silicon oxide (Si Ox) obtained by deposition and hydrogenation (hydrogen plasma hydrogena ti on); or (2) a silicon nitride (SiNx) is deposited by a PECVD method, and then. Obtained from high temperature annealing. In addition, the protective layer 204 may be a phosphosilicate glass PSG. Next, via holes 206a, 206b, 207a, and 20b are formed. For example, lithography and etching are used to form the interstitial holes. I Chinese painting country _ hidden 丨 1 _1_1 1 round country _ _ country page 9 457 725 5. Description of the invention (7) 206a, 207a, to the source / immortal At s / β and vias 206b, 207b to metal lines 208, 209, as shown in FIG. 2B. In this case, a third photoresist is required. Of course, the photoresist material required to form the vias 206a, 2 06b, 20 7a, and 207b by using lithography and etching methods may be a positive photoresist or a negative photoresist. For example, when a positive photoresist is used, the lithography process can be used to directly pattern the positive photoresist. After that, a conductive material 21 is formed to fill the via holes 206a, 2 06b, 20 7a, and 207b, so that the conductive material 21 () and the source / drain S / D and the metal line 208, 209 is electrically connected as the data line of the LCi) panel. The conductive material 210 is preferably indium tin oxide (Indium Tin Oxide).

Oxide, ITO). At this time, the fourth mask is used again to define the conductive material 210. [Effects of the Invention] The thin film transistor structure and manufacturing method disclosed in the above embodiments of the present invention enable the data bus line and scan bus 1Ue to be completed on the same photomask. By avoiding the overlap of the data bus line and the scan bus line through layout, it can reduce costs, reduce errors, and improve yield. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

6. Scope of patent application]. A thin film transistor structure includes: a silicon substrate; a first source / drain located on the silicon substrate; a second source / drain located on the hard substrate An active layer between the first source / protocol and source / drain of the silicon substrate; ^ a gate insulating layer covering the first source / drain and second source / Ji_cai and active layer; a gate and a plurality of metal lines 'on the gate insulation layer;-a protective layer' is on the gate insulation layer and covers the gate and the metal lines; and The lead wire is located above the protection layer and is connected to the first source electrode; the second source / drain region and the metal lines below. 2. The thin film transistor device structure described in item 1 of the patent application scope, wherein the silicon substrate is a polycrystalline silicon substrate. 3. The thin film transistor structure described in item 1 of the patent application scope, wherein the silicon substrate is an amorphous silicon substrate. 4. The thin film transistor structure according to item 1 of the scope of the patent application, wherein the gate insulating layer is formed of broken oxide. 5. The thin film transistor structure according to item 1 of the scope of the patent application, wherein the gate insulating layer is formed by a gas; 6. The thin film transistor device structure according to item 1 of the scope of the patent application, wherein the protective layer is formed by silicon oxide (s 丨 〇χ) through hydrogenation and hydrogenation (hydrogen p! Asma hydrogenation). 4f7725 6. Scope of patent application 7. The thin film transistor structure described in item 1 of the patent application park J, wherein the protective layer is a silicon nitride (SiNx) deposited by PECVD 9 and then subjected to high-temperature tempering (annea 1 ing). 8. The thin film transistor structure described in item 1 of the scope of the patent application, wherein the protective layer is a phosphorous silicon glass (PSG). 9. The thin film transistor structure J described in item 1 of the patent scope, wherein the conductor is an indium tin oxide. 10. A manufacturing method for forming a thin film transistor structure, including providing a silicon substrate; forming an active layer; forming a gate insulating layer covering at least the active layer * to form a conductive layer; defining the conductive layer as a gate Electrode and a plurality of wires ♦, using the gate automatic alignment, a first source / drain and a first-source / non-electrode are formed on the active layer; a protective layer (Passiva ion layer) is formed on the active layer Over the gate insulation layer to cover the gate and the metal lines; define a plurality of vias, pass through the protection layer to the first source / drain, the second source / drain, and the wires Forming a conductive material to fill the vias, wherein the conductive material is electrically connected to the first source / lower electrode, the second source / drain electrode, and the wires respectively; and to define the conductive material. Page 13 457725 6. Application scope of patents' 11. The manufacturing method as described in item 10 of the scope of patent applications, wherein the dream substrate is a polycrystalline silicon substrate β 12. As described in item 10 of the scope of patent applications Manufacturing method 'wherein the silicon substrate is a polycrystalline silicon substrate formed by lasering an amorphous stone substrate. 13. The manufacturing method as described in item 10 of the scope of patent application, wherein the formation of the active layer is to first define a pattern using a first photomask and then use etching to remove unnecessary portions. The manufacturing method according to item 10, wherein the material of the gate insulating layer is silicon oxide. 15. The manufacturing method as described in item 10 of the scope of the patent application, 'the material for which the gate insulating layer is applied is silicon nitride "16. The manufacturing method as described in the scope of the patent application item 10, where the gate is The insulating layer is formed by plasma chemical vapor deposition (PECVD). 17. The manufacturing method according to item 10 of the scope of patent application, wherein the conductive layer is formed by sputtering. 18. The manufacturing method as described in item 10 of the scope of patent application, wherein the conductive layer is defined by a second photomask. 19. The manufacturing method as described in item 10 of the scope of patent application, wherein the protective layer is obtained by depositing silicon oxide (SiOx) through hydrogen plasma hy drogena ti on The manufacturing method as described in item 10 of the scope, wherein the protective layer is formed by depositing silicon nitride (S i NX) by a method of PECV D, and then obtained by annealing. 21. The manufacturing method as described in item 10 of the scope of patent application, wherein Page 14 # i7725 VI. Patent application Fanyuan The protective layer is phosphorus 22, such as some vias. 23. Such as the medium 24. Such as the interlayer 25. Such as a conductive material system 26. Such as a manufacturing method of the conductive material system f, wherein the application of the patent scope of the patent method ... c carved method to use a first Three photomasks, lithography, and # ._.. Less β Μ manufacturing methods, which are described in item 22 of the patent scope ". The photoresist material required for the hole is 〆 疋: ^, of which the system described in the patent application scope No. 22, the photoresist material required for the hole is 〆 · negative light P, and the second application patent scope is No. 10 The system is also 'ττηΓ. A fourth photomask is used to define the manufacturer described in Item 1 of Indium Tin Oxide (Indium ΐίη〇Xide patent application scope). Tz im Page 15