TW457687B - Programmable antifuse cell - Google Patents

Abstract

The present invention comprises an antifuse capacitor, said antifuse capacitor comprises an ion doped well formed in a substrate as the first electrode of the antifuse capacitor. The first dielectric layer is formed on the ion doped well as the dielectric layer of the antifuse capacitor, the first gate is located on the first dielectric layer as the second electrode of the antifuse capacitor. At least one selective capacitor is adjacent to the antifuse capacitor, which comprises the second dielectric layer formed on the substrate, said second dielectric layer is thicker than the first dielectric layer. The second gate is located on the second dielectric layer, its drain is adjacent to the ion doped well and its source is located on the other side of the carrier channel.

Description

457687 V. Description of the invention (i) Field of the invention: The present invention relates to an integrated circuit element, particularly a one-time programmable antifuse cel 1 structure. Background of the invention: In the process of making a very large integrated circuit on a wafer, it is desirable to include one-time programmable nonvolatile memory '. This device is tested in wafer probe or packaged. It can be used later for stylization. For example, a programmable non-volatile memory element can be used to replace defective random access memory (DRAM). A general programmable anti-fuse element cell includes an anti-fuse capacitor and an optional transistor. Selective transistors are used as selection elements to pass through different potentials to penetrate the dielectric layer of a specific antifuse capacitor. For a related prior art, please refer to US Patent No. 6, 0 4 0, 608, the invention name is "Field Effect Transistor for One-Time Programmable Nonvolatile Memory Element". There are many ways to form one-time programmable (0TP) non-volatile memory devices. among them

d 5 7 6 8 7 V. Description of the invention (2) One of the methods is to selectively open the current to cause a specific metal fuse to open. In addition, there is also the use of laser to change the resistance value of the semiconductor to achieve the goal. For literature on 〇 TP anti-refining, please refer to IEEE, 38th Annual International Reliability Physics Symposium, 2000, page 169, " One Time Programmable Drift Antifuse Cel 1 Rel iabi 1 i ty, which mentions the laser fuse as the current SRAM And the solution of DRAM redundancy. In addition, a programmable non-volatile memory based on gate oxide rupture (Gat e ox i de breakdown) is currently proposed and is compatible with the .CMOS process at 0.5 μm. Drift anti-fuse element (type ant to use device), its cross-section is shown in Figure 1. The anti-fuse capacitor 4 includes _ doped polycrystalline silicon 6, 5 η oxide layer 8 and 10 The capacitance is located on the wafer ratio. :: ί Junction. For example, shallow trench insulation barriers are used as anti-fuse components. = Cheng, Cheng has the following advantages in making anti-dissolved wire. The rolled layer 1 is easy to control. 'Well in a particular. NM0S 14 is adjacent to the above-mentioned anti-melt Kai Du μ. "The swift payoff of S 14 is infinite, = 1 = ::: ,,,,,,,,,,,,, and," will be used as a servant. Contains a source electrode 16. The anti-fuse stylization step can include using the NM0s 1 key element to access a lower potential, and Nuode uses bismuth a to comment on a wide range of anti-common practices. Bit 6: The selected crystal is 6 which can be compared with the P-type doped polycrystalline stone. // // Low pole 6: f / hybrid polycrystalline circuit schematic diagram can be seen in the figure:. m-formula

Page 6 457687 V. Description of the invention (3) However, the above-mentioned anti-fuse element has the following disadvantages: the above-mentioned drifting NMOS 1 4 occupies too large an area and cannot really solve the problem of high potential reliability. In addition, the above technology requires a higher power supply or charge pumping circuit. Purpose and Summary of the Invention: The object of the present invention is a structure of an anti-fuse element cell. Another object of the present invention is to provide a selective transistor oxide layer with respect to the thickness of the anti-dazzle wire oxide layer to facilitate the improvement of reliability. Therefore, the present invention does not need a high potential to penetrate the anti-fuse, does not need the drift NMOS of the prior art, and can save the production of N-well space and the high power supply or charge pumping circuit. More importantly, the present invention is fully compatible with the C M 0 S process. The anti-fuse element cell of the present invention comprises: an anti-dazzle capacitor, which contains an ion-doped well (such as an N-well) formed in a substrate as a first electrode of the anti-fuse capacitor. The first dielectric layer, such as an oxide layer, is formed on the ion-doped well, and the first gate electrode is located on the first dielectric layer and serves as the second electrode of the anti-fuse capacitor. The first gate comprises N-doped polycrystalline silicon or P-doped polycrystalline silicon. At least one selective transistor is adjacent to the anti-fuse capacitor. The selective transistor includes a second dielectric layer, such as an oxide layer, formed on the substrate. The thickness of the second dielectric layer relative to the thickness of the first dielectric layer

457687 V. Description of the invention (4) The thickness is relatively thick, the second gate electrode is located on the second dielectric layer, the drain electrode is adjacent to the ion doped well and the source electrode is located on the other side of the channel. The second gate contains N-doped polycrystalline silicon or P-doped polycrystalline silicon. Detailed description of the invention: What is disclosed in the present invention is an anti-fuse element cell structure. A thin gate oxide layer is used as the gate oxide layer of the anti-fuse capacitor, which can save extra high-potential power supply and charge injection circuit. . A thicker gate oxide layer is used as the gate oxide layer of the transistor to solve the problem of high potential. The invention further provides transistors with different series connection methods as the selection gate to improve the reliability of the junction and the gate oxide layer. The present invention will be described below. The anti-fuse element cell of the present invention includes an anti-fuse capacitor. The above-mentioned anti-fuse capacitor includes an ion-doped well formed in a substrate as a first electrode of the anti-fuse capacitor. A first dielectric layer is formed on the ion-doped well, and a first gate electrode is positioned on the first dielectric layer as a second electrode of the anti-fuse capacitor. At least one selective transistor is adjacent to the anti-fuse capacitor. The selective transistor includes a second dielectric layer formed on the substrate. The thickness of the second dielectric layer is greater than the thickness of the first dielectric layer. A second gate is located above the second dielectric layer, a drain is adjacent to the ion-doped well, and a source is located on the other side of the channel. Referring to FIG. 3 and FIG. 4, a semiconductor material is used as a substrate or a wafer 20. For example, a single crystal silicon can be used as the wafer 20 in the embodiment of the present invention.

4 5 7 6 8 *, V. Description of the invention (5) This structure includes an isolation area such as a shallow trench isolation area (shal 1〇w trench isolation; STI). 22 It is first manufactured in a wafer 20 using a known technique. . Generally, shallow trenches are formed in the wafer by lithography and etching, and then backfilled into the shallow trenches with an oxide layer deposited by chemical vapor deposition. In addition, other isolation technologies can also be used to make the isolation area. For example, the field oxidation area can be formed on the wafer 20 using LOCOS or other related field oxidation insulation area technology as the insulation between the components. The implantation technology forms an N well (N well; NW) in the wafer 20, and this N well 24 will be used as one of the electrodes of the anti-fuse capacitor 21. Deposit an oxide layer as the gate oxide layer of the anti-fuse capacitor 21 and the transistor 2 3 'It is worth noting' that the above-mentioned gate oxide layer of the anti-fuse capacitor 21 1 and the transistor 2 3 The gate oxide layers 28 have different thicknesses. To make the above-mentioned gate oxide layer, an oxide layer of a first thickness can be deposited first, and then a photoresist is used to cover one of the specific areas. Then a gate oxide layer of a second thickness is grown again and vice versa. Therefore, oxide layers of different thicknesses can be made according to the above-mentioned techniques. In addition, an oxide layer can also be formed after implanting ions of different ion concentrations in the wafer 20 '. This technology can also be used to form oxide layers of different thicknesses. For one embodiment, a general technique such as chemical vapor deposition method using TEOS as a reactant can form a silicon dioxide layer. The thickness of the gate oxide layer 26 of the thinner anti-fuse capacitor 21 is about 16-2 2 angstroms (in terms of a 0 13 micron process). It can therefore be collapsed with a lower potential. And gate oxide with thicker selection transistor 2 3

Five 'invention description (6) The chemical layer 2 8 provides higher gate reliability. The CVD silicon layer is deposited on the oxide layer by CVD, and the gate 32 of the selection transistor 2 3 and the gate 28 of the anti-fuse capacitor 21 are defined by the lithography process. With the structure of the present invention, N-type doped or P-type doped polycrystalline silicon can be used as the material of the gate electrode, so that the selection of the process is more flexible. In a preferred embodiment, the polycrystalline silicon of the present invention is doped polysilicon or in-situ doped polysilicon. The next step is to use the ion implantation technique to form the drain 34 and source 36 of the selective transistor, respectively. It is worth noting that the drain 34 of the present invention is not an N-well, but an ion-doped region adjacent to its side. Therefore, the present invention can reduce the wafer size without the need for a drift transistor. Figure 5 shows the circuit. FIG. 6 is another embodiment of the present invention. It is obvious that this embodiment includes a plurality of (at least two) selective transistors connected in series. In this example, the first selective transistor 23 and the first selective transistor are included. The two selective transistors 25, and the gate oxide layer of both are relatively thicker than the gate oxide layer 26 of the anti-fuse capacitor 21. That is, the gate dielectric layer 38 of the second selective transistor 25 is thicker than the anti-fuse capacitor dielectric layer 26. The transistor 25 includes the gate 40 and is located in the gate dielectric layer 38. on. With this structure, the problem of the reliability of the gate oxide layer potential can be improved, and the gate oxide layer of an individually selected transistor can be reduced. That is, the difference in the gate oxide layer in the first embodiment can be reduced. Connect here

Page 10 4 57 68 V. Description of the invention (7) The road is electricity. It is considered to be reasonable. The thickness of the selected combination is that the thickness of the oxide layer oxidized by the oxide layer is thinner than that of JXJ. Jen. The thickness of the oxide layer can be specified. High cases are subject to 0 selection of the string crystal of the receiver, and the selection and selection of the crystal is the same as the medium. Not intended to be used for profit, the interlayer is a thick layer of oxygen, and the thickness of the elective layer is thickened. The thicker oxygen is more capable of dissolving anti-oxygen and the capacity of the filament layer. &Amp; Yuli is a phase or layer of oxygen. Crystal placement is layer selection and selection of oxygen connected in a series of thin and thick one. For example, the amount of grading of Fan Zhi is the same as the number of fields, so that the circuit of the element can be reversed, such as the structure of the road, which is due to the inclusion of the wire and the capacity of the terminal. The wire-melt inversion electrical test is performed at the end of the capacitor. The description of electrical selection of electric thick selective layer is based on the fact that electricity is not the same as that of the electric wire. It is more practical to connect the thick string than the crystal thick electric layer. The electric test is taken at the terminal 1. The capacitor wire is fused, but the package is included. The body is connected to the string. The body day is the day aa. The electrical property is selected. The nature of electricity is ^ € Μ The second fuse is inverse, and the in situ wire fusion should be the bulk crystal of the thicker dielectric gate. Electrically-thick selective layer selection of the second dielectric and the first capacitor on the terminal 1 First its capacitance fr & ^ 8. Silk fusion anti-cell-containing element element Wire fusion reverse 1 recrystallized & & ^ a ' The selection of the electric capacity of the first and the second terminal is based on the electrical test parameters of the fuse, and the electrical properties of the crystal phase are thick. The first layer is connected to the dielectric string of the dielectric string. The second choice is selected in the second and the first, followed by W-457687 V. Description of the invention (8) The thickness of the dielectric layer of the anti-fuse capacitor. The electric test is involved in the connection of the terminal 1. The capacitor wire is fused and the case is not included. The electrical selection of the electrical selection layer is as small as one of the two gates. The reversal of the two fuses should be described above, and the strings should be connected. The description of the two crystals in the body position can be used to dissolve the wires, and the inverse should be thicker than the thicker dielectric layer. fra-1 ΠρΒΓ should be used to reverse the crystals. Phase electrical thickness is thick and thick. The anti-fuse stylization step of the present invention includes the use of a selective gate to select an anti-spinning element that does not collapse into a lower potential, and then uses a higher potential to be selected to collapse. The gate of the anti-fuse capacitor of its gate oxide layer. The anti-fuse oxide layer of the present invention is very thin, so it can be penetrated without high potential, so N- or P-type doped polycrystalline silicon can be used. Moreover, the present invention does not require the drifting NMOS of the prior art, can save space, and really proposes to solve the problem of high potential reliability. In addition, the present invention does not require a higher power supply or charge pumping circuit. More importantly, the invention is fully compatible with CMOS processes. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Field-specific.

Page 12 4 6 7 6 8 7 Brief description of the diagram: The preferred embodiment of the present invention will be explained in more detail in the following explanatory text t with the following figures: Figure 1 shows the prior art reaction Cross section of fuse element cell. Figure 2 shows a schematic circuit diagram of the prior art. FIG. 3 is a top view of the anti-fuse element cell of the present invention. FIG. 4 is a cross-sectional view of the cell of the anti-dissolving silk element of the present invention. Figure 5 shows a schematic circuit diagram of the present invention. FIG. 6 is a cross-sectional view of an anti-dissolving silk element cell according to another embodiment of the present invention. Figure 7 shows a schematic circuit diagram of the present invention. Figure 8 shows a schematic circuit diagram of the present invention. Component comparison table Wafer 2 N-type doped polycrystalline silicon 6 N well 10 NMOS 14 Wafer 2 0 Isolation area 2 2 N 丼 2 4 Antifuse capacitor oxide layer 2 6 Select transistor oxide layer 3 0 Selective electricity Crystal Drain 3 4 Anti-Fuse Capacitor 4 Oxide 8 Insulation Structure 1 2 Source 1 6 Anti-Fuse Capacitor 2 1 Select Transistor 2 3 Second Select Transistor 2 5 Anti-Fuse Capacitor Gate 2 8 Select Transistor Gate 3 2 Selective transistor source 3 6 Second selective transistor Gate dielectric 3 8

Page 13 457687_ Brief description of the drawings Second selective transistor gate 4 0 ΪΒΒΙ Page 14

Claims (1)

457687 6. Scope of patent application Patent scope: 1. An anti-fusible element cell including: an anti-fuse capacitor, the above-mentioned anti-fuse capacitor includes an ion-doped well formed in a substrate as an anti-fuse capacitor A first electrode, a first dielectric layer formed on the ion-doped well, and a first gate electrode positioned on the first dielectric layer as a second electrode of the anti-fuse capacitor; and at least one selective transistor Adjacent to the anti-fuse capacitor, the selective transistor includes a second dielectric layer formed on the substrate. The thickness of the second dielectric layer is thicker than the thickness of the first dielectric layer. The second gate Located on the second dielectric layer, the drain is adjacent to the ion-doped well and the source is on the other side of the channel. 2. The anti-fuse element cell according to item 1 of the patent application scope, wherein the first gate comprises N-type doped polycrystalline silicon. 3. For example, in the anti-fuse element cell of the scope of the patent application, the first gate mentioned above includes P-doped polycrystalline silicon. 4. The anti-fuse element cell according to item 1 of the patent application, wherein the second gate includes N-type doped polycrystalline silicon. 5. For example, in the anti-fuse element cell of the scope of patent application, wherein the second gate includes P-type doped polycrystalline silicon. P.15 3 5 7 6 8 ^ 6. Scope of patent application 6. For example, the anti-fuse element cell of the scope of patent application item 1, wherein the first dielectric layer mentioned above includes an oxide layer. 7. The anti-fuse element cell of item 1 of the application, wherein the second dielectric layer includes an oxide layer. 8. An anti-fuse element cell comprising: an anti-fuse capacitor, the above-mentioned anti-fuse capacitor includes an ion-doped well formed in a substrate as a first electrode of the anti-fuse capacitor, and a first dielectric A layer is formed on the ion doping well, and the first gate electrode is located on the first dielectric layer * as the second electrode of the anti-fuse capacitor; the first selective transistor is adjacent to the anti-fuse capacitor, and the first A selective transistor includes a second dielectric layer formed on the substrate. The thickness of the second dielectric layer is thicker than the thickness of the first dielectric layer. The second gate is located on the second dielectric layer. A drain is adjacent to the ion-doped well; and a second selective transistor is adjacent to the first selective transistor, and the first selective transistor includes a third dielectric layer formed on the substrate. The thickness of the three dielectric layers is thicker than that of the first dielectric layer, and the third gate electrode is located on the third dielectric layer. 9. The anti-fuse element cell according to item 8 of the patent application scope, wherein the first gate includes N-type doped polycrystalline silicon. 10. The anti-fuse element cell according to item 8 of the scope of patent application, wherein the above Page 16 6. Scope of Patent Application The first gate contains p-doped polycrystalline silicon. 1 1. The anti-fuse element cell according to item 8 of the application, wherein the second gate includes N-type doped polycrystalline silicon. 1 2. The anti-fuse element cell according to item 8 of the patent application, wherein the second gate includes P-doped polycrystalline silicon. 1 3. The anti-fuse element cell according to item 8 of the patent application, wherein the third gate includes N-type doped polycrystalline silicon. 1 4. The anti-fuse element cell according to item 8 of the patent application scope, wherein the third gate includes P-type doped polycrystalline silicon. 15 · The anti-fuse element cell according to item 8 of the patent application, wherein the first dielectric layer includes an oxide layer. 16. The anti-fuse element cell according to item 8 of the application, wherein the second dielectric layer includes an oxide layer. 1 7. The anti-fuse element cell according to item 8 of the application, wherein the third dielectric layer includes an oxide layer. 1 8. —A kind of anti-epileptic element cell, including: Page 17 45768 7 VI. The scope of the application for a patent is to form a layered well with an electrical hybrid medium. It is difficult, a pole containing a capacitor, a capacitor containing the electricity, and the fusion of the electric reverse wire is, As a layer of dielectric on the board of the China Electron, the first dielectric layer should be in place, the first electrode, the second electrode, the well containing miscellaneous electricity, and the doped filament. It should be used as the electrical layer. The dielectric electric second choice is the second one, the first one is at the first position, the upper gate capacity, and the second electrical upper part of the wire-melting plate, when the anti-base phase should be close to a thick adjacent shape, layer by layer. The first choice of electric crystal, dielectric and dielectric properties includes the option package and the integrality of the layer thickness on the adjacent electrode. The second choice and the first choice of this bulk crystal are: The first subdivision is close to the adjoining, the third interposition, the third interposition, and the upper third, and the plate base phase is thicker than the dielectric subdivision. Containing the top layer and the bulk crystal thick electric layer dielectric dielectric, the cell element wire in the above is fused and reversed. The fragmented item crystal 8 1 is a complex heterogeneous model. It contains 7 packets of the main month M pole application gate as a 9 1 2 0. Such as the anti-fuse element cell of the patent application item 18, wherein the first One gate contains P-doped polycrystalline silicon. 2 1. The anti-fuse element cell according to item 18 of the patent application scope, wherein the second gate includes N-type doped polycrystalline silicon. 2 2. The anti-fuse element cell according to item 18 of the patent application scope, wherein the above-mentioned second gate comprises P-type doped polycrystalline silicon. Page 18 457687 6 'Application for Patent Scope 2 3. If the anti-fuse element cell of Item 18 of the Patent Application Scope, the third gate mentioned above contains N-type doped polycrystalline silicon. 24. The anti-fuse element cell according to item 18 of the patent application scope, wherein the third gate includes P-type doped polycrystalline silicon. 25. The anti-fuse element cell according to item 18 of the application, wherein the first dielectric layer includes an oxide layer. 2 6. The anti-fuse element cell according to item 18 of the application, wherein the second dielectric layer includes an oxide layer. 27. The anti-fuse element cell according to item 18 of the application, wherein the third dielectric layer includes an oxide layer. 2 8. An antifuse element cell including an antifuse capacitor, the first end of which is connected to a reference potential, and the second end of the antifuse capacitor connected in series with at least one selective transistor, which is characterized by the above The thickness of the gate dielectric layer of the selective transistor is thicker than that of the antifuse capacitor. 2 9. An antifuse element cell including an antifuse capacitor, the first end of which is connected to a reference potential, and the second end of the antifuse capacitor connected in series with a first selective transistor, which is characterized in that Diselective transistor is connected to the first transistor Page 19 4 5 7 6 8 7 6. Scope of patent application The gate dielectric layer thickness of the first and second selective transistors is thicker than that of the anti-fuse capacitor. 3 0. An anti-fuse element cell including an anti-fuse capacitor, the first end of which is connected to a reference potential, the second end of the anti-fuse capacitor is connected in series with the first selective transistor, and is characterized in that Two selective transistors are connected in series to the first transistor. The thickness of the gate dielectric layer of the first and second selective transistors is equivalent to the thickness of the dielectric layer of the anti-fuse capacitor. 3 1. An antifuse element cell comprising an antifuse capacitor, the first end of which is connected to a reference potential, characterized in that the second end of the antifuse capacitor is connected in series with at least two selective transistors, where The thickness of the gate dielectric layer of one of the two selective transistors is equal to the thickness of the dielectric layer of the anti-fuse capacitor, and the thickness of the gate dielectric layer of the other two selective transistors is thicker than the thickness of the anti-fuse capacitor. The thickness of the dielectric layer of the fuse capacitor. Page 20