TW457597B - Method for forming flash memory of ETOX-cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current - Google Patents

Abstract

A method of forming an ETOX-cell in a semiconductor substrate is disclosed. The method begins with forming a p-well in the substrate. Then, a drain region and a source region is formed in the p-well. The drain region is of a first dopant type and the source region is of a second dopant type (i.e. same as the dopant type of the p-well). A floating-gate and tunnel oxide stack is formed above the p-well, the floating gate formed between the drain region and the source region and only after the drain region and the source region have been formed. The floating gate is doped with the same dopant type as the p-well. Finally, a control gate is formed above the floating-gate, the floating-gate and the control gate separated by a dielectric layer. The new ETOX cells can be organized into a NOR array, but with no need of source line connections. Each cell is programmed by band-to-band induced substrate hot-electron (BBISHE) at the source, and read by GIDL at the drain side.

Description

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 457597 A7 6124twf. Doc / 008 V. Description of the Invention (I) The present invention relates to an erasable Programmable Read flash memory that can erase programmable read-only memory tunneling oxide layer. Only Memory Tunnel Oxide Flash Memory; EPROM Tunnel Oxide Flash Memory; ETOX-flash Memory), and in particular, it relates to a method for manufacturing an ETOX memory cell having a P-type source and an η-type drain region. The ETOX memory cell with a gate stack structure is one of the most common flash memory cell structures on the market today. Generally, it uses Channel Hot Electron (CHE) when programming, and When erasing, the Fowler-Nordlieim (FN) tunneling effect is used to eliminate electrons through the source extremes or channel regions. The manufacturing method of the eta-channel ETOX memory cell is known as a twin-well process or a recently proposed triple-well process. The results are shown in FIG. 1. The three-doped well structure is basically used to prevent memory cells from being disturbed by noise generated outside the deep η-doped well. The method is to make the interface between the deep η-doped well and the ρ-doped well. To achieve reverse bias, for example, the highest bias voltage Vcc is applied to the n-type doped well, and the lowest bias voltage Vss is applied to the p-type doped well. In addition, the tT source is basically composed of arsenic ions (3xl (^ 1 2 / cm2 ~ l (^ 6 / cm2 high-dose η + junction)) and phosphorus ions (about 1014 lower-dose η junction The double implantation (Double Implantation) is formed, so that the source junction can be applied with a high bias (such as about 12V) during the erase operation. In addition, the n + drain is basically only implanted by arsenic ions Formation, which uses a high dose (approximately 1016 / cm2), and the drain terminal does not require lightly doped drain (LDD) ion implantation and spacer (Spacer) — — — — — — —r — — — · ——— ^ '— — — ill — — — — — — — — I 1 ^ 1 (Please read the notes on the back before filling out this page) 1 2 This paper is for the Chinese country " Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 457597 A7 6124twf, doc / 008 Step 5. Invention description (π) structure. Although the lightly doped drain structure can be used in CMOS switches reduce their electric field strength to prevent the generation of hot electrons, which is very important for CMOS, but lightly doped drain structure It is useless for ETOX memory cells. The thickness of the tunneling oxide layer (TOX) is 80-120A, and the polycrystalline silicon interlayer dielectric layer (TPP) is basically composed of thin silicon oxide / silicon nitride / silicon oxide. (ΟΝΟ) composite layer structure. For example, a typical ETOX memory cell based on a 0.35μm CMOS process has the following parameters: Tox is about 90A and TPP is about 16A (this is the oxide layer equivalent thickness (0xide Equivalent Thickness)) The ratio of the floating gate to the control gate is about 0.8. The ETOX memory cell shown in Figure 1 uses Channel-hot-electron (CHE) to Programmable. Its bias voltage is basically Vd = 7V, Veg = 9 ~ 12V and Vs = 0V. Under this bias condition, the channel surface near the drain will have a high channel current (about 1mA) that can generate hot electrons. / Memory cell). When the energy of the hot electron is sufficient to overcome the energy barrier of the oxide layer, the hot electron can be injected into the floating gate by controlling the positive bias on the gate. After this stylized operation, the floating gate The net number of electrons in the pole will increase, making the initial voltage of the memory cell (Threshold V oltage; VT) increase. The electrons in the floating gate can stay for a long time (for example, about ten years at room temperature) unless they are intentionally erased. What are the disadvantages of this stylized method using channel hot electrons? Low hot electron injection efficiency, and it consumes a lot of power when programming. Next, the Fowler-Nordheim (F-N) tunneling effect 'is used to erase the electrons from the source terminal or channel region when erasing the memory cells. Wipe 5 sheets of paper at the source. Applicable to Chinese paper standard (CNS) A4 (210 x 297 male cage) ---- I κ II ---- ^ .-------- order. 1 — ! 1-line--ii (Please read the notes on the back before filling this page) Printed by the Economic and Intellectual Property Bureau Employee Consumer Cooperatives 457597 6124twf.doc / 008 V. Description of Invention (A) The voltage is basically: vd is about ον or floating, v £ g is about -5V to 0V and 乂 5 is +9 to + 12V. In this way, a high electric field of about 10 MV / cm is formed in the tunneling oxide layer between the floating gate and the source overlap region. Therefore, the electrons in the floating gate will be tunneled into the source region and eliminated. Those skilled in the art know that at this time, the source extreme will have a large gate induced drain leakage (GIDL), which will degrade the quality of the tunneling oxide layer. In addition, when F-N erasure is performed through the channel region, each bias voltage is basically: Vd floats, Veg is about -15V and Vpw is about 0V. In this way, a high electric field of about lOMV / cm will be formed in the tunneling oxide layer between the floating gate and the P-type doped well channel region (the Accumulation state at this time). Therefore, the electrons in the floating gate will tunnel into the channel region and be eliminated by the bias of the P-type doped well. Those skilled in the art should know that, because a very high negative voltage must be applied to the control gate in this example, the tunnel oxide layer is easily degraded by the high electric field during erasure. Then, the conventional ETOX memory cell reads at a bias voltage of basically everywhere: Vd is about IV to 2V, and Veg is about equal to Ve. , Vs is about 0V, Vpw is about 0V, Vdnw = Ve. And Vsub is about 0V. At this time, whether the channel area is reversed depends on the net number of electrons stored in the floating gate. In this way, the current of the Uad can be used to judge the switch of the memory cell, and the data stored in the memory cell can be learned. 0 or 1. The conventional ETOX memory cell shown in FIG. 1 can be programmed using another method, namely, a substrate-hot-electron (SHE) method, as shown in FIG. 2. It can be seen from Figure 2 that at this time, an extra 6 paper sizes must be applied to the China National Solid Standard (CNS) A4 specification (2KM297 mm) IIIIII ΙΓ II I- —1— ^ — — — — — — — — 6J11111111 — I (Please read the notes on the back before filling this page) A7 B7 4575 9 7 6124twf.doc / 008

5. Description of the invention (LfO n + junction (ie, “Injection” junction) so that electrons are injected into the floating gate by the forward bias of the n + injection junction and the P-type doped well junction. However, In this example, most of the electrons will not diffuse toward the channel region, but will diffuse toward the nearby n + source junction. Furthermore, the n + source, p-type doped well, and y injection junction form a plane ηρη Bipolar Transistor, which will cause a very large Bipolar Current at the node of the n + injection junction. Therefore, the ETOX memory cell programmed with the substrate hot electron is not only very slow, but also It must have an extra n + injection junction, so it needs a very large area. Therefore, this method of programming using substrate hot electrons is not often used in commercial EPROM or ETOX flash memory. Another recently proposed The substrate hot electron programming method was introduced by IC Chen, Kaya and Paterson in "Band-to-band Tunneling Induced Substrate Hot-deCtrom (BBTSHE)" injection method: a non-volatile New stylization of memory Method "Fec / ί. // 7 ". Electron Devices Meetings, p. 263, 1989. Thermionic electrons are generated by Impact Ionization of high-energy electrons. The band-tunneling mechanism of the surface of the doped island region is generated, and this P-doped island region is located in the center of the channel region of the EPROM memory cell. This method has a very high injection efficiency (compared with the known substrate hot electron mechanism) (Comparatively), because its hot electron system is generated near the channel region. However, the memory cell has a larger area because this memory cell requires an extra heavily doped P-type island region. Therefore, the industry urgently needs a kind of Modifications to solve the above problems of conventional techniques 7 This paper size is applicable to China National Standard (CNS) A4 (210x297 mm) ------- 1 ---.-- Jtt, ------ -Order --------- Line-L, (Please read the precautions for face-to-face first and then fill out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 57597 Λ7 6124twf, doc / 008 B7 V. Description of the invention (t) Manufacturing method of good ETOX memory cell. A method for forming an ETOX memory cell on a semiconductor substrate is proposed. The steps are as follows. First, a p-type doped well is formed in the substrate, and then a drain region having a first doped type is formed in the p-type doped well. Next, a source region with a second doping pattern (same as the P-type doping well) is formed in the p-type doping well, and a floating gate is formed on the P-type doping well. The thin oxide layer is separated, and it is formed between the source region and the drain region only after the source region and the drain region are formed. Finally, a control gate is formed on the floating gate, which is separated by a dielectric layer. The new ETOX memory cells can be arranged in an "inverted OR array", but do not require source line connections. Each memory cell uses the source extreme band tunneling to trigger substrate hot electrons when programming, and the drain gate (GIDL) is induced by the drain gate when reading. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Drawing in FIG. 1 Shown is a schematic diagram of ETOX memory cells obtained by the conventional three-doped well process. Figure 2 shows a schematic diagram of an ETOX memory cell using a conventional injection interface. Figure 3 shows a schematic diagram of the ETOX memory cell obtained according to the present invention. Figure 4 shows the ETOX memory cell program shown in Figure 3. The paper size is suitable for China Gujia Zhun (CNS) A4 specification (210x 297 mm) -__ ϋ ^ —- ϋ I n ϋ i tt n I ^ i (Please read the precautions on the back before filling this page) ^ 57597 6124twf.d〇c / ° oa A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Schematic. Fig. 5 is a schematic diagram of the ETOX memory cell shown in Fig. 3 during a read operation. Figure 6 is a schematic diagram of the ETOX memory cell shown in Figure 3 during the erasing operation. FIG. 7 shows an inverted OR array formed by the ETOX memory cells of the present invention. FIG. 8 shows a reverse OR array formed by the ETOX memory cells of the present invention, which is formed on a wafer with silicon (SOI) on an insulating layer. Figure 1¾ shows the layout of the ETOX memory cell shown in Figure 3. \ ^. It has the n + drain, metal line, and buried p + of the upper bit line contact window; source line. U / '9th oxygen is shown as the layout of the ETOX memory cell shown in Figure 3, which has a buried n + drain and a buried p + source line without a contact window. Fig. 10 shows a manufacturing flow chart of the ETOX cell of the present invention shown in Fig. 3. Figures Π-13 are sectional views of the manufacturing process of the ETOX memory cell of the present invention shown in Figure 3. Description of the symbols in the figure: 301: ETOX memory cell 303: p + doped region, p + source 305: n + drain 401, 403: electron 801: buried p + layer (p + Buried Layer) 9 (Please read the back first Please note this page before filling in this page) " b Ding 4. '·-This paper size is applicable to China National Standard (CNS) A'l specification (2] 〇X 297 gong) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 457597 A7 6124twf »doc / 0 08 37 V. Description of the invention (1) 901: Embedded p + wire (p + Buried Line) 903: Polysilicon floating gate (Polysilicon Floating Gate) 1101: P-type doped well (P-well) Π〇3: substrate 1105: η + drain 1107: ρ + source 1201: tunnel oxide 1203: first polycrystalline silicon layer 1301: silicon oxide / silicon nitride / oxide Silicon (NO) composite layer 1303: A description of a preferred embodiment of a control gate Please refer to FIG. 3, which shows an ETOX memory cell 301 obtained according to the present invention. It can be seen from Fig. 3 that the structure of the ETOX memory cell 301 is substantially the same as that of the η-channel ETOX memory cell shown in Fig. 1, except that the η + source is changed to the pi-parallel region 303 (called ρ + source) . In addition, other characteristics are also the same as those of ETOX memory cells in the conventional art. For example, the thickness of the tunneling oxide layer is about 80 ~ 100A, and the polycrystalline silicon interlayer dielectric layer (Interpoly dielectric) between the control gate and the floating gate is preferably thick ( Silicon oxide layer (equivalent thickness) is about 100 ~ 180A silicon oxide / silicon nitride / silicon oxide composite layer, and the coupling ratio between the control gate and the floating cathode is about 0.8. As seen by those skilled in the art, this ETOX memory cell 301 is not actually a metal-oxide-semiconductor field-effect transistor (MOSFET), because its p + source 303 and n + drain 305 have different doping patterns. This p + source The electrode 303 is only a P + contact window between the p-type substrate and the P-type doped well. In addition, P + source electrode 303 and n + 10 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) nnnn aL · II ϋ ii · n la I n II I line —— (, (Please read the back first Please note this page and fill in this page again) A7 B7 457597 6124twf. Doc / 008 V. Description of the invention (¾) The channel between the drains 305 can be reversed (by applying a sufficiently high voltage Veg) The sister is electrically connected to the n + drain However, there is no channel current flowing from the n + drain 305 to the p + source 303. The operation of the ETOX memory cell 301 is described below. The ETOX memory cell 301 tunnels the substrate heat with the energy band at the 303 end of the p + source. The electrons are programmed. Please refer to Figure 4. The bias on the n + drain 305 is 3 to 5 V 'P + the source 303 (p-type substrate) is 0V and the gate control bias V < ^ High enough (8 to 12V) to invert the channel between p + source 303 and n + drain 305. This inverted channel is n-type and is electrically connected to n + drain 305 ', so it is also biased Vd. Due to the high enough bias voltage (V, g) 'on the control gate, the electrons are generated in the table where the p + source 303 overlaps with the floating gate due to the band tunneling (BBT) mechanism. In this case, the electrons generated by the BBT mechanism at the surface of the P + source electrode 303 have two flow directions. One is to flow directly toward the channel that has been inverted. This inverted channel is electrically connected to the n + drain 305. And it has a bias voltage Vd. These electrons will be accelerated or "heated" by the electric field in the empty region between the P + source 303 and the inversion channel, and the energy of these electrons can be injected into the floating gate. The stylization method is similar to the known "source extreme injection method". In addition, these electrons are designated by 401. The second is to flow directly toward the P-type doped well, and is close to the drain junction and adjacent to the inversion layer. The electric field in the empty region is accelerated or "heated". When these electrons have enough energy, they can pass through the inversion layer and be injected into the floating gate. This stylized method is known as the "basic hot electron injection method" Similar, and the number of these electronics is 403. This paper size is applicable to China National Standard (CNS) A4 specification (210x 297 mm) ---- I I--1 ^ -------- Order .-- -------- i. (Please read the notes on the back first * Fill this guest) Intellectual property of the Ministry of Economic Affairs Printed by the Bureau Cooperative Consumer Cooperative, printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 457.597 6124twf.doc / 008 β7 V. Description of the Invention (q) Alternatively, the energy band tunneling of the ETOX memory cell of the present invention causes substrate heat The electronic programming method is a combination of the "source extreme injection method" and the "substrate hot electron injection method". This stylization process will continue (ie, bring more negative charge into the floating gate) until the channel inversion layer disappears. Please refer to FIG. 5, which is used to explain the reading operation method of the ETOX memory cell 301. This read operation method utilizes the principle that the drain leakage current induced by the gate of the η + drain 305 is highly (exponentially) related to the electric field between the n + drain 305 and the floating gate. Therefore, the amount of net charge in the floating gate has a significant effect on the change in gate-induced drain leakage. The preferred bias here is as follows: Ves is about -3 to 0V, Vd is about 3 to 5V, and Vs is 0V. As compared to an unprogrammed memory cell (that is, there is no charge in its floating gate), the drain and floating gate of a programmed memory cell (that is, it has a charge in its floating gate) The electric field between them is large, so it can cause the drain leakage current caused by the difference of about three orders of magnitude between the two gates, which is measured at the n + drain. Therefore, the magnitude of this drain current is closely related to the charge of the floating gate, and becomes the criterion for reading the data stored in the ETOX memory cell as 0 or 1. This reading method based on the gate-induced drain leakage is novel to the present invention. Then, the analysis of the gate-induced drain leakage current during reading shows that the voltage Vfg of the floating gate can be estimated by The Law of Charge Conservation, that is,

Cpp (Vfg-Vcs) + (Cs + Cd) (Vfg-Vd) + Cch (Vf 「Vd) = Qf or Vrg = Qf / Ct + VcgYs + Vd (yd + Ys + Ych) where Ct = Cpp + Cs + Cd + Ceh, and the definition of coupling ratio is as follows: Yg = Cpp / Ct; Yd = Cd / Ct; Ys = Cs / CtlYch = Cch / Ct 'and ya 8+ yd + ys + Ych =: l. In addition,- — — Ill · — — — — — — — ^ III 1 1 1 I ^ — — — — — — — f 1 (Please read the notes on the back before filling out this page) This paper size applies to the Chinese National Standard (CNS ) A4 size (2.10 ^ 297 mm) A7 B7 457597 6124twf.doc / 008

5. Description of the invention ({cO

Qf is the net charge in the floating gate. When this memory cell is not stylized (ie 0), there is no net charge in the floating gate, that is Of = 0. In this way, the voltage Vfs of the floating gate when reading in the "0" state is

Vfg) 〇 = vccyd (memory cell in “〇” state) When this memory cell is programmed (that is, 1), an analytical solution of the maximum net charge in the floating gate at the completion of programming can be obtained:

Qf / CeVk-V ^ A + Vd ^^ + T]) where Vt. Is the starting voltage seen by the floating gate, η is the Coefficient of Body-bias Effect, and its 値 is basically about 0.5 ', when V " d < pg > is programmed The bias. Please see Ji Minghua et al. "A new method using substrate hot electron injection mechanism for three-doped well ET0X memory cells proposed by the 1999 International Symposium on Ultra-large Integrated Circuit Technology, Systems and Applications, Paper No. G22, page 199 Self-adjusting stylization and erasing methods. " The read bias is Veg = 0V and vd = v. . . In this way, when the data 値 is 1 from the above equation, the vfs during reading is vfg, (γ6 + η) + ν ^ (when the memory cell is "1"). In addition, the overlapping area between the drain and the floating gate The surface electric field at the tunneling point is

Ed, t, s = (Vd-Vfg-1.12) / (31 ^) (for n-type doped polycrystalline silicon) or KV < j-Vfg) / (3Tc-) (for P-type doped polycrystalline silicon) Where Tm is the thickness of the tunneling oxide layer, and the constant 12 represents the band gap of the sand material. Gate-induced drain leakage current (that is, u is exponentially related to the magnitude of the electric field Ed: fg, and E < *. Fg is related to the potential of the floating gate: This paper size applies to China National Standard (CNS) A4 specifications ( 210 x 297 male cage) ---- I -------- " -------- 丨 Order ----------- ^, (Please read the precautions on the back first (Fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 0/597 6l24twf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description ((丨) Iread = AEd, fgexp (- B / Ed> fg) where A and B are constants, and published literature shows that B is about 21.3MV / cin. Please note that P-type doped polycrystalline silicon will cause a larger Ed.fg 'It will be more than M2 / ( If a typical bias voltage is used, the difference in Vfg when the data is 0 and 1 will be greater than 3V. This will cause the gate-induced leakage current at the η + drain to differ by at least three orders of magnitude. Please refer to Figure 6, which depicts the erasing action of ETOX memory cells, which is similar to the Fowler-Nordhdm tunneling effect known through the channel. At this time, there is a sufficiently large electric field (> 10MV / cm ) Is generated between the n + drain region 305 and the floating gate, so that the electrons in the floating gate can be excluded by the Fowler-Nordheim tunneling effect into the channel / drain / source region. The preferred situation here is The n + drain 305 and p + source 303 are both grounded to 0V, and the control gate voltage V "is -9 to -12V. Another option is to apply a 5V voltage to the n + drain 305 and tunnel through Fowler-Nordheim Effect to erase. Because this method will cause a large gate-induced drain leakage current to occur at the drain, this type of erase method is not a good choice for ETOX memory cell 301. Note that The new ETOX memory cell 301 is particularly suitable for making wafers with "silicon on the insulation layer". At this time, because the P + source 303 is only the main contact window of the component, the floating body effect can be It is completely eliminated. In addition, all the operation methods of this kind of element are the same as those made on the entire wafer. The advantages of the ETOX memory cell 301 of the present invention are described below. First, because the P + source 303 is actually p-type Contact window between substrate and p-type doped well, 14 ------ ------- ά-- (Please read the notes on the back before filling in this page)

I

^ D Γ This paper size applies Chinese National Standard (CNS) A4 (210 x 297 mm) A7 B7 457597 6124twf.doc / 008 V. Description of the invention ((v) Therefore, as long as the P-type substrate and the p-type doped well are grounded That is, no source interconnection is needed ', so smaller memory cells can be manufactured. Second, in all operations, the n + drain 305 does not generate a large current, so the buried n + wire (that is, used as the n + drain) The diffusion zone of the pole) is suitable for the operation of this memory cell, which eliminates the need to make the contact window of the drain electrode and the metal connection, and can further reduce the size of the memory cell. Third, this can be worn through the channel area. The method of programming the tunnel-induced substrate hot electrons and the Fowler-Nordheim erase method are both low current and low power consumption operations. Finally, the read operation of the gate-induced drain leakage current has a low correlation with temperature. Due to the reading mechanism of the drain leakage current caused by the gate. After explaining the structure and operation mode of the ETOX memory cell 301 in detail above, the method of effectively manufacturing the ETOX memory cell 301 will be described next. ETOX memory cell 301 manufacturing There are several key points, which are related to tradition The CMOS logic circuit process is different. First, the n + drain 305 and p + source 303 in the ETOX memory cell 301 must have the largest gate-induced drain leakage current, which is exactly the opposite of traditional CMOS transistors. Therefore, the n + of the present invention The drain electrode 305 and the p + source electrode 303 should be fabricated before the floating gate is formed (for example, using a mask and a high-dose ion implantation step). Second, the ETOX memory cell 301 does not need lightly doped drain ion implantation and gaps. However, in order to be more compatible with the CMOS process, a gap wall can also be formed on the side wall of the floating gate, and as long as the n + drain 305 and p + source 303 are formed before the floating gate, it will not cause negative effects. In this way, the spacer wall of ETOX memory cell 301 does not have to be removed (otherwise, another masking step and wet etching step are needed). --- 1 I ---_---- · --- ^- ----- Order --------- Line--I. (Please read the precautions on the back before filling out this page) Printed on paper standards for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, this paper applies Chinese national standards (CNS) A4 Specification (2 丨 0x297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 457597 A7 6124twf.d〇c / QQg ------- B7 V. Description of the invention (D) Thirdly, compared with n-type doped polycrystalline silicon floating gate, the polycrystalline silicon floating gate of ET0X memory cell 301 is preferably p-type doped ( For example, doped with boron (B0), to increase the drain leakage current caused by the gate of η + drain 305 during reading (due to the increased electric field due to the band gap of about 1.12V). Therefore, its negative effect is that the drain leakage current induced by the gate of ρ + source 303 will be reduced due to the difference in band gap between it and the n-type doped polycrystalline silicon floating gate. However, since only a small ρ + source 303 gate is required to cause drain leakage current during programming, the effect is irrelevant. In addition, the ΕΤΟχ memory cells 301 can be arranged in an inverse or array as shown in Figure 7 and its characteristics are described as follows: η + drain is connected to a row of bit lines through a buried η + region (no contact window) Array), or connected by a traditional contact window and metal lines; the control gate of the memory cell is connected to the word line. In addition, there is no need for the P + source connection here because the bias of the ρ + source is provided by a P-type doped well or a P-type substrate (that is, it is always grounded). The memory operation of this array is described below. When programming (taking a single memory cell as an example), select a row (vd) to apply a high bias (for example, 3.3V), and select the zigzag line Veg to apply a high bias (for example, 8 to 12V). Not selected The bit line and word line biases are zero. When you want to program a whole row of memory cells, all the row bit lines are biased according to the input digital information (for example, data V1 is 3V, 0 is 0V), and the selected character line is high biased. Voltage (for example, 8-12V), and the bias of the unselected word lines is zero. When you want to program a whole row of memory cells, all character lines are biased according to the input digital information (for example, 8 to 12V for data 値 1 and 0V for 〇). With a bias voltage of 3.3V, all the paper sizes that are not selected are applicable to the Chinese National Standard (CNS) A'l specifications (2) × X 297 mm) ------ l · I — L --- ^! | Order --------- line-1 (please read the precautions on the back before filling this page) A7 B7 457597 6124twf.doc / 008 V. Description of the bit line of the invention (1 mountain) All are 0. In short, the programming of unit cells, entire rows, and entire columns in this array can be done efficiently. While the read operation is in progress, the selected row of character lines is applied with a low bias (for example, 0 to -3V), and the selected row of bit lines is applied with a high bias (for example, 2 to 3v). Line Veg is applied with a high bias of 3., 3V, and all unselected bit lines are low biased (ie, 0V). Next, the gate-induced drain leakage current on a row bit line is used as a basis for judging the data stored in the floating gate. Among them, GIDL with a charge existing in the floating gate is more likely to have no charge in the floating gate. The extreme GIDL is three orders of magnitude larger. This read operation is unique, and it is significantly different from the conventional flash memory read method. ^ In the erase operation, only a low bias is applied to the selected character line (for example, -6 to- 12V), so that the memory cell is erased by the Fowler-Nordheim tunneling effect through the channel area, and the unselected character line 乂 is erased. 8 is biased at 0V, and all row bit lines are biased at 0. Of course, it is also possible to efficiently erase memory cells in more than one column at a time, or even all columns. This new ETOX memory cell 301 is also suitable for wafers with silicon (SOI) on the insulation layer. The p + source 303 in the array must be grounded and connected together by a buried P + layer 801 or a contact window and metal wires. As shown in Figure 8, its memory operation is the same as described in the description of Figure 7. What is important to note here is that, compared with the known ETOX memory cell, this ETOX memory cell does not have a "floating subject effect" or "parasitic bipolar effect" in its array. Figure 9a shows a layout of ETOX memory cell 30] ------------- ^ --------Order --------- line--ί 1 (Please read the notes on the back before filling out this page) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to the national standard (CNS) A4 (210x 297 public copy) Δ7 B7 4575 97 6124twf. Doc / 008 5. The top view of the invention description ($), which has a buried n + drain 305, a metal wire and a buried p + lead 901 connected to a one-bit line contact window. Please note that the polycrystalline silicon floating gate 903 is designed as a simple island, rather than a strip, so that the Self-aligned Etch (SAE) process can be eliminated. In addition, the positioning error between the "buried layer, buried P + wire 901" and the floating gate 903 and the word line 905 does not seriously affect the operation of the memory cell. Figure 9b shows another layout of the ETOX memory cell 301. It has a buried n + drain and a buried p + source, and no contact window or metal line is connected to it. It should be noted here that there must be enough space between the n + and p + regions so that the two have a sufficiently high Breakdown Voltage. In addition, for the ET0X memory cell 301 fabricated on a wafer with "sand on the insulation layer", the layouts shown in Figures 9a and 9b are suitable, where the P + source lines are connected at the edge of the array Together and grounded. In terms of manufacturing method, by adding two additional masking steps to form a buried n + layer and a p + layer, the new ET0X memory cell 301 can be manufactured using a conventional ET0X flash memory manufacturing process. At the same time, the floating gate was changed to P type by boron ion implantation. Figure 10 shows a typical manufacturing flow chart of ETOX memory cell 301, which is compatible with advanced CMOS logic circuits (0.25μm and below), and has a shallow trench isolation type, front-end isolation process and self-aligned metal. Silicide (Salicide) transistor. According to the present invention, Figures 11-13 illustrate the preferred method for forming ETOX memory cells 301. As shown in FIG. 11, a P-type doped well 1101 is first formed in a substrate 1103 (in this example, P-type doped). This p-type doped well 1101 ---- II I ----,- -Help ------- Order · -------- Line-^ (Please read the note on #face before filling out this page) Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Μ A7 B7 4575 9 7 6124twf. Doc / 003 5. The invention description (A) can be formed by traditional ion implantation method. Next, by using a mask and an ion implantation method, an n + drain 1105 and a P + source 1107 are formed in the P-type doped well 1101. Importantly, the n + drain 1105 and p + source 1107 are formed before the floating gate. In this method and the conventional technique, the method of using the floating gate electrode to form a self-aligned source and drain region is different. Next, referring to FIG. 12, a method of forming a tunneling oxide layer 120 on a p-type doped well is preferably a thermal oxidation method. Next, a first polycrystalline silicon layer (polyl) 1203 is formed on the tunneling oxide layer 1201, and its doping type is p-type, such as boron doping, and its doping method is deposition and simultaneous doping or ion implantation. . Then, the first polycrystalline silicon layer 1203 and the tunneling oxide layer 1201 are patterned to form a floating gate between the n + drain 1105 and the p + source 1107. Note that there is sufficient overlap between this floating gate and the n + drain and p + sources, as shown in Figure 12. Referring to FIG. 13, the next step is to form a silicon oxide / silicon nitride / silicon oxide composite layer 1301 on the floating gate, and then form a control gate 1303 on the silicon oxide / silicon nitride / silicon oxide composite layer 1301. In addition, the CMOS logic circuit transistor gate is formed simultaneously with the control gate, and the remaining manufacturing steps are the same as the common logic process shown in Figure 10. It must be particularly mentioned here that the £ TOX memory cell with the corresponding structure of n + source and 〆-drain obtained from the opposite type of doping is difficult to operate when an operating bias of opposite polarity is applied successful. This is because the thermo-hole injection method must be used for programming in this case, and since the energy barrier for hot-hole injection is higher than the energy barrier for hot-electron injection, the programming is difficult. Furthermore, the 'hot hole implantation' will also seriously degrade the quality of the tunneling oxide layer. This paper size applies to China National Standard (CNS) A4 specification (210x 297 mm) ---------! .-! 咚 ------- order --------- line 丨Γ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 457597 Λ7 6124twf, doc / 008 Printed 5. Description of the Invention (丨) Although the present invention has been described in a preferred embodiment The disclosure is as above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be regarded as the attached application. The patent scope shall prevail. -----------, — 0 ------- Order --------- line— ^ (Please read the notes on the back before filling this page) Wisdom of the Ministry of Economy The paper size printed by the Employees' Cooperative of the Property Bureau applies the Chinese National Standard (CNS) A4 specification (2〗 0 X 297 mm)

Claims (1)

457597 6124twf.doc / 008 A8 RS C8 D8 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for Patent Scope I — A method for forming ETOX memory cells on a substrate, including: forming a P-type doped well in In the substrate; forming a drain region in the P-type doped well, the drain region having a first doping type; forming a source region in the P-type doped well, the source region having a first Two doped type; a floating gate is formed on the P-type doped well, the floating gate is separated from the substrate by a thin oxide layer, and the floating gate is formed in the source region and Between the drain region, and the floating gate is formed after the source region and the drain region; and a control gate is formed on the: prepared gate, the control gate and the floating gate A dielectric layer is used between the electrodes. 2. As described in item 1 of the scope of patent application: ^^^ A method for forming an ETOX memory cell on a substrate, wherein the second doped type g-type. 3. The method for forming an ETOX memory cell on a semi-substrate as described in item 1 of the scope of the patent application, wherein the doping type of the floating gate is P-type. 4. An inverse or array structure capable of unit cell, single-row and single-stroke formatting and whole-row erasure, including a plurality of ETOX memory cells formed in a P-type doped well, and each of these ETOX memory cells includes : A control gate; a floating gate that is electrically insulated from the control gate; and the floating gate is located substantially below the control gate; an n-type drain, the n-type drain The pole system is located in the p-type doped well 'and -------: ------ C .------- order --------- line-((Please Please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (2) 0 X 297 public copy) 457597 as B8 C8 6124twf * doc / 008 D8 The gates are adjacent to each other; a P-type source is located in the P-type doped well and is adjacent to the floating gate: wherein the ETOX memory cells are arranged in a two-dimensional array, and Arrange in plural and plural rows; the floating gates of each of the ETOX cells in the same column are connected to a column of word lines; each of the ETOX records in the same row The n-type drain of the memory cell is connected to a row of bit lines; and the p-type source of each of the ETOX memory cells is connected to the p-type doped well. It is described that the unit cell, single-row and single-stroke conversion and the whole row erase inverse or array structure can be performed, in which the P-type source of the ETOX memory cells and the p-type doped well are grounded. --- I-- --R --- II ------ | Order_ — — ------- line --- Λ (Please read the precautions on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Du Print This paper size applies to China National Standard (CNS) A4 (210x 297 mm)