JPH11191616A - Improved well structure for nonvolatile semiconductor memory and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To completely solve the problem that a tunnel oxide layer deteriorates through a BTBT current perfectly by an arrangement, wherein the data of a cell transistor is programmed by channel thermal electron injection method and erased by an F-N tunneling system through the bulk region of the cell transistor. SOLUTION: In order to program the data of a cell transistor through channel thermal electron-implantation system and to erase by an F-N tunneling system through the channel or bulk region, cell transistors M1, M2 forming an NOR- type cell array structure are located in the cell region. At the time of programming the cell transistor, the word line and the bit line are applied voltages of about 10 V and 6 V, respectively. Consequently, thermal electrons generated together with a current upon turning the cell transistor on are injected into a floating gate, and the cell transistor has a threshold voltage of about 7 V upon finishing programming.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a NOR type flash EEPROM.
(NOR-type flash electrically erasable programmabl
The present invention relates to an improved well structure in a cell region and a peripheral region of a read only memory (e read only memory) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, nonvolatile semiconductor memory devices include a mask ROM, an EPROM (electrically progr
ammable ROM), EEPROM and flash EEPROM
ROM and the like. Among them, flash EEPROM
Has not only the operating characteristics of EEPROM but also the function of electrically erasing data at once and low power consumption characteristics.
Recently, it has been spotlighted not only as a permanent memory in personal notebook computers, but also as a recording medium for portable terminals such as digital cameras and memory cards.

The state of data stored in a nonvolatile semiconductor memory device is determined by the threshold voltage of a cell transistor. The threshold voltage refers to a critical voltage that is turned on when a voltage difference between a gate terminal and a source terminal of a cell transistor is gradually increased.

[0004] Each cell transistor in an EPROM, EEPROM or flash EEPROM has a floating gate isolated from a control gate. By changing the amount of charge stored in the floating gate, the threshold voltage of each cell transistor is changed to a desired level. As a result, the data is programmed to be distinguishable during the read operation.

In order to read the state of data stored in each cell transistor, it is necessary to check the storage state of the programmed cell. For this purpose, a desired memory cell is selected by using a decoder circuit, and a signal of a voltage form necessary for reading is applied to the memory cell and a circuit associated therewith. As a result, a current or voltage signal is applied to the bit line according to the storage state of the memory cell. When such a current or voltage signal is measured by a sense amplifier, the information stored in the memory cell indicates data "1" or data "0".

[0006] The structure of a memory cell array of a flash EEPROM is roughly classified into a NOR type and a NAND type according to a connection form of a memory cell to a bit line. In the case of the NOR type, as shown in FIG.
M3 and M5 are connected between the bit line BL1 and the common source line (CSL). However, in the case of the NAND type, as shown in FIG.
2 to M4 form a string structure together with the selection transistors ST1 and ST2, and are connected in series between the bit line BL and the ground line.

Each of the memory cell transistors shown in FIGS. 1 and 2 has a control gate CG connected to a word line and a floating gate FG separated from the control gate CG. The NOR type cell array structure shown in FIG. 1 is disadvantageous in terms of the degree of integration of cell transistors as compared with the NAND type cell array structure shown in FIG. Have. Therefore, due to such high-speed operation, the structure of the memory cell array of the flash EEPROM tends to change from NAND type to NOR type.
Various technologies for achieving high integration of cell transistors have been disclosed.

[0008] As one of such techniques, a NOR type flash EEPROM is described in the title of "A SIGNAL TRANSISTO".
R EEPROM CELL AND ITS IMPLEMENTATION IN A 512K CMO
S EEPROM ", Satyen Mukherjee et al., IEDM, pp, 616-
619. US Patent No. 4,698,7
In the technique disclosed in Japanese Patent No. 87, the data programming into the memory cell is performed by a channel thermionic (CHE) injection method, and the erase of the programmed data is performed in one side direction as shown in FIG. 3A. Through a source region which is a junction region of Fowler-Nordheim (FN) tunneling.

Referring to FIG. 3A corresponding to a cross section of an arbitrary cell transistor in FIG. 1, an operation of erasing data in a source region (or a drain region) which is a junction region in one direction is shown. Data erasing is changing the threshold voltage value of a programmed cell transistor to an initial threshold voltage value, which is achieved by discharging electric charges. Therefore, when about 0 V (volt) is applied to the control gate CG of the cell transistor connected to the selected word line and about 12 V is applied to the source region 12, the floating gate F
The electrons stored in G are emitted to the source region 12 through the lower gate oxide film by FN tunneling.

Hereinafter, each operation mode of the NOR type cell transistor will be described in detail in order to distinguish the source erase operation from the present invention. In FIG. 3A, when the cell transistor holds an electron in its own floating gate FG, the state is set to a data "1" state, and otherwise, the cell transistor is set to a data "0" state. The operation of changing the cell transistor in the data “0” state to the data “1” state
In this field, it is called program operation. For such a program operation, a threshold voltage should be increased to about 7 V by applying a necessary voltage signal to a cell transistor having a threshold voltage of about 2 V. In such a program operation, about 5 to 6 V is applied to the drain D connected to the selected bit line, and about 10 to 12 V is applied to the control gate CG connected to the selected word line. Alternatively, 0 V is applied to the bulk 10.

As a result, the cell transistor is turned on, and the cell current flows from the drain region 13 to the source region 1.
Flow to 2. At this time, some of the generated thermoelectrons are injected into the floating gate FG through a gate oxide film (tunnel oxide film) by the vertical electric field of the control gate CG. The threshold voltage of the cell transistor rises from the initial 2V to 7V due to the injection of the channel thermal electrons. Even when the program operation is completed, the thermal electrons injected into the floating gate FG are trapped by the surrounding gate oxide film and the triple film having the ONO structure, so that the programmed cell transistor is separately erased. Until the operation, data is retained permanently.

On the other hand, the above-described erasing operation is an operation in which the electrons stored in the floating gate FG are emitted to set the threshold voltage of the cell transistor to an initial threshold voltage (about 2 V in this case). In this case, the bit line connected to the drain D of the selected cell transistor is floated, and about 12 to 15 V is applied to the common source line CSL connected to the source S, and 0 V is applied to the word line. Accordingly, an electron tunneling phenomenon, that is, FN tunneling, occurs through a tunnel oxide film of about 100 ° due to a voltage difference between the floating gate FG and the source junction region 12.

In this manner, electrons trapped in the floating gate FG are emitted to the source region 12 through the oxide film. Since almost no electrons are present inside the floating gate FG due to this erasing operation, the threshold voltage of the cell transistor is lowered, and the original threshold voltage value of 2 is obtained.
Maintain V.

On the other hand, during a read operation, a voltage of about 1 V is applied to a bit line of a selected transistor, and a voltage of about 4 to 5 V is applied to a word line to form a current path, thereby storing data. The state of the data is sensed by the bit line.

Reference numeral 14 shown in FIG. 3A increases the breakdown voltage of the source junction region and increases the BTBT (BAND T).
9 shows an N-type ion implantation region having a lower concentration distribution than the source region 12 in order to reduce the current. That is, the cell transistor shown in FIG. 3A is a DDD (DoubleDouble) which has an advantage in the art.
ped Drain) structure. However, even with such a cell transistor structure, the amount of BTBT current does not decrease and still exists as a constant amount. Due to the BTBT current flowing in a constant amount, the tunnel oxide film is degenerated by holes.

The degeneration of the tunnel oxide film is a phenomenon in which holes are trapped in the tunnel oxide film, whereby the tunnel oxide film is deteriorated. In addition, since the adoption of the DDD structure reduces the effective channel length of the transistor, the channel length is longer than a general structure. Assuming DD
If the channel length is set as a general channel length by adopting the D structure, the probability of occurrence of the punch-through phenomenon due to the drain voltage at the time of programming is very high. Therefore, the structure shown in FIG. 3A is difficult for high integration.

In order to improve the above-mentioned problem due to the source erase shown in FIG. 3A and to achieve a low power supply operation and a high integration, a NOR type flash memory having a negative gate biased erase operation has been proposed. High
Speed Sub-halfmicron flash Memory Technology with
Simple Stacked Gate Structure Cell ", Seiichi Mori
et al., 1994 Symposium Technology Digest of Techn
ical Papers, pp. 53-54, and FIG. 4 shows the structure.

In FIG. 4, the erasing operation for the cell transistors M1 and M2 in the cell region is achieved by the source region 12 as in FIG. 3A. However, applying a negative voltage of about -10 V to the control gate of the memory cell transistor for the erasing operation and forming a double well structure for generating the negative voltage in the peripheral region is the case of the erasing operation in FIG. 3A. And different.
In addition, +5 V is applied to the source, and the drain is in a floating state. When erasing is performed through the source region 12 by the negative gate bias erasing operation, the BTBT current decreases as compared with the case of FIG. 3A. Therefore, the problem of deterioration of the tunnel oxide film is relatively reduced. However, the structure has a design rule of 0.4 μm because there is a burden to form a P-type pocket layer lower than the impurity concentration of the substrate 10 below the drain region 13 of the cell transistor.

FIG. 4 shows a well structure and a transistor in a cell region and a peripheral region of the NOR type flash memory.
As shown in FIG.
N-type and P-type MOs for driving low voltage for driving 1, M2
S transistors 20 and 21 and N-type and P-type MOS transistors 22 and 23 for high voltage are arranged. here,
Pocket P-wells 19,2 in N-type wells 16,17
0, the N-type wells 16 and
17 can be formed along the dot line. In this case, the distance between the N-type wells 16 and 17 is narrow as reference numeral “L”. Therefore, there is a problem that the insulation characteristics between the elements are deteriorated. Since the distance “L” decreases as the integration of the flash memory increases, the insulation characteristics may become a serious problem. And a pocket P-well 19,
20 have the same impurity concentration.
It is difficult to adjust the threshold voltages of the S transistor 22 and the low voltage NMOS transistor 20 to be different from each other. On the other hand, since the surface of the substrate 10 is exposed in the cell region, it becomes dirty during the manufacturing process, and the cell transistors M1 and M
There is also a possibility that the operating characteristics of No. 2 may be deteriorated.

As described above, in the conventional NOR type flash memory, since data is erased through the source region which is a one-side junction region, the problem of deterioration of the tunnel oxide film by the BTBT current is completely solved. There is a problem that it is difficult. And the cell transistors M1 and M2
The reduction in the size of the device is affected by the guaranteed conditions of the operating characteristics and reaches its limit. In addition, when a pocket well is manufactured in the peripheral region, insulation properties between wells surrounding the pocket well deteriorate, and it is difficult to lower the threshold voltage of the high-voltage NMOS transistor in the peripheral region. The exposed surface of the substrate in the cell region is easily stained.

[0021]

Accordingly, the first aspect of the present invention is as follows.
An object of the present invention is to provide a well structure of a nonvolatile semiconductor memory device and a method of manufacturing the same, which can solve the conventional problems.

A second object of the present invention is to provide a well structure of a NOR type flash memory capable of erasing data without passing through a source region and a method of manufacturing the same.

A third object of the present invention is to improve the well structure of the cell region and peripheral region of a NOR type flash EEPROM capable of completely solving the deterioration of the tunnel oxide film due to the BTBT current, and the manufacturing method using the same. Is to provide.

A fourth object of the present invention is to provide a NOR flash EEPROM which minimizes the size of a cell transistor and the size of a peripheral region.

A fifth object of the present invention is to improve the insulation characteristics between wells located in the peripheral region, and to increase the threshold voltage of the high-voltage NMOS transistor in the peripheral region as compared with the low-voltage NMOS transistor. An object of the present invention is to provide an improved well structure in a cell area and a peripheral area of a NOR type flash EEPROM which can be adjusted at a low level, and a manufacturing method using the same.

A sixth object of the present invention is to provide a non-volatile semiconductor memory device which is suitable for high integration and has excellent pollution prevention characteristics during manufacturing and excellent operating characteristics after manufacturing.

A seventh object of the present invention is to provide a NOR type nonvolatile semiconductor memory device which is suitable for high integration and has excellent element isolation characteristics.

An eighth object of the present invention is to provide a NOR flash EEPROM having an improved data erasing operation.

[0029]

In order to achieve the above object, the present invention provides a NOR transistor for programming a cell transistor by a channel hot electron injection method and erasing the cell transistor by a FN tunneling method through a bulk region of the cell transistor. A cell region in which a cell transistor formed in a type cell array structure is located, and a peripheral region including P-type and N-type transistors for low voltage and high voltage that are electrically isolated from the cell region, A nonvolatile semiconductor memory device in which a cell region and a peripheral region are formed on a substrate of a first conductivity type; a first well of a second conductivity type opposite to the first conductivity type formed in the cell region; The first to act as a bulk region of the cell transistor
A first pocket well of the first conductivity type formed in the well, a second well of the second conductivity type formed below the low-voltage P-type transistor, and isolated from the second well; A third well of the second conductivity type formed under the high-voltage P-type transistor;
A second pocket well of a first conductivity type formed in a third well below the transistor, and a fourth well of a first conductivity type formed below the N-type transistor for low voltage. A non-volatile semiconductor memory device is provided.

Between the second well and the third well,
It is preferable that a fifth well of the first conductivity type, which is the same as the conductivity type of the fourth well, is further provided to enhance insulation characteristics between the low voltage transistor and the high voltage transistor.

[0031] The present invention for achieving the above-mentioned other objects is as follows.
A cell region in which a cell transistor formed in a NOR type cell array structure is located for programming a cell transistor by a channel hot electron injection method and erasing by a FN tunneling method through a bulk region of the cell transistor; Is electrically isolated from
In a method of manufacturing a well of a nonvolatile semiconductor memory device having a peripheral region including P-type and N-type transistors for low voltage and high voltage, an oxide film and a nitride film are sequentially formed on a P-type semiconductor substrate. Masking a nitride film corresponding to a portion where a P-type well is to be formed, etching an exposed portion of the nitride film to expose a part of the oxide film, and forming a N-type layer through the exposed oxide film. A first well and a first local oxide film are formed in the cell region by ion-implanting a type impurity, and second and third wells and second and third local oxide films are separated from each other in the peripheral region. Forming, removing the remaining nitride film, and ion-implanting the P-type impurity through the exposed oxide film, and then performing local oxidation and heat treatment on the entire surface of the resultant to form the peripheral region. In the area Forming fourth and fifth wells on both sides of the two wells, removing the first through third local oxide films and the exposed oxide film, and forming a buffering oxide film over the entire surface of the resultant structure. Implanting a P-type impurity into the substrate deeper than the first to third wells to prevent punch-through; and forming a portion of a buffering oxide film on the first and third wells. Is exposed, and a P-type impurity is ion-implanted through the exposed buffering oxide film. Then, a photomask pattern is formed to form a first pocket well in a first well and a second pocket well in a third well. Forming a well and heat-treating the well. A method for manufacturing a well of a nonvolatile semiconductor memory device, comprising:

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawing,
The same components and portions are denoted by the same reference numerals and numbers as much as possible. In the following description, specific specific details are shown, but the present invention is not limited to the specific details, and it is apparent that various modifications can be made by those having ordinary skill in the art. . In addition, description of related well-known techniques will be appropriately omitted.

FIG. 3B is a sectional view of the cell transistor shown in FIG. 1 for explaining an erasing method or a substrate applied to the present invention. In FIG. 3B, since erasing is performed on the channel or the substrate 10, the BTBT shown in FIG.
No current is generated. During the erase operation, 0 V is applied to the word line of the cell transistor, and about 15 V is applied to the substrate 10. Otherwise, about -10V is applied to the word line, and about 5V erase voltage is applied to the substrate 10. As a result, of the many cells belonging to the selected word line, the cells having electrons in the floating gate are erased at once. That is, a voltage difference is generated between the substrate 10 and the floating gate of the selected cell by the applied voltage, and the electrons stored in the floating gate are transferred to the substrate 10 or bulk silicon through the tunnel oxide film due to the voltage difference. Released. This is also F
This is an erasing operation by the N-tunneling method. The threshold voltage of the cell selected by the completion of the erase operation is
The initial voltage is reduced to, for example, about 2V. The substrate 1
In order to apply a positive high voltage to 0, it is necessary to form a well of the same conductivity type as the substrate 10 in the substrate 10 as a pocket type. This is the bulk region.

When programming the cell transistor shown in FIG. 3B, about 10 V is applied to the word line and about 6 V to the bit line. Thereby, thermions generated together with the current due to the turn-on of the cell transistor are injected into the floating gate FG. As a result, the programmed cell transistor has a threshold voltage of about 7V.

On the other hand, the read operation for the programmed cell transistor involves applying about 1 V to the bit line,
This is achieved by applying a power supply voltage of about 0 V to the source line and about 5 V to the word line. in this case,
Since the cell transistor has a threshold voltage of about 7V, almost no current flows through the corresponding bit line. Therefore, the sense amplifier connected to the bit line outputs this as data "1". However, if the cell transistor has a threshold voltage of about 2 V even after the completion of the programming operation, this is the case when the cell transistor is programmed as data "0". In this case, a current of a certain level flows through the bit line during a read operation. Therefore, the sense amplifier senses this as data "0".

FIG. 5 is a sectional view showing a well structure in a cell region and a peripheral region of a NOR type flash memory according to an embodiment of the present invention. Since data programming is performed by the channel thermal electron injection method and erasing is performed by the FN tunneling method through the channel or bulk region, cell transistors M1 and M2 forming a NOR type cell array structure are located in the cell region. The well structure of the cell region functions as a first N well 30 formed with a conductivity type (N) opposite to the conductivity type of the P-type substrate 10 and the bulk region of the cell transistors M1 and M2. To be surrounded by the first N-well 30 and the substrate 10
And a first pocket P-well 36 formed of the same conductivity type (P) as the first conductivity type.

On the other hand, the peripheral area where the low voltage (LV) and high voltage (HV) transistors 20, 21, 22, 23 are located is electrically isolated from the cell area by the field oxide film 40, and Of the low-voltage and high-voltage transistors, the second type is formed separately on the substrate 10 with a conductivity type opposite to the conductivity type of the substrate 10 to accommodate the P-type transistors 21 and 23, respectively. N
A well 31 and a third N-well 32 are surrounded by the third N-well 32 for accommodating the N-type transistor 22 of the high voltage transistors, and have the same conductivity as the conductivity type of the substrate 10. A second pocket P-well 37 formed of a mold, and the first N-well having the same conductivity type as that of the substrate 10 for accommodating the N-type transistor 20 among the transistors for low voltage. 30
And a first P well 34 formed in the substrate 10 between the first P well 34 and the second N well 31. Between the second N-well 31 and the third N-well 32, the first P-well 34 and the first P-well 34 are provided in order to enhance the insulation characteristics between the low-voltage transistor and the high-voltage transistor. The second P-well 35 having the same conductivity type can be formed. Therefore, since the data is erased through the bulk 36, the problem of deterioration of the tunnel oxide film caused by the BTBT current can be completely solved. In addition, the surface of the substrate 10 is not exposed in any of the cell region and the peripheral region,
Since it is located below the well, it is insensitive to contamination during the manufacturing process, and the operating characteristics of the transistor are guaranteed.

The stacked gate 55 of the cell transistors M1 and M2 and the low-voltage and high-voltage transistors 20,
The gates 21, 22, 23 are manufactured by a normal manufacturing method after forming the field oxide films 40, 41, 42, 43 in the well structure of the present invention.

FIGS. 6 to 15 are views sequentially showing the steps of manufacturing wells and transistors in the cell region and the peripheral circuit region shown in FIG. Hereinafter, the manufacturing process of the structure shown in FIG. 5 will be described with reference to this drawing.

Referring to FIG. 6, a P-type semiconductor substrate 10 is formed.
An oxide film 60 and a nitride film 62 are sequentially formed on the upper surface.
This preferably has a resistivity of about 5 to 15 Ωcm.
After the initial cleaning of the mold substrate 10, about 300 to
An oxide deposition process is performed to have a thickness of 900 .ANG.
Is deposited.

FIG. 7 shows an ion implantation step for forming the first to third N wells 30, 31, and 32 shown in FIG. Specifically, a photoresist film pattern 63 is formed so as to cover only the nitride film 62 above the portion where the P well is formed, and the exposed nitride film 62 is etched to form the oxide film 60. Expose part. Thereafter, an N-type impurity, for example, phosphorus (P) is ion-implanted into the substrate 10 through the exposed oxide film 60 at an energy of 100 to 200 keV.

FIG. 8 shows the first to third N wells 3.
FIG. 6 shows an ion implantation step for forming 0, 31, 32 and the first and second P-wells 34, 35 shown in FIG. Referring to FIG. 8, when local oxidation, for example, LOCOS and heat treatment, for example, drive-in at 1000 ° C. or higher, a first N well 30 and a first local oxide film 64 are formed in the cell region. A second area is provided in the peripheral area.
And third N wells 31 and 32 and second and third local oxide films 65 and 66 are formed separately from each other. Here, it is desirable that the thickness of the local oxide film be about 3000-6000 °.

Thereafter, the photoresist film pattern 6
3 and the nitride film 62 are removed, and then the local oxide film 6 is removed.
4, 65, 66 are used as an ion implantation mask, and a P-type impurity, for example, boron (B) is ion-implanted into the substrate 10 at an energy of 50 keV or less.

FIG. 9 shows the first and second P-wells 34 and 35 by ion implantation in FIG. 8 and an ion implantation step for preventing punch-through. Referring to FIG. 9, the P for the NMOS for low voltage is formed through the ion implantation of FIG.
Well 34 and P well 35 are simultaneously formed on both sides of N well 31. Thereafter, the local oxide films 64, 65, 6
6 and the exposed oxide film 60 are removed, and a buffering oxide film 70 is formed on the entire surface of the resultant structure. The buffering oxide layer 70 functions as a buffer during high energy implantation.
It is formed with a thickness of 00 ° or more. Thereafter, in order to prevent punch-through, a P-type impurity, for example, boron is doped with high energy of 1 MeV or more at the first to third N wells 30 and 3.
Ions are implanted over the entire surface of the buffering oxide film 70 deeper than the depths of 1 and 32, that is, up to reference numeral 72.
The first to third N wells 30 and 3
Side diffusion between the transistors 1 and 32 is prevented, and element isolation characteristics between high-voltage and low-voltage transistors are ensured.

FIG. 10 shows the first and second pockets P of FIG.
4 shows an ion implantation step for forming the wells 36 and 37. Referring to FIG. 10, a portion of the buffering oxide layer 70 above the first and third N wells 30 and 32 is exposed using a photoresist layer pattern 75,
A P-type impurity, for example, boron is implanted at an energy higher than the dose of the N well and at least 80 Kev.

FIG. 11 shows the step of completing the well shown in FIG. Referring to FIG. 11, a first pocket P well 36 serving as a bulk region of the cell transistors M1 and M2 and a second pocket P well 37 for the high voltage NMOS transistor 22 are formed by the ion implantation of FIG. Is done. Thereafter, the photoresist film pattern 75 is removed, and a high-temperature heat treatment is performed on the entire surface of the resultant structure to form the wells 30 to 32 and 34 to 37 in a complete form.

6 to 11, the cell transistors M1 and M2 in the cell region and the N for high voltage in the peripheral region are formed.
The first and second pocket P-wells 36 and 37 in which the MOS transistor 22 is formed, the first P-well 34 in which the low voltage NMOS transistor 20 is formed, the low voltage PMOS transistor 21 and the high voltage And third N well 3 in which the PMOS transistor 23 is formed.
1 and 32 are completely formed.

Hereinafter, a method of forming the stacked gate 55 of the cell transistors M1 and M2 and the gate 56 of the low-voltage and high-voltage transistors 20 to 23 shown in FIG. 5 in the well structure according to the present invention will be described.

FIG. 12 shows the step of forming the field oxide film. Referring to FIG. 12, an active region in which a transistor device is substantially formed using a LOCOS process, which is a general device isolation method, and field oxide films 40 to 43 having a thickness of 4000 .ANG. Is done.

FIG. 13 shows a step of sequentially forming a tunnel oxide film 50, a first polysilicon layer (poly-1) 51, and an ONO film 52 only in the cell region in order to increase the program and erase efficiency. Here, the tunnel oxide film 50 is 80
The first polysilicon layer 51 may be deposited with POCl ₃ by depositing a thickness of about 100 °. Thereafter, the ONO film and the first polysilicon layer in the peripheral region are exposed using the photoresist film pattern 77 and anisotropically etched.

FIG. 14 shows a step of forming a photoresist film pattern for forming a second polysilicon layer, a tungsten silicide layer, and a cell transistor. FIG.
Referring to FIG. 4, after the process of FIG. 13, ion implantation for adjusting the threshold voltage of the transistor in the peripheral region is selectively performed, and the gate oxide film (80 to 150 °) used for the low voltage transistor and the high voltage Oxide film (200-350Å) used for transistor for semiconductor
Is selectively oxidized. Thereafter, a second polysilicon layer (poly-2) 53 used for control gates in the cell region and the peripheral region may be deposited, and POCl ₃ may be deposited. When forming a gate having a polycide structure, a tungsten silicide (WSix) layer 54 is formed on the second polysilicon layer 53. Thereafter, the peripheral region is covered with the photoresist film pattern 78, and the cell region is selectively opened.

FIG. 15 shows the steps of forming the cell transistor in the cell region and the high and low voltage transistors in the peripheral region. Referring to FIG. 15, the tungsten silicide layer 54, the second polysilicon layer 53, the ONO film 52, and the first polysilicon film 51 in the cell region are formed using the photoresist film pattern 78 as an etching mask.
Are sequentially etched to form cell transistors M1 and M2 having a floating gate FG and a control gate CG. Thereafter, the photoresist film pattern 78 is formed.
Get rid of.

Next, the cell region is covered with the photoresist film pattern 80, and the peripheral region is selectively opened, and then the tungsten silicide layer 54 and the second polysilicon layer 53 in the exposed peripheral region are etched. To form high voltage and low voltage transistors. Here, FIG.
The pattern of the peripheral region can be formed first by changing the process sequence of FIG.

According to the steps shown in FIGS. 12 to 15, the tunnel oxide film 5 is formed in the cell region on the first pocket P well 36.
0, the first polysilicon layer 51, the ONO film 52 and the second
Cell transistors M1 and M2 having stack gate 55 made of polysilicon layer 53 are formed. In the peripheral region, a low-voltage NMOS and PM having a low-voltage gate oxide film 50 and a low-voltage gate electrode 56 composed of a second polysilicon layer 53 and a tungsten silicide layer 54.
OS transistors 20 and 21 are formed on the first P-well 34 and the second N-well 31 and have a high-voltage gate oxide film 50 and a high-voltage gate composed of a second polysilicon layer 53 and a tungsten silicide layer 54. A high-voltage NMOS and PMOS transistor 22 having an electrode 56;
23 is a second pocket P-well 37 and a third N-well 3
2 is formed at one site.

FIG. 5 is a sectional view showing a cell region and a peripheral region of a transistor formed by impurity ion implantation for complete formation of the transistor. In the case of a cell transistor and an NMOS transistor, As (Arseni
c) Source and drain junctions are formed by ion implantation of N-type impurities such as Ph (Phosphorous),
B (boron), BF2 (born fl
The source / drain junction is formed by ion implantation of a P-type impurity such as uoride).

In the case of a conventional cell transistor, the junction structure reduces the source BTBT current and increases the junction breakdown voltage in the case of conventional source erase, as shown in FIG.
As shown in the above, a DDD structure having a relatively high concentration N + region and a low concentration N− region is employed. However, in the case of the present invention, since erasing is performed on the substrate or bulk, DDD, LD
Not only D (lightly doped drain) but also a conventional structure can be joined. A positive voltage is applied to the bulk below the channel of the cell transistor because there is a pocket P-well (PPWELL) in the N-well of the P-type substrate for erasing to the bulk substrate below the channel. Then, the N-well and the P-type substrate form a junction in opposite directions, so that there is no leakage current to the substrate.

In the peripheral region, in the case of a CMOS operating at a low voltage to form a logic circuit or the like, an NMOS is formed in a P well formed in a P sub (P type substrate), and a PMOS is formed in a P well. It is formed in an N well formed on the sub. As the junction structure, an LDD structure for preventing punch-through in a single channel or a conventional structure can be used. In the case of CMOS for applying a positive or negative high voltage to the cell, the NMOS reduces the body effect, maintains a low threshold voltage, and prevents the negative voltage from being released to the P-sub. N having a relatively lower concentration as compared to the P well formed above
A pocket is formed on the P-well surrounded by the well, and a PMOS is formed on the N-well. At this time, the N-well is charged as a positive voltage during the operation of the circuit,
It should be isolated from the N-well in which the low-voltage transistors forming the logic circuit are formed. On this occasion,
When the N-well is not isolated and used, a high voltage is released. In addition, the junction used in such a circuit for driving a high voltage increases the junction breakdown voltage at a high voltage by using DDD and LDD. DDD and L
In the process of forming the DD junction, spacers can be used,
One ion implantation can be performed before the formation of the spacer, and a junction structure such as DDD or LDD can be formed by ion implantation even after the spacer is used. After the formation of the joint is completed, H
After depositing TO and BPSG, perform BPSG reflow at a temperature of 800 ° C or higher to form a contact that joins the metal conductor and the metal conductor and the poly electrode to join the metal conductor and join the metal conductor and the poly electrode. I do.

[0058]

As described above, according to the present invention, the BT
The problem of deterioration of the tunnel oxide film due to the BT current can be solved, the size of the cell transistor can be reduced, and when a pocket well is manufactured in the peripheral region, the insulating property between the well surrounding the pocket well and the peripheral well is obtained. Is improved. In addition, N for high voltage in the peripheral region
It is easy to adjust the threshold voltage of the MOS transistor relatively low, and it is insensitive to contamination. This is advantageous for high integration and element insulation, and also improves the reliability of cell operation.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a normal NOR type self-lay structure applied to the present invention.

FIG. 2 is an equivalent circuit diagram showing a normal NAND type self-lay structure.

3A is an explanatory diagram of a source erasing method for the cell of FIG. 1, and FIG. 3B is an explanatory diagram of a substrate erasing method for the cell of FIG. 1 applied to the present invention.

FIG. 4 is a sectional view showing a well structure and a transistor in a cell region and a peripheral region of a normal NOR type flash memory;

FIG. 5 is a sectional view showing a well structure and a transistor in a cell region and a peripheral region of a NOR flash memory according to the present invention;

FIG. 6 is a view sequentially showing a manufacturing process of the cross-sectional structure of FIG. 5;

FIG. 7 is an explanatory view sequentially showing a manufacturing process of the sectional structure of FIG. 5;

FIG. 8 is an explanatory view sequentially showing a manufacturing process of the cross-sectional structure of FIG. 5;

FIG. 9 is a view sequentially showing a manufacturing process of the cross-sectional structure of FIG. 5;

FIG. 10 is an explanatory view sequentially showing a manufacturing process of the sectional structure of FIG. 5;

FIG. 11 is an explanatory view sequentially showing a manufacturing process of the sectional structure of FIG. 5;

FIG. 12 is a view sequentially showing a manufacturing process of the cross-sectional structure of FIG. 5;

FIG. 13 is an explanatory view sequentially showing a manufacturing process of the sectional structure of FIG. 5;

FIG. 14 is an explanatory view sequentially showing a manufacturing process of the sectional structure of FIG. 5;

15 is a view sequentially showing a manufacturing process of the cross-sectional structure of FIG. 5;

[Explanation of symbols]

 M1, M2 cell transistor, 10 semiconductor substrate, 20, 21, 22, 23 transistor, 30 first N well, 31 second N well, 32 third N well, 34 first P well, 35: second P well, 36: first pocket P well, 37: second pocket P well, 40, 41, 42, 43 ... field oxide film, 64 ... first local oxide film, 65 ... Second local oxide film, 66... Third local oxide film.

Claims (4)

[Claims] A cell region in which a cell transistor formed in a NOR type cell array structure is located for programming a cell transistor by a channel hot electron injection method and erasing by a FN tunneling method through a bulk region of the cell transistor. And a peripheral region electrically isolated from the cell region and including P-type and N-type transistors for low voltage and high voltage, wherein the cell region and the peripheral region are formed on a substrate of a first conductivity type. In the nonvolatile semiconductor memory device, the first well of the second conductivity type opposite to the first conductivity type formed in the cell region, and the first well to act as a bulk region of the cell transistor A first pocket well of the first conductivity type formed, and a second conductivity type formed below the low voltage P-type transistor. A second well of a second conductivity type formed under the P-type transistor for high voltage and isolated from the second well, and a third well of a second conductivity type formed under the N-type transistor for high voltage. A nonvolatile semiconductor device comprising: a first conductivity type second pocket well formed in three wells; and a first conductivity type fourth well formed below the low voltage N-type transistor. Memory device. 2. The semiconductor device according to claim 1, wherein the second well and the third well have the same conductivity type as that of the fourth well in order to enhance insulation characteristics between the low-voltage transistor and the high-voltage transistor. The nonvolatile semiconductor memory device according to claim 1, further comprising a fifth well of the first conductivity type. 3. A cell region in which a cell transistor formed by a NOR type cell array structure is located for programming a cell transistor by a channel hot electron injection method and erasing by a FN tunneling method through a bulk region of the cell transistor. And a peripheral region including low-voltage and high-voltage P-type and N-type transistors, which is electrically isolated from the cell region. After an oxide film and a nitride film are sequentially formed on the substrate, a nitride film corresponding to a portion where a P-type well is formed is masked, and an exposed portion of the nitride film is etched to partially remove the oxide film. Exposing, and ion-implanting N-type impurities through the exposed oxide film to form a first well and a first local oxide film in the cell region. Forming second and third wells and second and third local oxide films in the peripheral region at a distance from each other; removing the remaining nitride film; Ion-implanting the P-type impurity through the film, performing local oxidation and heat treatment on the entire surface of the resultant structure to form fourth and fifth wells on both sides of the second well in the peripheral region; After removing the first to third local oxide films and the exposed oxide film and forming a buffering oxide film on the entire surface of the resultant structure, P-type impurities are added to the first to third impurities to prevent punch-through. Implanting into the substrate a depth greater than the well depth, exposing a portion of the buffering oxide film above the first and third wells, and removing P-type impurities through the exposed buffering oxide film. Forming a photomask pattern to form a first pocket well in a first well and a second pocket well in a third well, and heat-treating the well. For manufacturing a well of a nonvolatile semiconductor memory device. 4. A cell region in which a cell transistor formed in a NOR type cell array structure is located for programming a cell transistor by a channel hot electron injection method and erasing by a FN tunneling method through a bulk region of the cell transistor. And a peripheral region electrically isolated from the cell region and including P-type and N-type transistors for low voltage and high voltage, wherein the cell region and the peripheral region are formed on a substrate of a first conductivity type. A first well of a second conductivity type opposite to the first conductivity type formed in the cell region; and a first pocket of a first conductivity type formed in the first well. A well, a second well of the second conductivity type formed in the peripheral region, and a second pocket well of the first conductivity type formed in the third well. The nonvolatile semiconductor memory device, characterized in that it comprises.