KR19990052461A - Well Structure of Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereby - Google Patents

Abstract

In order to improve device isolation characteristics and reliability of operation, an improved cell structure and a peripheral structure of a nonvolatile semiconductor memory device and a manufacturing method thereof are disclosed. The disclosed structure has a noble well structure in which data is programmed by channel hot electron injection and erase is performed by F-N tunneling through the bulk region.

Description

Well Structure of Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof

TECHNICAL FIELD The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to an improved cell structure and a peripheral structure of a NOR-type flash EEPROM (NOR-type flash EEPROM) and a manufacturing method thereof.

In general, mask ROM, EPROM, EEPROM, flash-EEPROM, and the like are widely known in the art as nonvolatile semiconductor memory devices. Among these, Flash YPyrom has the function to erase data at once and in addition to the operation characteristics of YPyrom, and it has low power consumption, so not only the permanent memory of personal notebook computer but also digital camera, memory card, etc. The trend is also attracting attention as a recording medium of the same portable terminal. The state of data stored in the nonvolatile semiconductor memory device is determined by a threshold voltage of the cell transistor. The threshold voltage refers to the threshold voltage if the cell transistor starts to turn on at a certain threshold voltage when the voltage difference is gradually increased between the gate terminal and the source terminal of the cell transistor. In the case of EPROM, EEPROM, or Flash-EEPROM, each cell transistor has a floating gate therein that is isolated from the control gate. By differentializing the amount of charge stored in the floating gate, the threshold voltage of each cell transistor is changed to the intended set level, respectively. Accordingly, data is stored (programmed) to have a state that can be distinguished from each other in the read operation. In order to read the state of data stored in each cell transistor, it is necessary to check the storage state of programmed cells. To this end, a decoder circuit is used to apply signals in the form of voltages required to select and read a desired memory cell to the memory cell, the cell transistor, and a circuit associated therewith. As a result, a signal of current or voltage according to the storage state of the memory cell is obtained on the bit line. When the current or voltage signal thus obtained is measured with a sense amplifier called a sense circuit, the state information stored in the memory cell is represented as data "1" or data "0".

The structure of a flash Y pyrom memory cell array is divided into NOR-type and NAND-type according to the form in which memory cells are connected to a bit line. In the case of the NOR type, each of the memory cells M1, M3, and M5 is connected between the bit line BL1 and the source line CSL as in the structure of FIG. The memory cells M1 and M2-M4 form a string structure together with the selection transistors ST1 and ST2 and are connected in series between the bit line BL and the ground line. Each of the memory cell transistors shown in FIGS. 1 and 2 has a control gate CG connected to a word line, and a floating gate FG isolated from the control gate CG. The noah type cell array structure shown in FIG. 1 is disadvantageous in terms of integration density of cell transistors in connection with the NAND cell array structure of FIG. 2, but has a high speed operation due to a relatively large amount of cell current in terms of read operation. Therefore, in order to respond to relatively high speed operation, the memory cell array structure of flash Y pyrom has tended to be converted from a NAND type to a noah type, and attempts to achieve high integration of cell transistors have been disclosed in various prior arts. have. As one of these prior arts, the NOR type flash EEPROM structure is published by Satyen Mukherjee et al. 512K CMOS EEPROM ". In the above prior art, also disclosed in US Pat. No. 4,698,787 issued in the United States, the data program into the memory cell is performed by channel hot electron (CHE) injection, and the erase of the programmed data is performed as shown in FIG. 3A. The Fowler-Nordheim (FN) tunneling method is performed through a source region, which is a junction region in one direction. Referring to FIG. 3A, which corresponds to the cross section of any cell transistor in FIG. 1, a data erasing scheme is shown for a source region (or drain region) that is a junction region in one direction. Erasing data means changing the threshold voltage value of the programmed cell transistor to an initial threshold voltage value, which is achieved as the discharge of charge. To do this, when about 0 Volt is applied to the control gate CG of the cell transistor connected to the selected word line and about 12 Volt is applied to the source region 12, electrons stored in the floating gate FG are lowered by FN tunneling. Through the source region 12.

In order that the above-described source erasing operation can be more specifically understood and can be thoroughly distinguished from the present invention which will be described later, each operation mode of the cell transistor of the noah type structure will be described in detail by way of example. If the cell transistor shown in Fig. 3A retains electrons in its floating gate FG, it is referred to as a data " 1 " state. The operation of changing the cell transistor in the data " 0 " state to the data " 1 " state is commonly referred to as program operation in the art. For such a program operation, voltage signals necessary for a cell transistor having a threshold voltage of about 2 volts should be applied to increase the threshold voltage to about 7V. In this program operation, about 5 to 6V is applied to the drain D connected to the selected bit line, about 10 to 12V is applied to the control gate CG connected to the selected word line and 0V is applied to the source S and the substrate or bulk 10. The cell transistors are then turned on so that cell current flows from drain region 13 to source region 12. Some of the hot electrons generated at this time are injected into the floating gate FG through a gate oxide film (tunnel oxide film) by a vertical electric field of the gate CG. The threshold voltage of the cell transistor is initially increased from 2 to 7 volts by the injection of the channel hot electrons. Even when the program operation is terminated, hot electrons injected into the floating gate FG are isolated by the gate oxide film and the triple layer having the O / N / O structure, so that the cell transistor in which the program is completed has a separate erase operation. It retains data permanently until it exists. On the other hand, the above erase operation is to emit electrons stored in the floating gate FG so that the threshold voltage of the cell transistor becomes the initial threshold voltage, that is, about 2V here. In this case, the bit line connected to the drain D of the selected cell transistor is allowed to float, and about 12 to 15 V is applied to the common source line CSL connected to the source S and 0 V is applied to the word line. As a result, a voltage difference is generated between the floating gate FG and the source junction region 12, and accordingly, electron tunneling occurs through a tunnel oxide film of about 100 kV. This phenomenon is the F-N tunneling scheme well known in the art. In this manner, electrons isolated in the floating gate FG are emitted to the source region 12 through the oxide film. Due to such an erase operation, since there are almost no electrons in the floating gate FG, the threshold voltage of the cell transistor is lowered again to maintain the original threshold voltage of 2 volts. On the other hand, during the read operation, a voltage of about 1V is applied to the bit line of the selected transistor and about 4 to 5V is applied to the word line to form a current path, thereby detecting the state of the stored data through the bit line.

The region 14 shown in FIG. 3A has an N-type ion implantation having a concentration distribution lower than that of the region 12 in order to increase the breakdown voltage of the source junction region and reduce the band-to-band tunneling (BTBT) current. Area. That is, the cell transistor of FIG. 3A has a double doped drain (DDD) structure, which is well known in the art. However, even in such a cell transistor structure, the BTBT current is not only reduced but is still present as a constant amount. When the BTBT current flows with a constant amount, the degradation of the tunnel oxide film due to holes occurs incidentally due to the BTBT current. The degradation of the tunnel oxide film is a phenomenon in which holes are trapped in the tunnel oxide film, and thus the tunnel oxide film has a defect of deterioration. In addition, since the adoption of the DDD structure reduces the effective channel length of the transistor, the length of the channel is longer than that of the general structure. Thus, this structure of FIG. 3A limits the high integration. If the channel length is set to the general channel length while adopting the DDD structure, the punch-through phenomenon due to the drain voltage during programming is very high.

In order to ameliorate the drawbacks due to the source erase of FIG. 3A and to promote low power supply operation and high integration, a quinoa flash memory having a negative gate biased erase scheme is described by Seiichi Mori et al. Many have been published under the title "High Speed Sub-halfmicron Flash Memory Technology with Simple Stacked Gate Structure Cell" published on pages 53-54 of the 1994 Symposium Technoiogy Digest of Technical Papers (VLSI) in 1994. It has the structure shown in FIG. An erase scheme for the cell transistors M1 and M2 in the cell region in FIG. 4 is achieved through the source region 12 as in FIG. 3A. However, applying a negative voltage of about -10 volts to the control gate of the memory cell transistor for the erase operation and forming a double well structure for generating the negative voltage in the peripheral region are different from the erase case in FIG. 3A. . In addition, +5 volts is applied to the source and the drain is in a floating state. When the erase is performed through the source region 12 by the above condition, that is, a negative gate biased erase scheme, the BTBT current is further reduced than in the case of FIG. 3A. Therefore, the degradation problem of the tunnel oxide film is relatively small. However, the above structure has a burden of manufacturing a low density pouch pocket (P-) layer which is lower than the impurity concentration of the substrate under the drain region of the cell transistor, and thus has a design rule of 0.4 micron.

Referring to FIG. 4, which shows the well structure and transistors of the cell region and the peripheral region of the noah type flash memory as a cross-sectional view, in the peripheral region, a low voltage en-type and a type Morse transistor 20 and 21 and a high voltage are used to drive the memory cell transistor. The N type and the MOS transistors 22 and 23 are disposed. Here, the shape of the lower portion of the N-type wells 16 and 17 may be formed along the dot line due to side diffusion when the pocket wells 19 and 20 are formed in the N-type wells 16 and 17. In this case, the distance between the wells is narrow as the sign L. Therefore, there is a problem in that the insulation characteristics between the elements become weak. Since the distance L is reduced according to the high density of the flash memory, the insulation characteristic may be a serious problem. In addition, since the impurity concentrations of the pocketed wells 19 and 20 are the same, it is difficult to adjust the threshold voltages of the high voltage en-type MOS transistor 22 and the low voltage en-type MOS transistor 20 differently. On the other hand, since the surface of the substrate is exposed in the cell region, the substrate may be contaminated during the manufacturing process, thereby degrading operation characteristics of the cell transistor.

As described above, in the conventional Noah-type flash memory, since data is erased through the source region, which is a junction region in one direction, there is a problem that the degradation of the tunnel oxide film due to the BTBT current cannot be completely solved. In addition, the size reduction of the cell transistor is limited by the operation condition guarantee conditions. In addition, when fabricating a pocket well in a peripheral region, there is a problem that insulation characteristics between the wells surrounding the pocket well may be degraded, and it is difficult to control the threshold voltage of the high-voltage en-type MOS transistor in the peripheral region to be low and vulnerable to contamination. have.

Accordingly, an object of the present invention is to provide a well structure of a nonvolatile semiconductor memory device and a method of manufacturing the same, which can solve the above-mentioned problems.

It is another object of the present invention to provide a well structure of a quinoa flash memory capable of erasing data without going through a source region and a method of manufacturing the same.

It is still another object of the present invention to provide an improved cell structure and a well structure of a quinoa flash EEPROM capable of solving the degradation of the tunnel oxide film due to BTBT current, and a manufacturing method thereof.

It is still another object of the present invention to provide a NOR-type flash EEPROM capable of minimizing the size of the cell transistor and the size of the peripheral region.

It is still another object of the present invention to improve the insulating properties between wells located in the peripheral region and to improve the cell voltage of the NOR-type flash EEPROM that can adjust the threshold voltage of the high voltage en-type MOS transistor in the peripheral region lower than that for the low voltage. And a well structure of the peripheral region and a method of manufacturing the same.

It is still another object of the present invention to provide a nonvolatile semiconductor memory device which is suitable for high integration and has excellent anti-pollution characteristics during manufacturing and operation characteristics after manufacturing.

It is still another object of the present invention to provide a noah type nonvolatile semiconductor memory device suitable for high integration and having excellent device isolation characteristics.

Another object of the present invention is to provide a quinoa flash EEPROM having an improved erase operation.

In order to achieve the above objects, a well structure of a nonvolatile semiconductor memory device according to an aspect of the present invention is designed to perform a program of data by a channel hot electron injection method and an FN tunneling method through a bulk region to erase data. The cell region in which the cell transistors forming the type cell array structure are located is formed in the first well and the first well formed in the substrate in order to function as the bulk region of the cell transistors in a conductivity type opposite to that of the substrate. And a first pocket well formed by the same conductivity type as the conductivity type of the substrate, and electrically isolated from the cell area, where the low voltage and high voltage transistors are located. Contrary to the conductivity type of the substrate for accommodating each of the heavy transistors The second and third wells formed separately on the substrate in the conductivity type of the substrate, and surrounded by the third well to accommodate the N-type transistors among the high voltage transistors, and the same conductivity type as the conductivity type of the substrate. And a fourth well formed on the substrate between the first and second wells in the same conductivity type as that of the substrate to accommodate the N type transistors among the low voltage transistors. . Here, a fifth well of the same conductivity type as that of the fourth well may be formed between the second and third wells in order to enhance insulation characteristics between the low voltage transistors and the high voltage transistors.

Further, according to another aspect of the present invention, in a nonvolatile semiconductor memory device for programming data by channel hot electron injection and erasing by FN tunneling through a bulk region, a cell forming a quinoa cell array structure A method for fabricating a well in a cell region in which transistors are located and a well in a peripheral region in which low voltage and high voltage transistors are electrically isolated from the cell region, includes: an oxide film and a nitride film are sequentially formed over an entire semiconductor substrate. After forming, masking only the nitride film placed over the portion where the wells are to be formed and etching the unmasked nitride film to expose a portion of the oxide film; After implanting the N-type impurity ions for forming the N-type well through the exposed oxide film into the substrate, local oxidation and heat treatment are performed to initially form the first well and the first local oxide film in the cell region. Allowing the second and third wells and the second and third local oxide films to be initially formed in the peripheral area at a distance from each other; After removing the remainder of the nitride film, implanting impurity ions for forming the wells into the substrate through the exposed oxide film to initially form the fourth and fifth wells with the second well interposed therebetween; ; After removing the first, second, and three local oxide films and the exposed oxide film and forming a buffering oxide film, implanted impurity ions are formed deeper than the first, second, and third wells to prevent punch-through. Injecting; A first pocket well serving as the bulk region of the cell transistors by exposing the buffered oxide film on the upper part of the first and third wells with a photomask pattern and implanting the dopant ions to form a pocket well; Initially forming a second pocket well for accommodating N-type transistors among the high voltage transistors; And performing a heat treatment to form the wells in a complete form.

According to the above-described well structure and its manufacturing method, it is possible to provide a nonvolatile semiconductor memory device which is suitable for high integration and excellent in pollution prevention characteristics during fabrication and operation after fabrication, and has excellent device isolation characteristics and improved erase operation. Advantages are obtained.

1 is an equivalent circuit diagram showing a structure of a conventional noah-type cell array as applied to the present invention.

2 is an equivalent circuit diagram showing a conventional NAND cell array structure.

3A is a diagram for describing a source erase method for the cell of FIG. 1.

3B is a diagram illustrating a substrate erasing method for the cell of FIG. 1 as an erasing method applied to the present invention.

4 is a cross-sectional view illustrating well structures and transistors of a cell region and a peripheral region of a typical NOR flash memory.

5 is a cross-sectional view illustrating well structures and transistors of a cell region and a peripheral region of a quinoa flash memory according to the present invention.

6 to 15 are views for explaining the sequential manufacturing process for making the cross-sectional structure of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Elements or parts that are identical to one another in the accompanying drawings are labeled with the same or similar reference numerals or names for convenience of understanding, even if in different drawings. In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details. In addition, the detailed operation of the MOS transistor having a floating gate so well known in the art and the known part of the manufacturing process are not described in detail to obscure the subject matter of the present invention.

First, FIG. 3B is a diagram illustrating a substrate or channel erasing method for the cell of FIG. 1 as an erasing method applied to the present invention. In FIG. 3B, since the erase to the channel or the substrate 10 is performed, the BTBT current as in FIG. 3A does not occur. In the erase operation, 0V is applied to the word line of the cell transistor, about 15V is applied to the substrate 10, or about 5V is applied to the substrate 10, and about -10V is applied to the word line. Doing so erases all of the cells retaining electrons in the floating gate of the plurality of cells belonging to the selected word line at one time. That is, a voltage difference is generated between the substrate and the floating gate of the selected cells due to the applied voltage, and electrons stored in the floating gate are released to the substrate or the bulk silicon through the tunnel oxide film according to the voltage difference. This is also an erase by the F-N tunneling method. The threshold voltage of the cells selected by the completion of the erase operation is lowered to an initial voltage, for example, about 2V. In order to apply a positive high voltage to the substrate 10, it is necessary to make a pocket of the same conductive well as the substrate on the substrate. This is the bulk area. In the case of programming the cell transistor of FIG. 3B, about 10V is applied to the word line and about 6V is applied to the bit line. In doing so, hot electrons generated together with the current by the turn-on of the cell transistor are injected into the floating gate FG. As a result, the programmed cell transistor has a threshold voltage of about 7V. On the other hand, the programmed read operation for the cell transistor is achieved by applying a power supply voltage of about 1V to the bit line, about 0V to the source line, and about 5V to the word line. In this case, since the threshold voltage of the cell transistor is about 7 V, almost no current flows in the corresponding bit line. Therefore, the sense amplifier connected to the bit line senses and outputs this as data "1". Conversely, if the cell transistor had a threshold voltage of about 2V even after the completion of the program operation, this is the case where it is programmed as data "0". In this case, a constant level of current flows in the bit line during read. Thus, the sense amplifier senses this as data "0".

Referring to FIG. 5, well structures and transistors of a cell region and a peripheral region of a noah type flash memory according to an exemplary embodiment of the present invention are shown as cross-sectional views. In order to program data by channel hot electron injection and erase by F-N tunneling through a channel or bulk region, a cell region is a region where cell transistors M1 and M2 forming a quinoa cell array structure are located. The well structure of the cell region is a N-type conductivity opposite to that of the substrate 10, and the first well 30 formed on the substrate 10 and the first region to function as the bulk region of the cell transistors M1 and M2. A first pocket well 36, surrounded by well 30 and formed of the same conductivity type P as the conductivity type of the substrate. Meanwhile, the peripheral region in which the low voltage and high voltage transistors 20, 21, 22, and 23 are positioned by being electrically isolated from the cell region by the field oxide layer 40 is formed of the transistors 21 and 23 of the low voltage and high voltage transistors. To accommodate the second well 31 and the third well 32 separately formed on the substrate 10 in a conductivity type opposite to that of the substrate 10, and the N type transistors 22 of the high voltage transistors. A second pocket well 37 enclosed by the third well 32 and formed of the same conductivity type as the conductivity type of the substrate 10, and conductive of the substrate to accommodate the N type transistors 20 of the low voltage transistors. A fourth well 34 formed in the substrate between the first and second wells in the same conductivity type as the mold. A fifth well 35 having the same conductivity type as that of the fourth well 34 may be formed between the second and third wells in order to enhance the insulating property between the low voltage transistors and the high voltage transistors. Therefore, since the data is erased through the bulk 36, the problem of deterioration of the tunnel oxide film caused by the BTBT current is completely solved. In addition, since the surface of the substrate 10 is not exposed anywhere in the cell and the peripheral region but is placed under the wells, it is insensitive to contamination during the manufacturing process, thereby ensuring the operation characteristics of the transistors.

The stacked gate 55 of the cell transistors M1 and M2 and the gate 56 of the low and high voltage transistors 20, 21, 22, and 23 form the field oxide layers 40, 41, 42, and 43 on the well structure of the present invention. It is manufactured by a conventional manufacturing method.

The following is a description of how to manufacture the structure of Figure 5 shown in the above embodiment. 6 to 15 are diagrams for explaining a sequential fabrication process of manufacturing the well arrangement structure and transistors of the cell and the peripheral circuit region of FIG.

Referring to Fig. 6, it is seen that the oxide film 60 and the nitride film 62 are sequentially formed on the entire top 10 of the semiconductor substrate. This is preferably achieved by performing an oxide film depot process such that the p-type substrate 10 having a resistivity of about 5-18 OMEGA cm is subjected to an initial cleaning and having a thickness of about 300 kPa to 900 kPa on the top thereof, and depositing about 1000 kW of the nitride film 62. do.

Referring to FIG. 7, only a portion of the oxide layer 60 is exposed by masking only the nitride layer 62 placed over the portion where the wells are to be formed and etching the unmasked nitride layer, and then forming an N-type well through the exposed oxide layer 60. It is shown to inject N-type impurity ions such as phosphorus (Ph) into the substrate 10. This is performed by exposing and developing a photomask, for example, a photoresist, to form a pattern of the photomask 63 to form N-wells 30, 31, and 32 shown in FIG. 5, and then removing the nitride layer 62 of the exposed portion according to the pattern. It is achieved by dry etching and ion implantation of n-type impurities (Ph) with energy of 100 KeV to 200 KeV. Subsequently, when localization such as LOCOS and heat treatment, for example, drive-in of 1000 ° C. or more, first well 30 and first local oxide 64 are initially formed in the cell region as shown in FIG. 8. Second and third wells 31 and 32 and second and third local oxide films 65 and 66 are initially formed in the peripheral area, respectively. Here, the thickness of the local oxide films is preferably about 3000 kPa to 6000 kPa.

Referring to FIG. 8, after removing the nitride film 62 under the photomask 63 as a photosensitive film, implanting impurity ions, for example, boron B, for forming the wells into the substrate 10 through the exposed oxide film 60 is performed. appear. Accordingly, fourth and fifth wells 34 and 35 are initially formed with the second well 31 interposed therebetween. The P-type aliquot (B) is ion implanted with energy of 50 KeV or less over the entire upper portion. In this case, the local oxide films serve as an ion implantation blocking mask. Through the impurity ion implantation, P-Well 34 in which L.V.NMOS is formed is formed, and 5-well 35, which is a P well, is formed together. Thereafter, the first, second and third local oxide films 64, 65 and 66 and the exposed oxide film 60 used as masks for ion implantation are removed and the buffering oxide film 70 shown in FIG. 9 is formed. The membrane 70 acts as a buffer for high energy ion implantation, which is formed to a thickness of about 500 kPa or more through an oxidation process.

Referring to FIG. 9, it is shown that implanted impurity ions such as boron are implanted into the substrate 10 deeper than the depths of the first, second, and third wells 30-32 to prevent punchthrough. That is, for the anti punch through, ion implantation is performed to the entire upper portion at a high energy of 1 MeV or more, and the implantation is performed up to a depth of up to 72. By the above process, side diffusion between the wells 31 and 32 is prevented to ensure device isolation between the high voltage and low voltage transistors.

Referring to FIG. 10, the buffered oxide layer on the upper portion of the first and third wells is exposed in a pattern of a photomask 75 and the implanted impurity ions for forming the pocket wells, for example, boron, are less than the dose of the N well. It is shown to inject with energy of 80KeV or higher. Accordingly, a first pocket well 36 of FIG. 5 serving as the bulk region of the cell transistors M1 and M2 and a second pocket well 37 for accommodating the N-type transistors 22 of the high voltage transistors are initially formed. .

Referring to FIG. 11, a structure in which the wells 30-32, 36, 35, 34, and 37 are formed in a complete form by performing a high temperature heat treatment of at least 1000 ° C. is illustrated. The cell region is the H.V. PP wells 36,37, on which NMOSs are formed, and P wells 34, on which L.V.NMOS are formed, and N wells 31,32, on which L.V.PMOS and H.V.PMOS are formed, are completely formed.

The description below shows how to make the stacked gate 55 of the cell transistors M1 and M2 and the gate 56 of the low and high voltage transistors 20, 21, 22 and 23 shown in FIG. 5 in the well structure according to the present invention described above. It is to show.

In FIG. 12, an active region in which a transistor device is substantially formed and a field insulating film 40-43 of 4000 Å or more for device isolation are formed using a general LOCOS process. Afterwards, the cell region first forms a low tunnel oxide film of 80 kV to 100 kV to increase the efficiency of program and erase, and deposits POCL3 after deforming poly1 (first polysilicon) to be a material of the floating gate FG. A portion of the poly 1 on the field in the cell is etched to form the floating gate, and then an ONO film is formed in sequence.

In FIG. 13, anisotropic etching is performed by exposing the ONO film and the poly 1 of the peripheral circuit portion except the cell to the pattern of the photoresist layer 77 to form the transistors of the peripheral circuit portion. Thereafter, ion implantation is selectively performed to match the transistor threshold voltage in the peripheral circuit area, and selectively oxidizes the gate oxide film (80 kV to 150 kV) to be used for the transistor for operating at low voltage and the gate oxide film (200 kV to 350 kV) to be used for the high voltage transistor. It is also possible to deposit poly2 to be used for control electrodes of cells and peripheral circuits, deposit POCL3, and gate to polyside structures such as WSix for low polyresistance.

In FIG. 14, a cell having a floating gate FG and a control gate CG is formed by covering all peripheral circuit regions with a photo mask 78 and selectively covering the cell regions, and then etching poly2 or poly2, polyside, ONO, and poly1 in the cell region. Transistors M1 and M2 are formed.

In FIG. 15, all of the cell regions are covered with PR 80, and then the peripheral circuit regions excluding the cells are patterned, and poly2 or poly2 and polysides are selectively etched to form high voltage and low voltage transistors. Here, the processes of FIGS. 14 and 15 may be reversed to form a pattern of a peripheral circuit region first and then a cell pattern.

Through the process up to FIG. 15, the stack gate cells M1 and M2 of FIG. 5 including tunnel oxide 50 and poly 1 (51), ONO (52), and poly 2 (53) are formed in the cell region on the PP well 36. A low voltage gate oxide film 50, a high voltage gate oxide film 50, and a poly 2 (53) are formed in the peripheral circuit region, and a gate electrode 56 having a low voltage gate oxide film is formed on the P well 34 and the N well 31, The gate electrode 56 having the gate oxide film is formed in part of the PP well 37 and the N well 32.

5 is a cross-sectional view of a cell and a peripheral circuit portion that have undergone impurity ion implantation for complete formation of a transistor. In the case of cells and NMOS, the junction of the source and the drain region is formed through the en-ion implantation such as As and Ph, and in the case of PMOS, the source and the drain junction are formed through the implantation of the ion such as B and BF2.

In the case of cell transistors, the junction (junction) structure is a relatively high concentration region of N + to reduce the BTBT current at the source side and to increase the junction breakdown voltage at the source side junction in the case of conventional source erase. Although the N-DDD structure having a low and low concentration is used, in the present invention, since the substrate or bulk is erased, the junction of the conventional structure as well as the DDD and LDD are possible. Because there is a PP well in the enwell above the substrate to erase to the bulk substrate below the channel, when the positive voltage is applied to the bulk below the channel of the cell transistor, the leakage current to the substrate is reduced because the enwell and the substrate are reverse junctions. There will be no.

In the case of the CMOS operating at a low voltage to form a logic circuit among the peripheral circuits, the NMOS is formed in the pewell formed on the P-sub (formed substrate), and the PMOS is formed on the Enwell formed on the P-sub. The junction structure may use an LDD structure or a conventional structure to prevent punchthrough in a single channel. In the case of CMOS for applying positive or negative high voltage to the cell, the NMOS reduces body effect, maintains low threshold voltage, and compares with the Pwell formed on the P-Sub to prevent the negative voltage from escaping to the P-Sub. It is formed on a PP well in an enwell having a relatively low concentration, and in the case of PMOS, it is formed on an enwell. At this time, an enwell is charged with a positive voltage during operation of a circuit, so that a transistor operating at a low voltage constituting a logic circuit is formed. It should be isolated from the enwell. At this time, if used together without isolation, high voltage will escape. In addition, the junction used in the circuit for driving such a high voltage increases the breakdown of the junction at a high voltage by using DDD and LDD. Spacers may also be used in the formation of DDD or LDD junctions, and ion implantation may be performed before spacer formation and ion implantation after spacer formation to form junction structures such as DDD and LDD. After the formation of the junction is completed, deform the HTO and BPSG, perform BPSG reflow at a temperature above 800 ℃, form a contact between the metal lead and the junction, the metal lead and the poly electrode, and then form the metal lead. Connect the electrode and the metal lead.

As described above, according to the present invention, a problem of deterioration of a tunnel oxide film caused by BTBT current is solved, and a size of a cell transistor can be reduced, and insulation between wells surrounding the pocket well when a pocket well is manufactured in a peripheral region is provided. Characteristics are increased. In addition, it is easy to control the threshold voltage of the high-voltage en-type MOS transistor in the peripheral region relatively low, and there is a characteristic insensitive to contamination during manufacturing.

According to the present invention as described above, there is an effect that it is advantageous for high integration and device isolation, and the reliability of cell operation is improved.

Claims (4)

In the well structure of a nonvolatile semiconductor memory device: In order to program data by channel hot electron injection and erase by bulk region F-N tunneling, a cell region in which cell transistors forming a quinoa cell array structure is located; A first well formed in the substrate in a conductivity type opposite to that of the substrate, and a conductivity type surrounded by the first well to function as the bulk region of the cell transistors and the same conductivity type as the conductivity type of the substrate Consists of a first pocket well formed in A peripheral region in which the low voltage and high voltage transistors are electrically isolated from the cell area; Second and third wells separately formed on the substrate in a conductivity type opposite to that of the substrate for accommodating each of the low voltage and high voltage transistors, and an N-type transistor among the high voltage transistors; A second pocket well surrounded by the third well for accommodating the second well and formed of the same conductivity type as the conductivity type of the substrate, and the same as the conductivity type of the substrate for accommodating N-type transistors among the low voltage transistors. And a fourth well formed in the substrate between the first and second wells in a conductive type. The semiconductor device of claim 1, further comprising a fifth well having the same conductivity type as that of the fourth well to enhance the insulating property between the low voltage transistors and the high voltage transistors between the second and third wells. Well structure of a nonvolatile semiconductor memory device. In a nonvolatile semiconductor memory device for programming data by channel hot electron injection and erasing by FN tunneling through a bulk region, a well of a cell region in which cell transistors forming a quinoa cell array structure are located; A method for fabricating a well in a peripheral region in which low and high voltage transistors are located in electrical isolation from a cell region: Forming an oxide film and a nitride film on the entire upper portion of the semiconductor semiconductor substrate, and then masking only the nitride film placed on the portion where the wells are to be formed and etching the unmasked nitride film to expose a portion of the oxide film; After implanting the N-type impurity ions for forming the N-type well through the exposed oxide film into the substrate, local oxidation and heat treatment are performed to initially form the first well and the first local oxide film in the cell region. Allowing the second and third wells and the second and third local oxide films to be initially formed in the peripheral area at a distance from each other; After removing the remainder of the nitride film, implanting impurity ions for forming the wells into the substrate through the exposed oxide film to initially form the fourth and fifth wells with the second well interposed therebetween; ; After removing the first, second, and three local oxide films and the exposed oxide film and forming a buffering oxide film, implanted impurity ions are formed deeper than the first, second, and third wells to prevent punch-through. Injecting; A first pocket well serving as the bulk region of the cell transistors by exposing the buffered oxide film on the upper part of the first and third wells with a photomask pattern and implanting the dopant ions to form a pocket well; Initially forming a second pocket well for accommodating N-type transistors among the high voltage transistors; And performing a heat treatment to form the wells in a complete form. In the well structure of a nonvolatile semiconductor memory device: In order to program data by channel hot electron injection method and erase by FN tunneling method through a bulk region, a cell region in which cell transistors forming a quinoa cell array structure is located and a low voltage and a high voltage are isolated from the cell region. And a portion of the peripheral region in which the transistors are located is formed of a pocket well formed by a conductivity type opposite to the conductivity type of the substrate and formed in the same conductivity type as the conductivity type of the substrate.