TW457568B - Method for manufacturing a MOSFET having a T shape gate - Google Patents

Abstract

A method for manufacturing a MOSFET having a T shape gate is disclosed. The MOSFET is formed over a semiconductor chip that comprises a substrate and a dielectric layer disposed on the substrate. In the present invention, first, a conducting layer is deposited on the dielectric layer, and then a photoresist layer is formed on a predetermined region of the conducting layer for forming a predetermined gate region. An etching process is performed to completely remove the conducting layer disposed outside the predetermined gate region and etch part of the bottom of the conducting layer on the predetermined gate region for forming a substantial T shape gate conducting layer in the vertical profile. The present invention utilizes the differences of etching rate in the horizontal direction in the etching process or utilize the etching rate difference of the upper and lower layer of the conducting layer to form the T shape gate conducting layer. Thereafter, the photoresist layer is completely removed and an ion implantation is performed to form a source doped region and a drain doped region in both sides of the substrate of the gate predetermined region.

Description

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V. Description of the invention (1) I! Field of invention i! The present invention provides a method for manufacturing a MOS transistor, particularly a method for manufacturing an M 0 S transistor with a T-gate.

I: Background note i: i Metal-oxide-semiconductor (MOS) |: Transistors are the most important electronic components in today's semiconductor products. They are mainly used as switches in circuits. With the increase of the integration degree of integrated circuit (integrat 丨 on), the gate line width of M0S transistors has been gradually reduced |

Increasingly, the needs of body circuit designers are not enough, and it is necessary to further reduce the gate line width of M0S and transistors. i! | Please refer to Figures 1-3. Figures 1-3 are schematic diagrams of the conventional MOS transistor 1 0 i:. The conventional MOS transistor 10 is fabricated on a semiconductor wafer: 12 ', and the semiconductor wafer 12 includes a substrate 14, and an active area 16 is provided on a predetermined area on the surface of the substrate 14 | 'And a field oxide layer (fie 1 d ο X ide) 1 8 is provided on the surface of the substrate 14 and surrounds the active area 16 around. ; I

I! As shown in FIG. 1, a conventional method for manufacturing the MOS transistor 10 is to first form a gate oxide layer (gate OX) 2 0 on a semi-conductor wafer 12 with I: and a doped Polycrystalline stone evening layer 22. Then perform a lithography 丨 A3jB ^ g ____________________________________________ V. Description of the invention (2) The process, a _photo-resist layer 24 is formed on a predetermined area on the surface of the doped polycrystalline silicon layer 22 to define The position of a gate 2 6. As shown in FIG. 2, a dry etching process is performed next to vertically remove the doped polycrystalline silicon layer 22 and the gate oxide layer 20 which are not covered by the photoresist layer 24. After the dry etching process, the photoresist layer 24 is completely removed, and then an ion implantation process is performed. The doped polycrystalline silicon layer 22 and the field oxide layer 18 are used as a hard mask. Dopant is implanted into the substrate 14 not covered by the hard cover to form a heavi 1 y doped drain (HDD) 28 ° on each side of the gate 26, as shown in Figure 33 After the HDD 28 is formed, a spacer 30 is then formed around the gate 26. Then, an ion implantation process is performed, and the sidewall 30, the gate 26, and the field oxide layer 18 are used as another hard mask, and the dopants are implanted into the substrate 14 not covered by the hard mask, and Slightly doped; and a portion of the electrode 28 overlaps to form a source doped region 32 and a drain doped region 34 'on both sides of the gate 26 respectively. The fabrication of M0S transistor 10 is known. However, the width of the gate 26 of the M0S transistor 10 is getting smaller and smaller in order to improve the integration degree of the integrated circuit, and the current lithography technology limits the wide production; the gate below 0. 15 # m Pole making. In addition, the M0S transistor 10 ge 2 4 5 7 5 6 0 .......-............. · .-. _ V. Description of the invention (3) a ^ 6 / There will be an electrical effect between the source doped region 32 and the gate 26 / drain doped region 34 to reduce the operating speed of the jj〇s transistor 10 (〇perati〇s s + peed) . Therefore, in the production of smaller line width 'faster MOS transistor', the conventional MOS transistor 10 manufacturing method has its limitations and has become the bottleneck of the current semiconductor process development.

I; The main object of the present invention is to provide a method for manufacturing a MOS transistor with a τ gate, so as to improve the accumulation and operation speed of the MOS transistor. The invention provides a method for manufacturing a MOS transistor having a T-gate. The MOS transistor system is fabricated on a half-lead wafer. The semiconductor wafer includes a substrate and a dielectric layer disposed on a surface of the substrate. The method of the present invention first deposits a conductive layer on the dielectric layer, and then forms a photoresist layer on a predetermined area of the conductive layer to define a predetermined area of the gate. Subsequently, an etching process is performed to completely remove the conductive: layer outside the predetermined area of the gate, and to etch a part of the bottom of the conductive layer in the predetermined area of the gate, so as to form a gate conductive layer with a vertical cross section similar to a T-type. The method is to use the difference in the horizontal silver etch rate in the touch-etching process or the difference in the horizontal etching rate of the conductive layer to form the τ-type gate conductive layer. Then the photoresist layer is completely removed, and finally an ion implantation process is performed on the substrates on the two opposite sides of the predetermined area of the gate I-the source doped region and a drain 4 5 7 5 6 8 (4) Miscellaneous region 5 The MOS transistor of the present invention has the T-gate conductive layer, which can reduce the line width of the gate under the current: lithography technology to increase the accumulation of M0S transistors and Operating speed. Detailed description of the invention Please refer to FIG. 4 to FIG. 11. FIG. 4 to FIG. 11 are schematic diagrams of the manufacturing process of the MOS transistor 40 of the present invention. The MOS transistor 40 of the present invention is fabricated on a semiconductor wafer 42, and the semiconductor wafer 42 includes a substrate 44, an active area 46 is provided on a predetermined area on the surface of the substrate 4, and a field oxide layer 48 is provided on the substrate. The 4 4 surface surrounds the active area 4 6 and a gate dielectric layer 50 is disposed on the surface of the substrate 44. Layer one pre-charge or one. 6 interlayer 5-pole silicon surface-domain gate-gate surface area 2 The pre-push electrode method has been used for the first 5 layers, and the gate-side method has been implemented. The 52-step process is used to generate light. 4 This guide yellow 5 , A layer of 52 lines of resistance into the light after the four electricity picture a picture of the same. Si layer

As shown in FIG. 5 and FIG. 6, a first # engraving process is then performed to completely remove the conductive layer 5 2 outside the predetermined gate area 56 and etch the conductive layer 52 in the predetermined gate area 56. Bottom, and a vertical cross-section similar to a T-shape gate electrode (T-shape gate electrode) 58 ° is formed in the first 45756s five 'invention description ¢ 5) |: 1 photoetching process, and then the photoresist layer is completely removed 5 4.

There are two methods for forming the T-shaped gate conductive layer 58. The first method is to remove the conductive layer 5 2 outside the predetermined region 5 6 of the gate to a predetermined depth 60, and then adjust the etching machine by Settings, such as temperature, gas pressure, applied voltage, and wafer temperature, etc., to adjust the etching rate of the conductive layer 5 2 in the horizontal direction to completely remove the conductive layer 5 2 outside the predetermined gate area 5 6, and 1: chain engraving At the bottom of a part of the conductive layer 52 in the predetermined gate area 56, a T-shaped gate conductive layer 58 can be formed at the end. The second method is to first perform an anisotropic (a η 丨 s 〇tr 〇pic) surname engraving process, for example, a reactive ion etching (RIE) process is used to remove the predetermined gate area. 5 The outer conductive layer 5 2 is up to a predetermined depth 60. Then perform an isotropic (is ο ΐ r 〇 p i c) etching process, for example, a wet etching (wet e t c h i n g)!

Process to completely remove the conductive layer 52 outside the gate predetermined area 56 and etch back | the bottom of the conductive layer 5 2 in the gate predetermined area 56 is etched to form a T plastic gate I

极 conductive 层 58. I; Then, as shown in FIG. 27, a chemical vapor deposition (CVD) process or a high temperature thermal oxide (oxidation) process is performed to form an oxide layer on the exposed outer wall of the conductive tub 52. 62. As shown in FIG. 8, a second etching process is subsequently performed, such as a reactive ion etching (RIE) process. Then, it is completely removed 丨 jj 1 above the gate predetermined area 5 6 and gate predetermined The oxide layer 62 | 1 and the gate dielectric layer 50 outside the region 5 6. Residual in the T-gate conductive layer 5 8 The outer wall and bottom recess | 457568 V. Description of the invention (6) The oxide layer 62 in the depression can prevent the T-gate conductive layer: 5 8 and other conductors from short-circuiting, However, depending on the quality of the process, the manufacturing process of the oxide layer 62 can be cancelled. As shown in FIG. 9, after the oxide layer 62 is formed, an ion |: implantation process 6 4 is performed, and a source doped region 6 is formed in the substrate 4 4 on the opposite sides of the predetermined gate region 5 6. 6 和 一罐 极 多多 区 6 8。 6 and a drain doped region 68. The ion implantation process 64 is to implant ions into the substrates 4 4 on the opposite sides of the predetermined gate region 56 with a first incident angle, and the first incident angle is approximately perpendicular to the surface of the semiconductor wafer 42. In addition, before and after the ion implantation process 64, a separate sub-plantation process 70 may be performed to form an i-dual hybrid dopant in the substrate 4 4 below the T-type gate conductive layer 5 8 doped drain (HDD) 72 ° ion cloth: the implantation process 7 0 implants the ions under the gate conductive layer 5 8 at a second incident angle within the substrate 4 4, and the second incident angle is inclined to the semiconductor wafer Table 2 of 2: surface.

.. I 1.];! In addition, in addition to the ion implantation process 64 and the ion implantation process 72, an ion implantation process 74 may be performed according to the needs of the process. The ion implantation process 74 is to implant ions into the substrate 4 4 adjacent to the source doped region 6 6 at a third incident angle, respectively, to form two Pocket: the ion implantation region 76, and the third angle of incidence is inclined to the surface of the semiconductor wafer 42. The order of the foregoing three ion implantation processes and the second etching process can be reversed, i .: j ί, that is, the ion implantation process is performed first, and then the second touch process is performed.

Page 10 ^ 57568 ____________________________________________________...___________________________________ 5. Description of the invention ¢ 7) As shown in Figure 10, both the second etching process and the ion implantation process are completed; after that, a bond elimination (spu 11 ering) process is performed. A metal layer 78 is formed on the top of the T-shaped gate conductive layer 58, the surface of the source doped region 66, and the surface of the drain doped region 68 respectively. The sputtering process is a collimated sputtering process or an ion-metal-plasma (IMP); the base forging process = a high temperature process is performed after the sputtering process, so that the metal layer is within 7 8 Gold: the metal atom reacts with the substrate 44 or the silicon atom in the T-gate conductive layer 58 to: on the top of the T-gate conductive layer 58, the surface of the source doped region 66, and the dopant doped A self-aligned silicide (salicide) layer 80 ° is formed on the surface of each of the regions 6 and 8 as shown in Fig. Η. Finally, the unreacted metal layer 78 is completely removed to complete the M0S transistor. Making of 4 0. Please refer to FIG. 12 to FIG. 14, which are schematic diagrams of the manufacturing process of another embodiment of the MOS transistor 40 according to the present invention. In the foregoing embodiment, the T-gate conductive layer 58 is formed on the same conductive layer 5 2 by adjusting the isotropic etching rate. The second embodiment of the present invention uses two or more conductive layers with different properties to control the shape of the closed-electrode conductive layer under the same etching conditions. As shown in FIG. 12, a second embodiment of the present invention first deposits an upper conductive layer 4 5 7 ^ 6 8_: V. Description of the invention (8) = two m below the table, a conductive layer 52 b ′ 'upper conductive layer ... (Setching rate) is less than the lower conductive layer ... at a level .., .., for example, the upper conductive layer 52a is a metal silicide = the lower conductive layer is a stone-like conductive layer. / / Heteropolycrystalline silicon or amorphous silicon. In addition, the upper conductive layer ... and the lower conductive layer 52b may be the same as the conductive material, but the upper conductive layer, layer 02; a lattice structure is different from the lower hole conductive layer 5-hole lattice structure, or the upper conductive layer is conductive The doping concentration of the layer 5 2 a is different from the doping concentration of the lower conductive layer 5 2 b, so that the etching rate of the upper conductive layer 52 a in the horizontal direction is lower than the etching rate of the lower conductive layer 5 2 b in the horizontal direction. Next, as shown in FIG. 13, a first etching process is performed. First, the upper conductive layer 5 2 a outside the gate area 5 6 is removed vertically. Then, as shown in FIG. 14i, under the same etching conditions, the lower conductive layer 52b 'called the gate predetermined region 5 is completely removed and a part of the bottom of the lower conductive layer 52b in the gate predetermined region 56 is etched.成 τ 型 gate electrode conductive layer 58. Subsequent! Processes are described in Figures 7 to Η, so they are not repeated here. The MOS transistor 40 of the present invention is characterized by having a τ-type gate conductive layer: 5 8 ′, which can further reduce the gate line width under the current lithography technology, and advance to 1 to increase the accumulation on the semiconductor wafer. The MOS transistor 40 does not need to be fabricated on the side, and the fabrication of the oxide layer 62 can also be deleted, which can reduce the thermal budget of the process and enable the MOS transistor 40 to have better electrical performance. Even if the production of the oxide layer 62 is retained, since the ion implantation process can be performed after the oxide layer 4 5 7 5 6 8 ________; __ 5. Description of the Invention (9) 6 2 The ion implantation process can also be reduced. Thermal budget in a mixed area. In particular, for the heavily doped drain electrode 7 2 1 formed by the method of the present invention, it is at least one high-temperature oxidation process, which can accurately control the heavily doped drain electrode 7 compared with the conventional process of making sidewalls and then forming the heavily doped drain electrode 7 2 1. The change contour of 2 (pr 0fi 1 e). Compared with the conventional MOS transistor 10, the gate of the MOS transistor 40 of the present invention: the line width can be further reduced, and the integration degree of the integrated circuit is improved. In addition, the bottom of the T-gate conductive layer 58 of the MOS transistor 40 is concave, which can reduce the T-gate conductive layer 5 8 / source doped region 6 6 and the T-gate conductive layer 5 8 / i The capacitive effect between the drain-doped regions 68 increases the speed of MOS transistor operation. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

^ 57568 Brief description of the diagrams Brief description of the diagrams Figures 1 to 3 are schematic diagrams of a conventional MOS transistor 10 manufacturing process. FIG. 4 to FIG. 11 are schematic diagrams of the manufacturing process of the MOS transistor of the present invention. Figures 12 to 14 are schematic diagrams showing the manufacturing process of another embodiment of the MOS transistor of the present invention. =: Symbols shown in the figure 10 Known MOS transistor 12 Semiconductor wafer 14 Substrate 16 Active area 18 Field oxide layer 20 Gate oxidation Layer 22 Doped polycrystalline silicon layer 24 Photoresist layer 26 Gate 28 Heavily doped drain 30 Side wall 32 Source doped region 34 Drain doped region 40 MOS transistor 42 Semiconductor wafer 44 Substrate 46 Active region 48 Field oxidation Layer 50 Gate dielectric layer 52 Conductive layer 52a Upper conductive layer 52b Lower conductive layer 54 Photoresist layer 56 Gate predetermined area 58 T-gate conductive layer 60 Predetermined depth 62 Oxide layer 64 Ion implantation process 66 Source doping Region 68 Drain Doped Region

Page M 457565 Brief description of the diagram 70 Ion implantation process 74 Ion implantation process 7 8 Metal layer 72 Heavyly doped drain 76 Pocket ion implantation area 8 0 Self-aligned metal silicide layer

Page 15

Claims (1)

457568 VI. Application for patent scope 1. A method for manufacturing a MOS transistor with a T-type transistor, the MOS transistor system is fabricated on a semiconductor wafer, the semiconductor wafer includes a substrate and a dielectric layer is provided on the substrate On the surface, the method includes: depositing a conductive layer on the dielectric layer; forming a photoresist layer on a predetermined area of the conductive layer to define a predetermined area of the gate; performing a first etching process, completely Remove the conductive layer outside the predetermined area of the gate electrode, and etch the bottom of the conductive layer in the predetermined area of the gate electrode; and form a gate conductive layer with a vertical cross section similar to that of the gate; completely remove the photoresist layer; And a first ion implantation process is performed, and a predetermined region of the gate is opposite: a source doped region and a drain doped region are formed in the substrates on both sides, respectively.丨 2. As in the method of claim 1, the first etching process uses the etching rate in the horizontal direction to adjust the bottom of the conductive layer in the predetermined region of the gate electrode to form the vertical section. For T type: open electrode conductive layer. ： 3. The method according to item 1 of the scope of patent application, wherein the first etching process includes the following steps: An anisotropic (anis 〇tr 〇pic) money engraving process is performed to remove the gate electrode. The conductive layer outside the area is up to a predetermined depth; and I is subjected to an isotropic (is 〇tr 〇pic) engraving process, and the bottom of the conductive layer in a predetermined area of the gate is etched inward, so that the cross section is approximated. T-gate P.16 45 7 5 6 8 ____________ ______________________________________________ I Six 'scope of patent application I |: conductive layer. 4. The method according to item 1 of the scope of patent application, wherein the method further comprises the following steps after removing the | photoresist layer:; I performing a chemical vapor deposition (CVD) process, in An oxide layer is formed on the exposed outer wall of the conductive layer; and a second etching process is performed to completely remove the oxide layer and the dielectric layer above the predetermined area of the gate and outside the predetermined area of the gate. : 5. The method according to item 1 of the patent application scope, wherein the method further comprises the following steps after removing the photoresist layer: 1; performing a high temperature thermal oxidation process, and exposing the outer wall of the conductive layer An oxide layer is formed thereon; and I: a second etching process is performed to completely remove the oxide layer and the dielectric layer above the predetermined area of the gate and outside the predetermined area of the gate. I 6. The method according to item 1 of the patent application range, wherein the first ion implantation ^: i: the process is to implant ions at a first incident angle into a predetermined area of the gate opposite to each other: inside the substrate on both sides, The first incident angle is approximately perpendicular to the surface of the semiconductor wafer.丨 I! 7 · The method according to item 1 of the patent application scope, wherein the method is completely removed; in addition to the photoresist layer, a second ion implantation process is performed to form two in the substrate below the interlayer conductive layer. Heavily doped 笫 πPage 457568! 6. Patent application scope drain, HDD) ° 8. If the method of patent application item No. 7 is adopted, wherein the second ion implantation process implants ions into the gate electrode at a second incident angle to conduct electricity In the substrate below the layer, the second incident angle is inclined to the surface of the semiconductor wafer. 9. The method according to item 1 of the patent application, wherein the method further comprises a third ion implantation process with a third entrance after the photoresist layer is completely removed; the ions are implanted in the vicinity of the source electrode and doped separately. The bottom of the impurity region and the substrate adjacent to the bottom of the drain: doped region form a two-pocket ion implantation region, and the third incident angle is inclined to the surface of the semiconductor wafer. 10. The method according to item 1 of the patent application scope, wherein the method further comprises the following steps after the first ion implantation process: removing a dielectric layer outside a predetermined area of the gate; and performing a sputtering ) Process, a metal layer is formed on the top of the gate conductive layer, the surface of the source doped region and the surface of the drain doped region. 11. The method as claimed in claim 10, wherein the method is followed by the sputtering; the process further includes the following steps: a high temperature process is performed to the top of the gate conductive layer, the source doped region; A self-aligned silicide (salicide) layer is formed on the surface and the surface of the drain doped region; and Page 18 457568 6. Scope of patent application Complete removal of unreacted metal layer. i 2. The method according to item 10 of the patent application scope, wherein the sputtering process is a collimated sputtering process or an iometal-plasma (IMP) hidden bond process. 1 3. The method according to item 1 of the patent application, wherein the conductive layer is a doped polycrystalline silicon layer or an amorphous silicon layer. 14. The method according to item 1 of the scope of patent application, wherein the conductive layer includes an upper conductive layer and a lower conductive layer, and the upper conductive layer has a lower etching rate in the horizontal direction than the lower conductive layer. Section i C. Fan Fan. 1 Sb is next to the special C article. The gold layer 5 1 is a conductive layer and the conductive layer is an upper layer and the middle layer is electrically conductive. The lower method is the other and the item layer is 4 N1 / 1 6. If the method of item 14 of the scope of patent application, The lattice structure of the upper conductive layer is different from that of the lower conductive layer, so that the etching rate of the upper conductive layer in the horizontal direction is lower than that of the lower conductive layer. j 7. The method according to item 14 of the scope of patent application, wherein: the impurity concentration of the upper conductive layer is different from the doping concentration of the lower conductive layer, so that the upper conductive layer: the etching rate of the layer in the horizontal direction is less than the lower layer Conductive layer. Page 19 457568 VI. The patent application scope of the method of the layer of electric conductance gate gate and the above-mentioned negative film integrated crystal are: the guide contains a semi-contained piece encased in the crystal seed body, one guide the half, 8 1 the top of the bottom Base Xuan--D The layer dielectric is set to block the light 1%, and the electrical domain conduction area 1 on the shape layer is set to pre-sink one layer above; the electrical domain conduction area should be located in the prepolar gate. S to 1: μρ l · * πν of a laminar electrical guide, etc. A certain line of pre-advance pole gates in the first region of the field = ° Excluding the process etch and the depth of the pre-cut profile i # 直 ο and vertical rt, 〇S " 成 • 1 丨 the electrical shape leads to it, waiting for the outer field to distinguish between the bottom line and the predetermined part. The 1NJ surname of the polar layer system is similar to that of the gate near the gate. ^ F divided by t pole ^ ^ ^, 1 of the -domain%. 9. If the method of item 18 of the scope of patent application, the method is used in After the photoresist layer is completely removed, the method further includes the following steps: forming an oxide layer on the exposed outer wall of the conductive layer; and performing a second anisotropic engraving process to completely remove the gate over the predetermined area And an oxide layer and a dielectric layer outside the predetermined area of the gate. 20. The method of claim 18, wherein the conductive layer is a doped polycrystalline silicon layer or an amorphous silicon layer. Page 20 4—57—56.1- ___________________________— One _____________________________________________________—————————————————————————————————————————————————————————————————————————————————————————— 6. Applicable patent scope: 2 1. If the method of item 18 of the patent application scope, the conductive layer contains ί : An upper conductive layer and a lower conductive layer, and an etching rate of the upper conductive layer in a horizontal direction is smaller than that of the lower conductive layer. 22. The method according to item 21 of the scope of patent application, wherein the upper conductive layer is a silicide layer, and the lower conductive layer is a stone conductive layer. 1 i; 2 3, as in the method of claim 21 in the scope of patent application, wherein the upper conductive layer has a lattice structure different from that of the lower conductive layer to make the upper conductive layer 丨: etching of the layer in the horizontal direction The rate is less than the underlying conductive layer. : 2 4. The method according to item 21 of the scope of patent application, wherein the doping concentration of the upper conductive layer is different from the # impurity concentration of the lower conductive layer, so that the etching rate of the upper conductive layer in the horizontal direction is lower than that of the lower conductive layer. Floor.